DE2321268A1 - CIRCUIT ARRANGEMENT FOR GENERATING A SYNCHRONOUS PULSE SEQUENCE - Google Patents

Description

Circuit arrangement for generating a synchronous clock pulse sequence The invention relates to an arrangement for generating a synchronous clock pulse sequence ge for the recovery of a current information signal from a digital one Two-phase carrier signal that is used for data processing by logically combining the Information signal and the clock pulse train was generated.

It is common in data processing, for example in data preparation or during data transmission, the digital information signals on a data carrier to be imprinted A frequently used data carrier is the so-called two-phase carrier signal (bi-phase level - Si.onal), which is made up of a logical combination of a clock pulse sequence with the actual information signal, which is often also called the NRZ-L signal (non-return to zero level) results.

This two-phase carrier signal is particularly useful in telemetry.

data security and wired data transmission used.

About the actual information content, that is, the 'NRZ-L signal from the two-phase carrier signal, it is necessary to recover this signal to be linked with a pulse train synchronous to the original clock pulse train. This requires for example in data transmission and in telemetry the receiving side a corresponding effort to the clock pulse train again produce. So far this has been done with the help of an oscillator and a synchronization unit realized, so that this requires a considerable amount of effort. Despite this However, the synchronization is only complex to the two-phase carrier signal and thus only indirectly possible, which is not without repercussions on the recovery of the Information signal remains.

The invention is therefore based on the object of a circuit arrangement to provide, with which it is possible without great effort, a clock pulse train directly from a two-phase carrier signal. According to the invention, this is on Gabe solved in that the two-phase carrier signal and an inverted two-phase carrier signal to generate a pulse train are logically linked and that of this Pulse sequence The clock pulse sequence is derived by shaping certain pulses is.

By combining the two-phase carrier signal and one derived therefrom inverse two-phase carrier signals it is possible to obtain a pulse train the pulses of the clock pulse rate and twice the clock pulse rate contains. Au-s this pulse train can be doubled by suppressing the pulses Clock rate and subsequent pulse shaping without great effort original clock pulse train synchronous pulse train are generated.

Further details of the invention are based on one in the enclosed Drawing illustrated embodiment. explained in more detail. They show: figure 1 shows a block diagram and FIG. 2 shows a pulse diagram of the received two-phase carrier signal which is designated with a in the pulse diagram, is available at input terminal 10.

From there, this two-phase carrier signal went to one on the one hand monostable multivibrator 11 and on the other hand via an inverter 12 to another monostable multivibrator 13. The inverted two-phase carrier signal is in the pulse diagram denoted by b. Both multivibrators 11, 13 are dimensioned so that their duty cycle at most a value of 25 ço of the clock pulse period and thus each emit a pulse train of needle pulses labeled c or d. These two Needle pulse trains are linked in a NOR gate 14, so that this NOR gate creates a pulse sequence designated with e, which pulses of the Taktsequcnz and twice the clock rate. To suppress the impulses double The pulse sequence that can be taken from the output of the NOR gate 14 is the pulse sequence passed through a monostable multivibrator 15 whose duty cycle is 75 % of the clock pulse period. The output of this monostable multivibrator 15 a pulse sequence denoted by f can thus be taken which only contains pulses contains the clock rate. This pulse train is via another monostable Multivibrator 16 passed, whose duty cycle is exactly half the period of Clock pulse repetition frequency is measured. At the output of this monostable multivibrator 16 is thus a pulse train g available that is synchronous to the original Clock pulse train runs.

The clock pulse sequence g generated in this way is used for recovery in a known manner of the NflZ-L signal fed to an input of an exclusive OR gate 17, the at a second input from the input terminal 10 receives the two-phase carrier signal. From the output of this or »gate 17, the previously impressed on the transmitting side can thus NRZ-L signal can be extracted The recovered NRZ-L signal labeled h however, it is not free from needle-shaped indentations and is therefore suitable for further processing not yet suitable. Therefore, the one at the exit of the Exclusive Oder-Ciatter 17 can be taken NRZ-L signal further processed.

For this purpose, the generated clock pulse train from the output of the monostable multivibrator 16 tapped and on the one hand a monostable multivibrator 18 and on the other hand via an inverter. 19 another monostable multivibrator 20 supplied, the duty cycle of both multivibrators 18, 20 are respectively 25 O / o of the clock pulse periodc measured. In the pulse diagram, the pulse trains are behind the inverter 19 with i, behind the monostable multivibrator 20 k and behind the monostable multivibrator 18 denoted by 1. The output pulse trains of the monostable Multivibrators n8, 20 are linked in a NOR gate 21, so that a Pulse sequence m twice the clock rate results. This pulse train m is a Input of a one-bit viewing register 22 fed to a second input the clock pulse sequence inverted by the inverter 19 receives. The input of this shift register 22 a pulse sequence n of the clock rate can thus be taken, but with one Phase shift of 25% of the clock pulse period. When comparing the impulse sequences This can be clearly seen in g and n. The phase-shifted clock pulse train generated in this way n is fed to a one-bit shift register 23 which is an. a second entrance that The output signal of the OR gate 17 is received. At the output of this shift register 23 a flawless NRZ-L signal can now be taken, which compared to the phase shift of 25% at the output of the OR gate 17 the Clock pulse period has-.

The circuit arrangement according to the invention is characterized by a simple structure in the recovery of the clock pulse train without assistance an external frequency and a synchronization unit. Phase shifts between the two-phase carrier signal to be processed and the clock pulse train do not arise because the clock pulse train is derived directly from the two-phase carrier signal will.

With the help of the circuit arrangement according to the invention, it is possible to generate a clock pulse sequence that after the first bit (start bit ^ NRZ-L change) supplies a synchronous clock pulse, so that on expensive synchronization units can be dispensed with.

The invention therefore enables data transmission links to be set up (Telemetry or wired transmission routes) on which information is not can only be transmitted continuously, but also in the form of short data words.

- patent claims -

Claims (3)

P a t -e n t a n s p r ü c h e 1.) Circuit arrangement for generation a synchronous clock pulse train for the recovery of a digital information signal from a digital two-phase carrier signal, which is used for data processing by logical Linking the information signal and the clock pulse sequence was generated thereby G e k e n n n z e-i c h n e t that the two-phase carrier signal (a) and an inverted Two-phase trigger signal (b) for generating a pulse train e) logically with one another are linked and that of this pulse sequence (s) by pulse shaping Pulses the clock pulse train (g) is derived. 2.) Circuit arrangement according to claim 1, characterized in that g e k e n n -z e i c h n e t that the two-phase carrier signals (a, b) each have a monostable k5ultivibrator (11, 13), the duration of which is switched on to a value of less than 25 so the clock pulse period are dimensioned to two inputs of a NOR gate (14) are routed, the output of which is a pulse train (s) with pulses of the clock rate supplies. 3.) Circuit arrangement according to claim 1 or 2, characterized g e -k e n n e i c h n e t that the pulse train (s) for the suppression of pulses doubled Clock rate over a duty cycle of 75% of the clock pulse period set monostable multivibrator (15) to another monostable multivibrator (16) is passed, its duty cycle to generate a symmetrical clock pulse sequence (g) is measured at half the period of the clock pulse frequency.