DE2304005C3 - Transversal filter - Google Patents

Description

Fit? 4 a third embodiment and

Fig. 5 a fourth ΛικΓύηηΗ ^ ίοπη of the transversal filter * according to the invention.

The transversal filter according to FIG. 1 contains a number of storage elements E ₀ . E ₁ . E ₁ . E _} and £ ₄ . S Pie capacities of adjacent storage elements are via a charge transfer circuit. which is formed by the source-drain corner of a field effect transistor, connected to one another. The source-Efcktrode of the transistor T ₀ is via the series connection of the drain-source path of a transistor 7 ″, the resistor R ₀ md of the input signal voltage source V with a point constant Between the drain electrode of the transistor T and its gate electrode there is the capacitance C. The gate electrode of the transistor T is connected to the clock pulse generator 1. The transistor T. the capacitance C and the resistor R ₀ form one so-called η read circuit for the shift register formed by the memory elements. The capacitance C ₄ is connected via the source-drain path of a transistor T ₅ to the clock pulse conductor a_ , which is connected to an output of the clock pulse signal source _{S 0} between the source electrode and the gate electrode of the field effect transistor of the memory element concerned ents appropriate. The gate electrodes of the transistors T 0 T _{4 of} the memory elements E _{1, E 4 also} form the control electrodes of the memory elements. The control electrode 1 of the storage element E ₀ is connected to the current input of the current dividing device I. The current output 2 of the current divider device 1 is connected to the conductor c; connected, while the Stromauseang 3 is connected to the conductor / ^ ν. _{The source-drain path of the transistor T 00 is} attached between the current input and the current output 2 of the current conductor _{device I. The source-drain path of the transistor T m} is located between the current input and the current output 3 of the current divider device I. The control electrode 21 of the storage element E ₂ is connected to the current input of the current dividing device II. The current output 22 of the current dividing device II is connected to the conductor χ, while the current output 23 is connected to the conductor ^). The source-drain path of the transistor T _{20 is} attached between the current input and the current output 22. _{The source-drain path of the transistor T 2} is located between the current input and the current output 23. The control electrode 41 of the storage element E ₄ is connected to the current input of the current dividing device III. The current output 42 is with the conductor_c and the current output 43 with the conductor h. connected. _{The source-drain path of the transistor T 40} lies between the current input and the current output 42 of the current divider device III. _{The source-drain path of the transistor T 41} is located between the current input and the current output 43 of the current divider device III. The gate electrodes of the field effect transistors of the current dividing devices are connected to outputs of a setting register P. The conductors b and _c are each connected to an input of the differential amplifier SV. The mode of operation of the transversal filter is as follows:

In the time intervals r ,, r, ■ · -, the F i 2. 2 new information about the size of the F. input signal V is stored as a charge in the capacitance C. The information stored in the even numbered capacities C ₀ and C ₁ is shifted to the odd numbered capacities C 1 and C 1. where in the mentioned time intervals the even numbered capacities C ₀ . C. and C ₄ cite such an amount of charge that the charge in these capacitances becomes equal to the reference charge, and / was (E - Vj C Coulomb, where £ represents the amplitude of the clock signal and Ki represents the threshold voltage of the field effect transistors used. The currents , which flow through the source-drain paths of the transistors T _1, 7 ₃ and 7 ~ _{5 in} the specified intervals, also flow through the current divider devices I. II and III A simple calculation shows that the currents which flow through the various source-drain paths of the field effect transistors of each of the current dividing devices I., II and III, correspond to the following relationships:

I, η ⁼

I, ι =

i = ', ο *' vi · χ = 0. 2. 4.

(D (2)

In these relationships, V _{x is} the voltage at the current input of the current dividing device under consideration. (V + Y _x ) and [VY _x ) are the voltages output by the setting register P , V _d is the threshold voltage of the field effect transistors used, and ft is a factor which is determined by the material and the geometry of the field effect transistors. From the relationships (1) and (2) it follows that the differential current

(5)

is. It is assumed that ^ V _x with respect to

the voltage [V - V _ä ) is negligible, which in practice will mostly be the case. From relation (5) it follows that

(6)

where Q _{x is} the charge from the storage level χ in question, which is transferred to the adjacent storage level. The total difference in charge which flows over the conductors b and £ in a certain time interval τ becomes the same

(7)

being. Assuming that the signal supplied from the signal voltage source Vj has a spectral component having an angular frequency w and a

UUO

Amplitude contains λ, can be used for existing in the capacitance C charge Q ₀ r ₀ in the time interval are written in complex form:

C- W -e "".

and E ₄ the relevant spectral component is shifted further over time intervals τ, 2 r, 3 τ.

For the charge Q ₁ and ζ | present in the capacities C ₂ and C _{4 4} can be written in a complex form:

C- IKe ¹

C- W e

/ H (I - 4 T)

where C is the capacitance value of the storage capacities C ₀ -C ₄ and I V is the amplitude A of
considered spectral component is proportional. Applying the above in relation to the successive storage levels E ₁ , E ₃ 10 hung (7) results

(8th)

Any special component C-II 'e'"'in the frequency spectrum of the signal fed to the capacitance C ₁₁ supplies an output signal as in (8), so that the following applies to the transmission characteristic H (\\) de: device according to FIG.

(9)

where α, = Y ₀ - {VK) ', O ₂ = Y ₂ (VV ₁₁ ) ¹ , b _x = Yt (VV ₁ ,) - ¹ . Any desired amplitude-frequency characteristic and also any desired phase-frequency characteristic can be achieved by suitable selection of the transfer coefficients a ,, <i _{2 ... />, ... (also referred to as weighting factors) ".}

Since the setting means 1 and II of the transversal filter according to FIG. 1 _{are arranged in series with the capacitors C 0} and C _2, no charge is lost when information is transmitted between the capacitors C ₀ and C ₁ , C ₂ and C _3. The consequence of this is that the number of storage elements that can be accommodated in the row is not restricted by the attachment of said setting means. A large number of storage elements can therefore be connected in series, as a result of which a large number of coefficients a _t ... etc. can be obtained. In addition, the weighting factors can now be set independently of one another.

When deriving the formula (5) it is assumed

men that the voltage 3 V _{x is} negligible.

This neglect causes an error of about 2% in the weight factor if all field effect transistors are the same size. If you want to work very precisely, the influence of the 5 V _x voltage can be greatly reduced. So z. B.

in the odd time intervals T ₁ ..., during which information is written into the capacitance C ₀ , the voltages (V + Y ₀ ) and (VY ₀ ) to the values shown in FIG. 1 are supplied to the current divider device I, while in the subsequent even time intervals T ₂ ... the voltage (F - lo) of the gate electrode of the transistor J ^ ₀ and the voltage (F + iy of the gate electrode of the transistor T _m was fed This is also done Ηώ the voltages (F -I- T ₂ MV Y ₂₎ and (V + Y _11). (B - II). iur the Strontfeflervorrichrnngen Π and III By iTerwecbsüing adds adjustment is te of Fields averagedL It has been shown that the

remaining errors infoige of ^ V _x only 1%

This can also be achieved by using the 6s ladder A ** d . £. alternately mk of the ice drifts s tiad * · of the DüfeBBaverstaifeeis SF, in ^ effinterwäil% the leäer j? with the input s and the conductor x with the input r and in the time interval τ _{2 of} the conductor J> with the input r and the conductor_c with the input s. This measure also averages out the error.

In the exemplary embodiment according to FIG. 3, it is indicated on the one hand how the setting register P can be implemented and, on the other hand, how the differential amplifier can be implemented. Furthermore, the gate electrodes of the transistors T ₀ , T ₂ and T _{4 are} connected to the clock pulse conductor ^ instead of to the current inputs of the current dividing devices I, II and III. The latter has the advantage that a faster signal transmission between the capacities is possible. The differential amplifier contains the differential amplifiers A and B, each of which has one input connected to ground. The other input of the amplifier A is connected to the output X of this amplifier via the capacitance C _A. The other input of the amplifier B is connected to the output Y of this amplifier via the capacitance C _8. The capacity value of the capacities C _A and C ₈ is many times greater than the capacity value of the storage capacities C ₀ -C ₄ . Between the outputs X and Y , Σ I Q _{x is} measured according to formula (8). This is also the output signal of the transversal filter. The setting register contains two delay circuits. The first delay circuit contains the field effect transistors T ₆ -T _n , the source-drain paths of which are connected in series with one another. Between the drain electrode and the gate electrode of each of these transistors there is a capacitance with the same rank as the respective transistor, with the exception of the transistor T ₁₁ , the drain electrode of which is connected to its gate electrode. The second monitoring circuit includes the transistors T ₁₂ -F ₁₇ , whose source-Draifl path are also connected in series with one another. The gate 3ektr £ © de NND between the drain electrode of each of these transistors is & m KapastMt ίαώ Rangnununer same as the transistor "in question mounted, with the exception of the transistor T ₁ - ,, whose drain nut its gate ^ ElektPode is connected. The gate electrodes of the transistors a %, ??> T _n , T ₁₃ , T ₁₅ and T "sinilati ground, i & äiitmA the gate electrodes of the transistors%,% 3" * Tu, T ₁₄ and T ₁₆ with the output rf of the ScfaaiBjjaflnungsquelle S ₀ are connected. the Orain-ElektriHie of the transistor T ₆ is fiber of the resistor A ₁ "Φ

3615 ■ - »

the signal voltage source ν; connected. The source electrode of the transistor T ₁₂ is connected to the signal voltage source Y _{1 via the resistor R 2} ^m ' ¹ . The signal voltage source Y 1 is also connected to a point of constant potential via a DC voltage source 100.

The setting register P can be operated in various ways. Before the input signal to be filtered is _{fed to the first transistor T 0} , the setting signals (V ± Y _x ), where χ = 0, 2, 4, can be generated with the aid of the switching voltage _{source S 0} and the signal source r]. can be stored in the setting register P. Furthermore, instead of set weighting factors, variable weighting factors can also be selected. This can e.g. B. be educated by the fact that in the time intervals in which information transfer takes place between adjacent storage capacities, the previous time intervals in the setting register P setting voltages are shifted by one or more places in the register. When digital signals from the transversal filter of FIG. 3, instead of the analog shift register shown in this figure, a digital shift register composed of bistable elements can be used as the setting register P.

F i g. 4 shows that instead of the memory stages shown in FIG. B. E ₂ , other storage runs can also be used. The memory stage contains the transistor T ₂ and the capacitances C ₂ , C ₂₂ , C ₂₄ and C ₂₆ . The capacitance C ₂ is attached between the gate electrode and the drain electrode of the transistor T _2. The gate electrode of transistor T ₂ is connected to the current input of the _{current divider device formed by transistors T 20} and T ₂₁ , the current outputs of which are connected to conductors c_ and b . The capacitance C ₂₂ is connected to the current input of the current divider device formed by the transistors T ₁₂ and T ₂₃ , the current outputs of which are connected to the conductors _c and b_, respectively. The capacitance C ₂₄ is connected to the current input of the _{current divider device formed by the transistors T 24} and T ₂₅ , the current outputs of which are connected to the conductors £ and b_ . The capacitance C ₂₆ is connected to the current input of the _{current divider device formed by the transistors T 26 and} T ₂₇ , the current outputs of which are connected to the conductors c_ and b . The capacity value of the capacities C ₂ . C ₂₂ , C ₂ A- C ₂₆ and C ₃ is e.g. B. C, 2 C, 4 C, 8 C and 15 C [Coulombs]. The digital signals F ₁ and F ₁ are fed to the gate electrodes of the transistors T ₂₀ and T ₂₁ with the aid of a first setting register (not shown). The gate electrodes of the transistors. T ₂₂ and T ₂₃ , the digital signals F ₂ and F ₂ βώ are supplied with the help of the second (not shown) setting register. The gate electrodes of the transistors T ₂ ^ and T ₁₅ are supplied with the digital signals F ₃ and F ₃ with the aid of a third setting register (not shown). The digital signals F ₄ and F ₄ are fed to the gate electrodes of the transistors T ₂₆ and T ₂₇ with the aid of a fourth setting register (not shown), depending on the digital signal (0 or 1). that is fed to the said Tramptors, the transistor in question will be nonconductive or conductive. Since four flow divider devices are used in the filter according to FIG. 4, the number of possible values that the relevant weighting factor can assume is 2 * = 16. In this way the following values can be achieved:

1, 13/15, 11/15, 9/15, 7/15, 5/15, 3/15, I / 15 - 1/15, -3/15, -5/15, -7/15, - 9/15, -11/15 -13/15. -1.

The four setting registers mentioned can be conventional digital shift registers of the static type. This means that the information written in such a shift register can be retained indefinitely, in contrast to the setting register P according to FIG. 3 of the dynamic type. The latter means that the information written in such a register is lost after a certain time due to the discharge of charge from the storage capacities. With the transversal filter according to FIG. 4, both analog and digital signals can be filtered.

In Fig. 5, an embodiment is shown in which other flow dividing devices are used. In the current divider device 1, the source-drain path of the additional field effect transistor T ₀ 'is attached parallel to the source-drain path of the field effect transistor T _00. The source-drain path of the additional transistor T ₁ 'is attached parallel to the source-drain path of the transistor T _01. The gate electrodes of these additional transistors are connected to the current input of the current dividing device 1. In the current dividing device II, the source-drain path of the additional transistor T _{2 is} attached parallel to the source-drain path of the transistor T _20. The source-drain path of the additional transistor T _{3 is} attached parallel to the source-drain path of the transistor T _21. The gate electrodes of the additional transistors are connected to the current input of the current dividing device II.

Attaching the additional field effect transistors T ₀ ', T ₁ ', T ₂ ', T ₃ ' in the relevant current divider device has the advantage that the resistance characteristic of the associated field effect transistor is linearized. The resistance characteristic of the field effect transistor T ₀₀ is approximately formed by the sum of a linear and a square part, while the resistance characteristic of the transistor Tq is approximately formed by the difference between a linear and a square part. This means that the resistance characteristic of the combination of the field effect transistors T ₀₀ and T _{0 will have} a greater linearity than the corresponding characteristic of the transistor T ₀₀ , because the square parts of the two field effect transistors will equalize each other. A simple calculation shows that this match is optimal if it is ensured that the following relationship applies:

Zq- Σ-Ν
CL

In this regard, ß _t a factor which is determined by the material and the geometry of the transistor T _m, whereas ß ₂ is a similar factor of the transistor! £, Σ is the dielectric constant of the Süizhnns, C 'the capacity of the OberSächeneinheii

€ 09631/217

of the gate electrodes of the transistors, V "is equal to the sum of the voltage between the source electrode and the substrate of the transistor T ₀₀ and the voltage between the drain electrode and the substrate of the transistor T ₀ ', <I> _F die Difference voltage between the Fermi level and the intrinsic Fermi level. N is the doping concentration and £ / is the elemental charge of an electron.

10

The shift registers used in the embodiments are implemented with field effect transistors. It is clear that the shift register z. B. also on the in the Dutch patent application 71 14 770 described manner can be carried out. The shift registers can also access the z. B. in "Electronics" from June 21, 1971, pp. 50 to 59, be carried out as described.

For this purpose 3 sheets of drawings

3

Claims (3)

Capacities of a storage element over an L; Claims: transmission transmission circuit is coupled to the capacity of a fo - »ending storage element and di 1. Transversal filter which contains a series of storage clock pulses to the control electrodes of the storage elements, each with a capacity and a 5 element to control the charge transfer between the control electrode, in which each of the capacities is transferred via the above-mentioned overload circuits to a storage element a country-coupled capacitors are fed to the transmission transfer circuit with the capacity of one and at least a number not next to each other in the following memory elements and the lying memory stages are coupled to the control electrodes of the memory factors with an adding element for controlling the Charge transfer which adds the signals fed in the storage elements over a respective time interval between the capacitances further coupled to one another via the above-mentioned upper charge circuit feed period and which are adjustable, and at least one A number of non-additional weighting factors through flow divider devices with interconnected storage stoves via one part i ₅ one current input and two current outputs below; bare weighting factors are coupled with an adder using a field effect transistor and a tuna, which are implemented in the memory element high-ohmic resistance,
elements each over one of the feed period Em transversal filter with such current divider The corresponding time interval for devices is known from "IEEE Transactions on Si, aiale added, and the adjustable weight 20 Communication Technology", February 1970, p. 6, factors through flow dividing devices with FIG. 1 and p. 9, FIG . In this known current input and two current outputs, the taps of the filter are measured with the help of the taps of the filter using a field effect transistor and applied current divider circuits, and these are characterized by the fact that the voltages are measured with the aid the avoidance associated with the current-in-current divider devices (I, II. III) in the past of the current divider circuits, which converts resistances into currents, which are difficult for circuit integration. The above realizable high-resistance resistors each have a high resistance value, _{contain two field effect transistors (T 00} -T ₄₁ ), so the known current divider circuits do not have their source electrode with the current input 30 suitable for integration in a semiconductor of the current dividing devices and their drain bodies . Electrodes each with a current output of the next is in the known current divider circuits Current dividing devices are connected and both the impedance at the drain electrode of the field effect The control electrodes of the field effect transistors depend on the voltage at the branch the current division determining control voltage 35 point of said resistor. This will cease. caused by the fact that in the known 2. transversal filter according to claim I, characterized in that the current divider circuit is the combination of a reflection that in at least a number of state and a field effect transistor is used Stromteiiervorrichtungen (I. II) in parallel to the. As a result, the total current through the source-drain _{path of an additional field resistor connected to the source-drain path of the transistors 1T 01} , T ₄₁ I 40 to the current input of the current divider circuit is attached depending on the mentioned chip effect transistor 17 ,, T, '> is. its voltage and thus also the weighting factors of the TransGate electrode are connected to the current input of the general filter, as a result of which a distortion of the current divider device (I. II) affecting the signal occurs. that is. 45 The object of the invention is to provide a transversal filter 3. Transversal filter according to claim 1 or 2, which can be easily integrated and is characterized in that the adding device does not affect the weighting factors from the output (S. V) two differential amplifiers (A. B) relaxation of the storage elements each of the two inputs and one output (A ". Y) so that the signal distortion is kept to a minimum, with one input of each of the difference 50. This object is achieved by the invention by providing amplifier (A. B) with a Point constant that the current divider device is connected while avoiding potential, while the other inputs, which are difficult to implement for circuit integration , are connected to the current outputs (c. B) of the baren high-ohmic resistors two field current divider devices, with effect transistors containing their source -EI electrode between the output (A '. K) and that with a 55 with the current input of the Stromteiiervorrichtungen current output of the Stromtei device connected and their drain electrodes each connected to a current to the input of each of the differential amplifiers an output of the current dividing devices capacitance (C ^. C _n ) is attached, which have a capacitance and the two control electrodes have the field effect value which is greater than that of the capacitance transistors, the control value of the storage capacitances which determines the current division. 60 voltage received. Some embodiments of the invention are shown in the drawing and are described below described in more detail. It shows Fig. 1 shows a first embodiment of the Trans-65 versalfilters according to the invention, The invention relates to a transversal filter that has a F i g. 2 is a voltage diagram for explanation Row of storage elements, each with a capacity of the mode of operation of this transversal filter,
and a control electrode in which each of the F i g. 3 a second embodiment,