DE2302149A1 - METHOD AND DEVICE FOR DETECTING FAULTS - Google Patents

Description

ZPHrsT.6495 .

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AfcfeNo. ^ PHN- 6495 Registration worn »Jan. 16, 1973

Method and device for detecting defects.

The invention relates to a method and a device for detecting errors in a signal processing arrangement with a number of interacting sub-units containing digital signal processing circuits, which make it possible to detect errors occurring in one of these sub-units with a high degree of probability.

The localization of faults in an arrangement of the type mentioned above generally causes great difficulties due to the mutual dependence of the signals
in the various sub-units, which means that a very large number of signals must be checked. The error localization must then take place in accordance with a previously determined error localization program, which as a result of the aforementioned

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ORIGINAL tNSPECTED

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Fact will be involved and will have a long duration.

The most commonly used fault localization method mentioned above, e.g. to localize errors with the help of function curve sheets and various measuring instruments, has many disadvantages because this fault localization is then necessarily carried out by a trained Person and must be carried out in an environment that corresponds to that provided to the instruments for this fault localization Requirements.

In a method in which a so-called test lead is used, the number of test leads is limited Signals are fed to the selection of signals and to the reference necessary for error localization very strict requirements. A major disadvantage of this method is that the shape of the arrangement, in which this fault localization method is used, must necessarily be adapted to the test system used must, which means that this method is only applicable to new constructions and then at a much higher cost leads.

The use of a separate test system in which the fault localization for each sub-unit is separate is not practical in those cases where said signal processing device is sequential contains working logic circuits, which means that a large number of input signals must be generated in order for the Information about any errors taken from the output signals can be.

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The aim of the invention is to provide a method and a device for detecting faults, in which a detection device can be used in the signal processing device to be tested, which, in relation to the operation of this device, can be used in signal processing _; device can be operated by untrained personnel, where a fault localization can be carried out without the aforementioned disadvantages.

The method according to the invention is characterized in that the inputs or outputs of each sub-unit be combined into suitable test groups in such a way that each test group contains single inputs or single outputs; that it is ensured that said signal processing device works in a selected, predetermined mode with a predetermined amount of input data, said signal processing device performing an operation predetermined by said ones Input data and said operating mode is determined; that the inputs or outputs of each test group with Be controlled using a time division multiplexing unit, with the help of which the inputs or outputs mentioned one after the other a counter are brought into contact during a sampling cycle that is a predetermined very large number of times is repeated for each test group; that said counter is incremented with the aid of the scanning signals that are received when said signals exceed a predetermined amplitude level, said Counter of each input or output sampling signals with a

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Receives periodicity, which preferably does not equal one is an even multiple of the periodicity of one or a number of those operations that are carried out in the relevant subunit be repeated during the process mentioned and determined by the number of inputs or outputs of the test group concerned are determined, the .Endlage of said counter after passing through said previously determined Number of sampling cycles a statistical representation of the signals occurring in the relevant test group during testing forms; and that the position of said counter is compared with reference data after testing each test group, which are stored in a memory with an error indicated if the stated position of this counter does not match the corresponding reference data in the stated memory «

With a suitable combination of the test groups mentioned and with a suitable scanning sequence, a detected errors must always be related to a reduced number of error sources, which means that the method According to the invention, a quick localization of a fault in a given sub-unit with the help of a written Instruction permitted.

A major advantage of the detection method according to the invention is that the device to be tested can work in a normal mode with normal input data. Another benefit is that it is an essential Reduction of the number of sampled data output signals in a simple manner by using the multiplex unit mentioned is obtained.

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A common example of signal dependency will be formed by two complementary signals. Errors in such signals can be determined by the recording method used, in which the scanning signals are continuously added, do not detect. This problem could be solved by that complementary signals are not allowed in one and the same test group} but this would mean a larger number .Require test groups, which adds to the complexity of the procedure.

According to a further embodiment of the inventive The procedure is the mutual dependency of different signals in one and the same test group eliminates the fact that the sampling signal of each input or output of a test group is evaluated in such a way that each input or output will have a characteristic weight, said counter when scanning a given input or The output is advanced by a number of steps according to the characteristic weight of the input or output mentioned is, if the received sample signal exceeds said amplitude level, which means that the counter far switched *

Statistical studies have shown that the likelihood that any failure will not be detected is very small and of the order of a few Percent or less; Among other things, the capacity of the binary counter used is important.

Assume that there are X number of undetected errors if the counter Ji contains steps, which means that there are 2 * possible end positions of the named counter

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gives. The probability of an undetected fault P can then (probably) as:

P = A. X / 2 ^N.

- where A depends on the number of test cycles, among other things and the evaluation process depends, if the number of counter steps is increased by K is

P = A. X / 2 ^{N + K}

which means that the probability of an undetected Error is reduced by a factor (i / 2) if the Signals are mutually independent.

An embodiment of a device for performing the method according to the invention is characterized by: a time division multiplexing unit and connecting links interacting with this, each with one of the corresponding number Inputs or outputs of the sub-unit to be tested are connected, while this connection is established in such a way that Test groups are formed which contain only outputs or only inputs; an address memory for Controlling said time division multiplexing unit and storing the addresses for each of the outputs and inputs of the subunits; an address decoding unit for controlling the aforesaid Memory; a first pulse counter for synchronizing said arrangement and for supplying a control signal to said address decoding unit, which is preferably controlled by a clock pulse generator that is fed into the device under test is included; "a selector for selecting the sub-unit to be tested and a selector for selecting of the desired test group, with the mentioned addresses

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unit is controlled and effected by the named voters, that the address memory supplies an address for each control signal of said first counter; a second counter, which is connected to the output of said time division multiplexing unit and which in each case when a control signal occurs of the first counter, the sampling signal of the input or output of the relevant by the address supplied at the same time receives test group specified from said address memory, while said second counter receives from e.g. very large binary signals are switched on; a comparison unit connected to the output of said second counter is connected and the output of which is connected to an error indicator lamp; and a reference address unit used by the called address decoding unit "is controlled and a reference data memory is put into operation, the reference data supplies that of the test group of the said comparison unit correspond, this lamp being ignited by the comparison circuit when the mentioned reference data and the position of said second counter do not agree with each other after the end of the test.

Another embodiment of the device according to the invention contains a weighting unit which is between the The output of said time division multiplex unit and the input of said second counter and the sampling signal, which is taken from each input or output of a test group, via said time division multiplex unit assigns characteristic weight.

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Yet another embodiment of an apparatus according to the invention is characterized in that the second counter is a binary counter with a number with one another stages connected in series, said weighting unit containing a control unit, one input of which is connected to is connected to the output of the time division multiplex unit and has the same number of outputs as the number of. Inputs and outputs each test group contains, said outputs of the Control unit are each connected to an input of a separate stage of said binary counter.

The invention is explained in more detail below with reference to the drawing, which schematically shows an embodiment of a Detection arrangement for carrying out the inventive Procedure shows.

The sub-unit that is subjected to fault localization is denoted by 1. In this embodiment the detection arrangement becomes a so-called additional unit used, which makes it possible to connect the multiplex unit 2 to the inputs and outputs of the subunit 1, their The number in this embodiment is 80 (N = 80), such that that said sub-unit always forms part of the processing device while the method is being carried out and thereby can work in a normal mode.

In the embodiment of the test system described, the multiplex unit 2 is shown as a separate unit. In a further embodiment of the test system, however, a multiplex unit in each sub-unit can be next attached to the entrances and exits of the sub-unit concerned

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are, with control signals and output signals of the said Multiplex unit from a test system to the usual Contact members of said sub-unit are supplied or received, it being advantageous, inter alia, that the sub-unit can be tested without it being necessary that this sub-unit is moved from its usual working position.

Said detection arrangement further contains two selectors 3 and k _t. The selector 3 selects the sub-unit to be tested, while the selector 4 selects the relevant test group. In this example test groups with eight inputs or outputs are used. An address decoding unit 5 is controlled by the selectors 3 and k , which unit 5 in turn controls an address memory 6 in which the addresses for the inputs or outputs in each test group are stored The exemplary embodiment contains a control unit which, as a function of the weight assigned to the respective inputs or outputs in the relevant test group, supplies the said signals to the relevant positions of the binary counter 9.

In one embodiment, the weighting unit 8 contains a multiplex circuit, one of which is a signal input the multiplex unit 2 is connected and the same number of outputs as the number of outputs or inputs in each test group contains, whereby each of the named outputs with a separate stage (relevant position of the binary counter 9) of the binary counter 9 is connected to obtain different weights for each of the outputs while a

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Control input is connected to the pulse counter 13.

Said address decoding unit 5 also controls a reference address unit 7 which is the reference data memory the reference address supplies that of the test group to be tested corresponds, according to which said reference data memory 10 the comparison circuit 11 provides reference data in which Comparison circuit the reference data with the output signal of the counter 9 can be compared after the completion of the scanning of each test group. When the said signals are not interrelated match, the fault indicator lamp 12 is lit.

The detection arrangement as a whole is controlled by the pulse counter 13 controlled, that of said address decoding unit 5 and the mentioned weighting unit 8 control signals feeds, ensuring an accurate synchronization of the various signals occurring in said detection arrangement is ensured.

Said pulse counter 13 is in turn switched on with the aid of clock pulse signals that are generated by the clock pulse generator be supplied, which is included in this embodiment in the device to be tested.

The error detection takes place in the following way.

A sub-unit is replaced by the named additional unit in the named signal processing device, after which the corresponding sub-unit is connected to the named additional unit. The selector 3 is set to the position for said corresponding sub-unit. The desired test group is selected by means of said selector h , under the control of said pulse counter 13

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said address decoding unit 5 supplies an output signal, The output of said address decoding unit 5 then activates said address memory 6 in such a way that said memory of said multiplex unit 2 supplies the address of the first test point to the test group, said multiplex unit 2 providing the corresponding Scanning signal forwards to the said weighting unit 8, which under synchronous control by the counter 13 said Received scanning signal forwards to the position of said counter 9, which corresponds to the test point to be tested. The counter 9 is incremented when the scanning signal represents a binary "1". The output signal of the mentioned address decoding unit 5 is also supplied to the mentioned reference address unit 7, which then the mentioned Reference data memory 10 activated, which in turn corresponds to said comparison circuit of said test group Supplies reference data. After completion of the operation of said signal processing device and thus after the test points of the tested group have been scanned, the end position of said counter 9 with said of the reference data memory 10 supplied reference data in the mentioned comparison unit 11 compared. When the two The error indicator lamp 12 is lit.

In this embodiment, the scanning takes place said test points during the time during which the signal processing device used a predetermined tone

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The operation is carried out, which time in this case 1.25 seconds amounts to. The clock pulse frequency used is 0.7 MHz, which means that each test point takes about 10 times during of the detection process is scanned.

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Claims (3)

- 11? - ZPHN.6 ^ 95. 2302H9 PATENT CLAIMS t r \ y Method for detecting errors in a signal processing device with a number of interacting sub-units which contain digital signal processing circuits which, with a high degree of probability, allow the detection of errors which may occur in each of the sub-units mentioned, characterized in that the inputs or outputs ( 1,2,3 ··· Ν) of each subunit (i) can be combined into suitable test groups in such a way that each test group contains only inputs or only outputs; that it is ensured that said signal processing device operates in a selected predetermined mode with a predetermined amount of input data, wherein "i said signal processing device performs an operation which is determined by said predetermined input data and by said operating mode; that the on - or outputs of each test group are controlled by means of a time division multiplex unit (2) which brings the named inputs or outputs one after the other into contact with a counter (9) during a scanning cycle which is repeated a predetermined very large number of times for each test group; that said counter (9) is incremented with the aid of the sampling signals which are received when said signals exceed a predetermined amplitude level, said counter (9) receiving sampling signals from each input or output with a periodicity which is preferably not the same 309832/1073 - "\ K - ZPHN.6495. 2302H9 is an even multiple of the periodicity of one or a number of those operations that are cyclic in the relevant subunit (i) repeated during this process and are determined by the number of inputs or outputs of the relevant test group, with the end position of said counter (9) after running through said predetermined number of scanning cycles a statistical one Representation of the signals occurring in said test group during testing; that the position of the said meter (9) after testing each test group is compared with reference data stored in a reference data memory (1O) and that an error is displayed if the stated position of this counter does not match the corresponding reference data matches. 2. The method according to claim 1, characterized in that the sampling signal of each input or output one Test group is evaluated in such a way that each input or output will have a characteristic weight, and that said counter (9) scanning a given input or output by a number of steps corresponding to characteristic weight of said input or output is switched on, if the received sampling signal the exceeds said amplitude level, which means that said counter (9) advances. 3. Device for performing the method according to Claim 1 or 2, characterized by: a time division multiplex unit (2) and connecting links interacting with it, 309832/1073 - 15 - ZPHN. 6 ^ 95. 2302H9 which are each connected to one of the corresponding number of inputs or outputs (1, 2, 3, Contains inputs; an address memory (6) for controlling said time division multiplex unit (2) and for storing the addresses for each of the outputs and inputs of the sub-units; an address decoding unit (5) for controlling said memory (6); a first pulse counter (13) for synchronizing said arrangement and for supplying a control signal to said address decoding unit (5), which is preferably controlled by a clock pulse generator which is incorporated in the device to be tested; ■ a selector (3) for selecting the subunit to be tested and a selector {h) to select the desired test group, said address decoding unit (5) being controlled by said selectors (3 »* 0 t is and causes the address memory (6) to supply an address for each control signal of said first counter (13); a second counter (9), which is connected to the output of said time division multiplex unit (2) and in each case when a control signal of the first counter (13) occurs, a sampling signal from the input or output of the address in question from said address memory ( 6) receives the specified test group while the said second counter is being switched on by large binary signals, for example; a comparison unit (11) connected to the output, second counter (9). 3 f! 9 B 'II I 1 0 7 3 ~ 16 - ZPHN.6 ^ 95. and the output of which is connected to an error indicator lamp (12); and a reference address unit (7) which is controlled by said address decoding unit (5) and activates a reference data memory (1O) in such a way that it supplies reference data corresponding to the test group to said comparison unit (11), said lamp (12) from the Comparison unit (ii) is ignited when the mentioned reference data and the position of said second counter (9) do not agree with one another after the end of the test, k. Device according to Claim 3, characterized in that a weighting unit (8) is arranged between the output of said time division multiplex unit (2) and the input of said second counter (9) and the sampling signal taken from each input or output of the test group via the assigns said time division multiplex unit (2) a characteristic weight. 5 »Device according to claim k _t, characterized in that the second counter (9) contains a binary counter with a number of stages connected in series, the said weighting unit (8) containing a control unit, one of which is an input with the output of the time division multiplexing unit (2 ) and which contains the same number of outputs as ax number of inputs or outputs of each test group, said outputs of the control unit being connected to each input of a separate stage of said binary counter. T. G 9832/1073