DE2263019A1 - ADDRESSABLE MATRIX SYSTEM - Google Patents

Abstract

1418038 Data storage systems THOMSONCSF 21 Dec 1972 [23 Dec 1971] 59264/72 Heading G4A A data store includes N storage matrices the elements of which are addressed by a common addressing means, a test means arranged to compare data written into a read from the elements of successive ones of the matrices to determine whether each matrix is faulty, and a means for connecting the first n (n < N) fault free matrices to an addressing means arranged, in conjunction with the common addressing means to select any one from n matrices for read write operations. Eight matrices P 0 -P 7 each comprising 64 binary storage locations addressed by X and Y decoders are provided. A decoder DZ has four coded outputs Z 0 , Z 0 , Z 1 , Z 1 which present 5 volts for logic one and 0 volts for logic zero. In operation the first output of decoder DZ, viz. Z 0 = Z 1 = 0, Z 0 = Z 1 = 1, is selected. Z 0 and Z 1 are placed at 30 volts in order to destroy diodes D 00 and D 01 , leaving D 11 , D 00 acting as an AND gate to decode the output of decoder DZ in its first state and select matrix P 0 . Matrix P 0 is then tested by setting the output R 0 of decoder DA to render To conductive, the AND gate formed by diodes D 01 , D 00 , and fuse F 0 selecting matrix P 0 . The data written into P 0 is compared with the data read from P 0 and if the comparison is unsuccessful fuse F 0 is destroyed by a 30 volt signal IN, the decoder DZ outputs remain as they are and the procedure is repeated for matrix P 1 which is selected by rendering T 1 conductive. If the comparison is successful the fuse is not destroyed so that P 0 is accessed in response to the output Z 0 = Z 1 = 0, Z 0 = Z 1 = 1 of decoder DZ. The outputs of decoder DZ are then set to Z 0 = Z 1 = 0, Z 0 = Z 1 = 1 and the procedure is repeated for the next matrix. If when four fault free matrices have been assigned to the four states of decoder DZ some unused matrices remain they are tested by setting Z 0 = Z 1 = Z 0 = Z 1 = 1 and rendering their transistors T conductive and, if fault free, are retained as spares. The stores may be field effect or bipolar transistor devices.

Description

THOMSOK - OSP
173, vol. Haussmann
PARIS 8e ■ / France

Our sign:

Addressable matrix system

Ir. In certain cases, especially in program-controlled computing systems, arrangements with geographical addresses are used. In particular, use is made of memories which contain a certain number of matrices. Each of these matrices contains a certain number of memory elements which are arranged in rows and in columns. Each of these memory elements can be implemented in various forms, for example in the form of semiconductor circuits, magnetic elements, etc. It contains a certain amount of information, for example if the system operates in binary code, the memory element contains a number which is a sequence of digits is 0 or 1. To read the memory element of the matrix, which is identified by the number ^ a-Ja (where x. is the number of the row of the memory element in "the matrix and y ^ is the number of its column), one takes a so-called

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Lei / Gl

x-y addressing, i.e. that you have an adjustable x-y query arrangement, which has the equation x = x., y = y. and thereby the reading of the in the information contained in the memory element or the writing of information in this storage element.

In certain cases it may be desirable to store the memory elements of the matrix in several, for example η T sub-matrices or to arrange pages, each page in turn containing a matrix and having a number between 1 and η lies. The addressing then takes place with the help of an x-y-z query arrangement, where χ all values of 1 to p, y can assume all values from 1 to q and ζ all values from 1 to η; where ρ is the number of lines and q is the number of columns in each matrix, and η is the number of sides.

If you bet:
χ = χ ..

the memory element of the page z .. is controlled, the has the line number x .. and the column number y-.

If the storage elements are modules made up of large-scale integrated field effect transistors or bipolar transistors are formed, it can happen that one or more of them.entweder during manufacture is unusable or fails over time. -

In this case, the relevant page of memory or even all of the pages must be replaced.

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The aim of the invention is to provide an arrangement of addressable matrices of the type indicated above, in which this disadvantage is avoided.

The matrix arrangement according to the invention essentially contains a number of TT sub-matrices or pages, which are individually arranged in rows and columns, i.e. in coordinates χ and y are addressable.

The essential idea of the invention is that Facilities are provided which test the elements of each page one after the other and which are recognized as faulty Separate pages, and that facilities are provided which allow access to η (n <N) pages recognized as good and allow their elements between 1 and η depending on the number assigned to them.

The invention is described by way of example with reference to the drawing. Show in it:

1 shows the basic diagram of the arrangement according to the invention,

FIG. 2 shows the diagram of one of the sides of the arrangement of FIG. 1,

Fig. 3 shows the final connections of the arrangement of Fig. 1,

Fig. 4 shows an embodiment of the invention, Fig. 5 shows a detail of the arrangement of Fig. 4 and

FIG. 6 shows the final connections of the arrangement of FIG. 4.

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Fig. 1 shows a group of N pages P _Q through P ₇ ; in this case, N = 8, without this number being viewed as a restriction.

Each of these pages P. (Fig. 2) is a matrix with ρ rows and q columns, for example made of integrated semiconductor elements. One chooses, for example, ρ = q = 8; every side thus contains 64 integrated elements, each of which has a certain, always the same number of flip-flops contains. In the present case, for example, elements with a flip-flop circuit each are used as a reference point chosen. The states of each of these flip-flops become state 0 and state 1, respectively, by convention called, and each element can thus store the information of a digit in the binary code, without this example is to be regarded as a restriction. .

Each page P. of the type shown in FIG. 2 thus contains 64 flip-flops Bqq, Bq .. ... B .. ... B ₇₇ , the first number being the number of the line (O to 7) and the second number being the Indicates the number of the column (O to 7).

Two decoders DX and DY allow each to be selected Toggle switch according to -Iäer- ^ number of your -line and -the lobster their column. Ss is, for example, a decoder that receives a number at its inputs and that of the latter Activate number corresponding output. With an arrangement EL common to all sides, it is possible to use this decoder read or write in the information contained in each element as desired. All of these in themselves known arrangements require no further explanation.

Reference should now be made to FIG. 1 again. The arrangement contains 8 pages P _Q to P ", which are numbered from 0 to 7 in a three-digit binary code.

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When these pages are mass-produced, it is' inevitable that some of them will be faulty. With According to the invention, a device is provided which enables each element of each side in turn to describe and read, to separate the pages which contain faulty elements, and from the rest Pages to select a predetermined number n <N and to connect them to a z-addressing arrangement, with them the numbers O, 1 ... η - 1 are assigned. For simplification the explanation -soll chosen as an example η - = 4 will.

The arrangement of Pig. 1 contains the 8 pages P _Q to P ₇ . These 8 pages are connected in parallel to an X address decoder DX and to a Y address decoder DY and to a read-write arrangement EL. The read-write arrangement EL is connected to a signal generator G- via a coincidence detector "DC" * This generator is operated by the coincidence detector DC and then generates a pulse IN of large amplitude.

The arrangement also contains a Z decoder DZ with four outputs 0, 1, 2, 3 _? the parallel with four inputs e ^ to e. of eight arrangements "Cq to C _{7 are} connected. Each of these arrangements has a control input E. (j = 0,1 ... 7), which is connected to one of the N (N - 8) outputs of an auxiliary decoder DA.

The output S ^ (i = 0 _e . “7) of each of the arrangements Cq to Cr is connected to the side with the same number via a fuse Eq to P ₇ , to the input of which the pulse IN is applied. Any arrangement C- (3 = Ö «* <. 7). is designed so that when one of the inputs e _Q to e., a

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Receives signal from the corresponding output of the decoder DZ and the input E. receives a signal from the corresponding output of the auxiliary decoder DA, a connection between this input e. (i = 0, 1, 2, 3) and the output S. is formed and this connection remains after the disappearance of all input signals.

Given these conditions, the described arrangement operates in the following way: In a given At its first output, the decoder DZ excites the inputs eQ of all arrangements Cq to C ~.

At the same moment, the auxiliary decoder DA excites the input Eq of the arrangement Cq at its output number O. The output Sq of this arrangement is excited and a sensitizing voltage is applied to the side Pq.

All elements of this page are then addressed by the decoders DX and DI according to Y and X, and the read / write arrangement EL then writes and reads this page element by element. If one of the elements is recognized as unusable because the result when reading does not correspond to the writing, the coincidence arrangement DC activates the generator G, which "then generates a pulse IN. This causes the fuse Pq to break through (case of FIG. 3). This side is not assigned the number O. The same test is carried out for the P- side, from the input e _{Q of} the Um-B switch C ^ and its input E *. This side 'S λ is well recognized and remains through its fuse F .. and the arrangement Cj is connected to the input Gq, ~ ie to the output Ö of the decoder DZ, so that the number O is finally assigned to it.

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2263018

At a later point in time, the inputs e * of the arrangements C_ to G _{7 are} excited by the second output of the decoder DZ, and the auxiliary decoder DA excites the input E _{2 of} the arrangement C _2. Then the same test procedure runs again, and the input e * the arrangement C ₂ is connected to its output S ₂ , as in Pig. 1 is shown. If the page P _{2 is} faulty, the pulse ΙΪΓ destroys the fuse P ₂₀ Since the output 1 of the decoder DZ remains energized ₉ then the test process is repeated for the page P ^ o In the present Pail it should be assumed that the page P ₂ is recognized as good. The fuse P ₂ therefore remains in place, and the side P ₂ remains connected to the output 1 of the decoder DZ via the input e ^ of the arrangement C ₂ , whereby the number 1 is assigned to it.

This process is continued ₉ until ¥ ¥ ier pages have been recognized as good »

The arrangement corresponds to the representation of Pig. The output O of the decoder DZ is connected to the side Pj, the output 1 to the side Pg _5, the output 2 to the side P. and the output 3 to the side Pe. · The ■ sides P _Q and P ~ - have been determined to be bad.

The orders Cg and C- are not activated and therefore no connection to pages Pg and P ~, the fuses of which Pg or P ~ are still present; these pages are in reserve held.

The following piguren relate to an exemplary embodiment in which semiconductor circuits as well as in binary Number representation working decoders are used.

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The one in Pig. The arrangement shown in FIG. 4 contains eight pages Pq to P ₇ , from which, as in the previous example, four pages that have been determined to be good are to be selected, to which the numbers O to 3 are assigned, and those for Z addressing with Z = O, 1 , 2 or 3 should be made accessible.

As in the preceding Pail, the arrangement contains a decoder DX and a decoder DY, of which only the outputs X and Y are shown, which are connected in parallel to all elements of the sides P _Q to P ₇ .

The decoder DZ, which should display the numbers O to 3 in binary code at its outputs, contains four outputs Zq, YZ, Z ₁ , "ST. Since it is assumed that the system works in positive logic, the value 1 should be a voltage of 5V and the value 0 correspond to a voltage of 0V.

It is also possible to validate the connections that are normally in operation on the Value 0, bring it to a much higher potential of the order of 30 volts.

Under these conditions, the four outputs of the decoder DZ form a Z addressing network. The first two outputs Zq and YZ correspond to the direct value or the complementary value of the first digit of a two-digit binary number with which the numbers 0 to 3 can be represented.

So if output Z _{0 has} the value in normal operation, output YZ has the value 1 and vice versa.

The outputs Z * and ZT correspond in the same way the direct value or the complementary value of the second

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^z o
O ^No. 1
O and ^z o
1 ^No. 1
1 O 1 1 O 1 O O 1 1 1 O O

Digit of the two-digit binary number. It is well known that the numbers 0 to 3 correspond to the following binary digits:

For O the binary digits
1
2
3

The eight address conductors corresponding to the numbers 0 to 7 are each connected to one of the eight outputs of the auxiliary decoder DA in the same way. Therefore, only the connection for the Pq side will be described in detail. It contains a transistor T ₀ , the base of which is connected to the output R _{Q of} the auxiliary decoder DA, the emitter of which is connected to a point A, and its collector on the one hand to the sensitization input Eq of the side P _Q and on the other hand via a fuse I ¹ Q with the output IiT of the generator G and a DC voltage source of 5 V and a resistor E. is connected to ground. The connection going from the collector of the transistor Tq to the input Eq is connected to the Z-Adressiej? Ungsnetz via diodes Dq ₀ , Dq ^ j »Dq ₁ and D _Q y, which are switched so that their forward direction from the input Eq to the associated connection Zq, "Zq ₉ Zj, Z ^ goes. These diodes are designed in such a way that they are destroyed if a sufficient voltage is applied to them in the reverse direction, in the present Pail a voltage of the order of magnitude of 30 volts.

The final allocation takes place under these conditions the numbers O, 1, 2, 3 to those found to be good Pages in the following way:

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For the number 0, the two outputs YI and are brought to the corresponding logic potential in the order of magnitude of 5 V and the connections Z _Q and Z * are brought to a voltage in the order of magnitude of 30 V. The side P _Q should be checked first; namely, it is assumed that the pages are checked in the order from 0 to 7, without this being mandatory. The output R _{Q of} the decoder and only this is brought to a potential through which the transistor T _{Q is} opened. A voltage of 0 T is applied to point A.

The connections Z _Q and Z ₁ are brought to the potential of 30 V, whereby the diodes Dqq and Dq _{1 are} destroyed.

No further diode Dq or D. ^ will be destroyed at this point in time. Since the transistors T ₁ to T ^ are not open, the potentials between the inhibitors of the fuses remain high, and the corresponding resistors R bridge these transistors, while "the transistor Tq is the opposite of the Pail.

As a result, the potentials of the inputs E. "until he is close to the potential at input IF.

Thus, only the diodes Dq * and D ₀ ^ - and the _{other diodes connected to the inputs E 1} to Er, remain.

2. The potential at the output Rq of the auxiliary decoder DA and the potential at the connections Zq and Z ₁ are brought back to the value 0V. The input E _Q and only this is brought to a potential of 5 V by an and circuit, which is shown in Pig 5,

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This AND-Sehaltung has three inputs, namely the input Z ^, which is connected to the diode D _Q ^, the input Z ^ - which is connected to the diode Dq ^ -, while the third input is the output of the fuse Pq is. The other inputs E-, "to E ₇ " remain at the potential O, since the four corresponding diodes are not destroyed and therefore two of these diodes are always at the 0 V potential. If one of the inputs of the AND circuit falls to the potential 0, the input E _Q connected to the output of the AND circuit also assumes the potential O (see Pig. 5).

The page is then checked. If it has been found to be good, the condition described remains. In the opposite pail, the pulse G emits a pulse IN that is sufficient to cause the fuse P ₀ to break down. The input Eq then falls to the potential O. It can never be accessed again because the associated fuse has been destroyed.

The same process is repeated for the page P ^ · Es it is believed to be determined to be good. Then it is assigned the number 0.

In the portrayal of Pig. 6, it is assumed that the sides P 1, P 1, P, and Pc have been found to be good are.

The pages that have been checked and found to be good are shown without their associated transistors, as they no longer serve any purpose. The sides P / - and Pr ₇ are still connected to the transistors Tg and T ₇ and connected to the inputs Zq, Z ^, Z ₁ , Z ^. To make them sensitive too

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make, it is sufficient, since their diodes have not yet been destroyed, _{to apply an access voltage to the outputs Rg or R 7} and to form signals Z _Q = Z * = 1, Z ^ = Z * = 1.

These pages can be checked and kept in reserve.

The steps described are shown in ■ Pig. 4, 5 and 6 - to be found.

The connecting bar of the changeover switches of FIGS. 1 and 3 is replaced in this case by the destruction of the superfluous diodes and the lack of a connecting bar by the presence of all diodes.

Of course, the invention is suitable for all types of components; it increases the yield of memory with Semiconductor elements or the like. By at least an order of magnitude.

Furthermore, since the good sides are kept in reserve, the service life is considerably increased -a-system, namely -with the help of equipment whose Costs are negligible compared to those of the entire system.

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Claims (5)

Claims Addressable matrix system of memory elements, which are divided into N pages, with a write and a Reading arrangement and with first and second addressing devices that enable the writing and reading of the Enable information of each memory element, it being with the first and with the second addressing device it is possible to address the storage elements of each page one after the other line by line and column by column, characterized by a third addressing device which selectively enables access to each of the IT pages, a fourth addressing device which selectively allows access to each of the η pages, where η is a is a predetermined number for which n <IT, connecting devices for connecting each of the IT pages to the fourth addressing device and by destroying devices created by a coincidence arrangement in this way can be actuated that they destroy the connecting devices when at least one storage element of the relevant Page is recognized as faulty. 2. Matrix system according to claim 1, characterized in that the fourth addressing device is a decoder with η outputs, each output of which can selectively assume a potential different from O, the rank of this output expressing the number j of a page with <n-1 . 3. Matrix system according to claim 1, characterized in that the fourth addressing device is a .Decoder that works according to the binary code that η is an integer power η = 2 ^ of 2, that every output of the 309827/1061 -H- fourth addressing device two mutually complementary Has connections and that the states of the connection pairs in the binary code are between O and η Express number and its complement. 4. Matrix system according to claim 3, characterized in that the connection devices each contain diodes, which are connected between the input of the corresponding side and the output connections of the decoder in such a way that that their forward direction is from the input to the output terminals and that the diodes are of such a nature that they will be destroyed if their electrodes are in the In the reverse direction, a predetermined potential is applied which is considerably greater than that expressing the binary value 1 The potential is that this potential to destroy the diodes in each case at the output terminals assigned to state 0 is delivered, and that a transistor whose base with the corresponding output of the third Aitressie is connected when a Voltage at the output is brought into saturation and the potential at the input of the corresponding side holds at zero. 5. matrix system according to claim 4, characterized in that each destructive device is formed by an AND circuit whose output is connected to the input of the corresponding side and has the inputs via the non-destroyed diodes are connected to the output terminals, the potential of which is at the value 1, while Another input is connected to a voltage source via a fuse, which provides a voltage supplies whose value is in the vicinity of the voltage assigned to the binary value 1, that the fuse is connected to a Pulse generator is connected and is destroyed by the occurrence of an output pulse of the generator, and that the generator is actuated by the coincidence arrangement. 309827/1061