DE2255031C3 - Circuit arrangement for a module for building fail-safe protective circuits - Google Patents

Description

The invention relates to an electronic circuit arrangement according to the preamble of the patent claim 1.

Such a circuit arrangement is known from DE-OS 15 37 532. In the »m out» n circuit described there, pulse patterns are supplied by a pulse generator, the evaluation of which at the output of the selection circuit provides information about the status of the signal channels with a distinction as to whether »1 from 3 "or" 2 from 3 "state is made possible. Because of hers

With a complicated structure, the known circuit arrangement is expensive and prone to failure.

Further guidelines VDE 2180, Part 2, "Safeguarding of industrial process engineering possibilities of signal processing," in October 1967, also circuit arrangements are known from the VDI /, the order of "a / - perform selection!.

Based on such an arrangement, the invention is based on the object of providing the arrangement in this way design so that the output signals of limit value

Bern can be monitored with a minimum of components and a maximum of security.

This task is carried out by the in the characterizing

Part of claim 1 mentioned features solved Compared to the known "2 out of 3" -AuswahlschaI-

J5 tion can detect individual errors with this Circuit arrangement according to the invention can be implemented without additional circuit complexity. Furthermore is the circuit against short circuits and faulty interruptions in components secured by an immediate shutdown

This arrangement is designed in such a way that if the signal fails, one or two of the limit switches will switch on Error is displayed. It is assumed that the limit value transmitter (s) is / are exceeded when the Limit values no longer give a size.

The block according to the invention is then particularly simple if for the logical basic elements (“AND” gates, “OR” gates) Circuit arrangements are used that do not

w can be controlled with static signals, but with pulse trains and in which the failure of the Pulse sequence is displayed as an »error« at the output.

A particularly simple basic logic element for an "AND" gate circuit has a transistor, whose base is controlled by one winding of a magnetic switch core, the two other windings has, to which the two quantities to be linked are fed as phase-shifted pulse trains. Then namely the magnetic switch core of the

w) both impulse trains to be combined in one State of magnetization continuously switched back and forth, so that in the winding controlling the transistor base The magnetic switch core also induces a pulse train, which is amplified for further processing on the

h5 collector of the transistor can be removed.

This "AND" gate circuit just described can be used in a simple manner to monitor an "OR" Gate switching can be operated if the

fenden phase-shifted pulse trains are combined in an addition network and each input variable of this addition network is passed over windings of magnetic switching cores, so that all Input variables form an "AND" link.

Advantageously, to suppress the Shutdown by the »2 out of 3« selection switch »ORw gate circuit added more impulse trains

The block according to the invention thus allows a great deal to build a variety of safety circuits with the most varied levels of security without the Module itself would have to be varied. This results in great manufacturing advantages. if you then arrange the error display and / or the shutdown display on the block itself, like this the maintenance staff can immediately see at which point or in which module an error has occurred is and replace the module without major delays, so that the maintenance of a safety circuit that consists of modules according to the invention is constructed, is greatly simplified.

In the following the invention is described in detail with reference to the drawings. It shows

F i g. 1 is a block diagram for a module according to the invention,

F i g. 2 shows a circuit arrangement for realizing the block diagram according to FIG. 1,

F i g. 3 shows a diagram of the circuit arrangement according to FIG. 2 occurring impulses,

4, 5 and 6 examples of a combination of the Building blocks for a safety circuit.

. With reference to FIG 1, the logic block diagram is illustrated of a block, of a combined »1 of 3 '- and' 2 of 3 'linkage performs each input El, £ 2, £ 3, EH, Ep, Vas, E is a corresponding input signal SEI, SE2, S £ 3, SEH, SEp, SVas, SE supplied. The pulses SA, SAH and SApan are then available at the outputs A, AH, Ap.

There are three “AND” gate circuits Ki, K 2 and K 3 , to which the three input signals SEI, SE2 and S £ 3 are each fed in pairs via the inputs E1, E2 and E3. These three input signals are available as phase-shifted pulse trains. The outputs of the three "AND" gate circuits Ki, K 2 and K 3 are fed to an "ORw gate circuit Oi as well as two" UNDw gate circuits K 4, KS which enable these three inputs of the "OR" gate circuit to be monitored at the same time . The two other inputs EH and Vas are not monitored at this point. The outputs of the two "AND" gate circuits Ki and K 2 are fed to the two inputs of the "AND" gate circuit K 4, the output of which is connected to one input of an "AND" gate. Gate circuit KS is connected The other input of the "AND" gate circuit KS is controlled by the output of the "UNDw gate circuit K 3" .

If only one of the signals SEI, S £ 2 or SE3 fails, only one of the three “AND” gate circuits Ki, K 2 or K3 can emit a signal. This means that the signal at the "AND" gate circuit K 5 must disappear, while a signal is still present at the output of the ¹ "OR gate circuit O 1. In the “AND” gate positions Ki to K 5, a “1 out of 3” selection is therefore carried out. The four basic logic elements, namely the three "AND" gate circuits K 1 to K3 and the "OR" gate circuit O 1, on the other hand, carry out the "2 out of 3" selection, since the signal at the output of the "OR"

Gate circuit Oi only disappears when at least two of the three signals SEi to S £ 3 have disappeared.

The circuit arrangement according to FIG. 1 also has two “UNDtt” gate circuits K 6 and K 7, two modules Fi and F2 and another “OR” gate circuit O 2 . These components of the circuit serve failsafe prove whether the signal characteristic at the output of the "AND" gate circuit K 5 and at the output of the "OR" gate circuit Oi is present or not do this, the output of the "AND" gate circuit KS is the "OR" gate switching O 2 is fed through to one input of the "UNDtt gate circuit K 6, the other input of which is subjected to test pulses SEp. If the pulse train at the output of the "AND" gate circuit K 6 is lost, a warning signal is triggered in module Fi

In the same way, the output of the “OR” gate circuit Oi is checked with the aid of the “AND” gate circuit K 7 to which pulse trains SE are applied.

The "OR" gate circuit O 2 is not necessary per se. It is used to feed the signal SVas to one input of the “UNDw” gate circuit KS , which is also fed to the “OR” gate circuit Oi. The meaning of the signal SVas and also of the signal S £ f / will be explained later

The circuit arrangement is designed so that both in the event of a short circuit and in the event of a fault Occurring interruptions in components as well as in the occurrence of short circuits to earth potential or the supply voltage is switched off in each case

FIG. 2 shows how the logic block diagram according to FIG. 1 can be constructed with known circuit arrangements. The three "UN D" gate circuits Ki to K 3 from FIG. 1 consist of the three memory switching cores Ki, K 2 and K 3 each with three windings Wl, W 2 and W3, the three transistors Ti, T2 and T3 and the resistors R 1, R 2 and R 3, which are the load resistances for the respective Windings Wl, W2 are. The three input signals S £ l, SE2 and 5 £ 3 are the three "AND" -Torschaltungen in the form of phase-shifted pulse trains pairs supplied to the outputs of the three "AND" -Torschaltungen Ki, K 2 and K 3, which at the collectors of the three transistors Tl, 7 "2 and T3 occur are linked in the» UNDw gate circuits K 4 and KS , which each consist of a magnetic switch core with windings Wl, W2, W3 and the transistors Γ4 and TS 2, the output variables of the UNDw gate circuits K i and K 2, which are present at the collectors of the transistors Ti and 7 * 2, are fed to the windings Wl and W2 of the UNDw gate circuit K 4, which in turn are fed to it on The collector of the transistor TA sends the output signal to the winding W2 of the "AND" gate circuit K 5 .

As already mentioned in connection with FIG. 1 explains, the "AND" gate circuit K 5 then no longer emits a signal, who? also only one of the input signals SEI, SE2 or SE3 fails. In order to check this fail-safe, the output of the transistor Γ5 is fed to the output AH via the winding Wl on the magnetic switch core of the »UNDw gate circuit K6 , whose winding W2 receives the test pulses SEp . This means that the pulse train at output Ap will disappear if an error occurs.

These test pulses SEp can be taken from a clock generator or come from another module. With the “AND” gate circuit K 6 , the output AH and thus the input EH of the “OR” gate circuit C 1 of another device (Fig. 5) is also monitored in block F1 if the output variable fails of the transistor T% triggered a warning signal

The "OR" gate circuit 0 1 from FIG. 1 has been designed as a passive network in the circuit arrangement according to FIG. As you can see, a pulse train is always applied to the winding Wl on the magnetic switch core of an "AND" gate circuit K 7 when either the transistor TX of the "AND" gate circuit K ί (via Wl from K 4) or the transistor ii T2 the "AND" gate circuit KI (via W2 from KA) or the transistor T3 of the "UNDtt gate circuit K 3 (via Wl from AC 5) or the input EH or Vas leads a pulse train since the winding W2 of the switching core K 7 a pulse train SE is fed, which is phase-shifted against all 2 "possible phase positions of the pulse train at the input of Wl the" AND "tone", attitude K 7, the presence of a signal at the "AND" gate circuit K7 in conjunction with the block Fl The output of the "OR" gate circuit 0 1 is monitored in the same way as has already been described in connection with the "AND" gate circuit K 6 and the block F1.

Operating states can now occur in a system in which not a single one of the parameters to be monitored has reached its setpoint, so that a fault is displayed and a shutdown is triggered. Such an operating state occurs, for example, when a system is started up. In order to avoid a shutdown in this case, the two “OR” - “gate circuits 0 1 and O 2 from FIG. 1 the signal SVas is supplied, which is switched off when the operating parameters have reached their setpoints. In the circuit arrangement according to FIG. 2, the signal SVas reaches the winding WX of the "<> magnetic switch core of the" AND "gate circuit K 7 via a resistor R 9 and via the transistor 7" 8 and a resistor R 10 to the base of the transistor Γ5 of the "AND" - K gate 5, of which the winding WX is driven to the "AND" -TorschaI-tung K 6th Since the two "AND" gate circuits K 6 and K 7 are additionally supplied with the pulse trains SEp and SE , there is a signal train at the outputs of these two gate circuits so that neither an error display nor a shutdown occurs. The signal input EH is required when larger protective circuits can be assembled from such modules as shown in FIG.

The F i g. 3 is a pulse diagram and shows how the various pulses occur inside the device and at the outputs AH, Ap and A when the input pulse trains SEX, SE2, SE3, SEp and S £ have the specified phase position and the direction of winding of the control windings of the magnetic switch cores is selected as it by points in F i g. 2 is indicated

In Fig. 4 is an example of a larger «· Safety circuit, a so-called. Shutdown chain, shown with the modules according to the invention can be put together. With this safety circuit, two measurands over three each Limit switches are monitored, and also the *> 5 Safety strands are designed threefold

Two modules AWXX and AW2X form the first safety line, consisting of a test and shutdown line. The second security line is formed by the modules AW 12 and AW22 and the third security line is formed by the modules AW 13 and A W23 '■ A pulse generator TK X supplies the limit monitors GIl, G21 as well as the inputs E and Ep of the first module AWIl of the first security line . The limit switches G12 and G 22 as well as the inputs E and Ep of the first module of the second security strand AW 12 are supplied by the clock generator TK 2 The supply of the limit switches G13 and G 23 as well as the inputs E and Ep of the module A WX3 is provided by the clock generator 7X3.

If, for example, the value entered at the limit indicator GJ1 is exceeded, the pulse trains at the inputs of the modules AW 11, AW 12 and AW 13 fail, so that the test branch indicates an “error”. The modules A W2X, A W22 are received and A W23 no more test pulses, since the test pulses SEp for these components are taken from the outputs Ap of the upstream components. The error display occurs on the one hand via the blocks Fl of the individual devices and on the other hand in a fail-safe manner in the output devices Λ 11, Λ 12 and Λ 13. It is \ therefore triggered no shutdown Only when exceeds the set value of the same measured variable, a second limit sensor is switched off as g in combination with F i. 2 has already been described, namely via the blocks RA XX, RA Yl and RA 13. If desired, the outputs of the blocks AMIl, RA 12 and RA X3 can still be linked according to a "2 out of 3" method. ' ₍

F i g. 5 shows as an example how a “3 out of 6” link can be carried out with four modules according to the invention. A measured variable is monitored by six limit switches G 31 to G 36. If, for example, the two limit switches G 31 and G 32 respond, there are no longer any pulse trains at the inputs EX and £ 2 of the module AW3X, and a shutdown should therefore actually take place. This is not the case, because module A W32 receives pulse trains at all three inputs, so that another pulse train is pending at output AH of module A W32 which is fed to input EH of module AW3X.

As you can remember, the input EH leads to the "OR" gate circuit 0 1, which is shown in FIGS. 1 and 2 has been shown and explained and in particular from FIG. 2 it can be seen that the magnetic switch core of the "AND" gate circuit K 7 is switched back and forth and this gate circuit thus emits an output signal when a signal is fed to the winding Wl of K 7 from the "OR" gate circuit OX - in In this case, the signal SEH from the subsequent stage - since the signal SE is also present at the winding W2 of K 7

Only when another limit switch signal fails, for example the signal from limit switch G 33, is it switched off, this time via module A W34, since the state of module A W3X no longer changes due to the loss of the signal from limit switch G 33

FIG. 6 now shows an example of a safety circuit constructed from modules according to the invention, with which it is achieved that the shutdown when the limit values of an f

Measured variable only takes place when another measured variable has exceeded a certain limit value. This example is very similar to the example from FIG. The main difference is that the pulse trains at the outputs A of the modules 5 A W4t to 43, with which the measured variable 4 are monitored with the aid of the limit value transducers G 41 to G 43, now not the input E of the modules AW5 \ to 53, are fed separately to the inputs Vas of these modules. ι ο

In addition 6 sheets of drawings

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Claims (6)

Patent claims: 1. Electronic circuit arrangement for a module for building safe safety circuits from inherently error-free logical basic elements, in which "m" separated signal channels are provided and an "n out" kc selection can be carried out, with three first UN D gate circuits being provided , to which the output variables of three limit switches can be fed in pairs, in which an OR circuit is provided for "2 out of 3" selection, to which the outputs of the first three AND gate circuits are fed, and a circuit part through which the Failure at least ·; , one of the outputs of the first three AND gates detected and the absence of output signals can be displayed characterized in that the circuit part to the "1 3": Store from a fourth AND gate (KA), of the outputs from two of the three first UN D gate circuits (K 1 to K 3) are supplied, and from a fifth AND gate circuit (K 5), the output variables of the third of the first three AND gate circuits (Ki to K3) and fourth AND gate circuit (K3 and K 4) are supplied, and that the "1 out of 3" · and the "2 out of 3" selection circuits are each designed with a separate display. 2. Circuit arrangement according to claim 1, characterized in that the AND gates (KI, K 2. K 3, K 4, K 5) are supplied with the input variables in the »/.- state as pulse trains, and that at their outputs in »/,« - status pulse trains are present. 3. Circuit arrangement according to claim 1 or 2, characterized in that the output of the "1 out of 3" selection circuit are each fed to an AND gate circuit (K 6, K 7) that the second input of the AND gate circuit (K 6 or . K 7) a pulse train (SEp or SE) is present, that an error display or shutdown occurs due to the loss of the output variable at these two AND gates (K 6 and K 7) , and that when several modules are connected in series, the pulse trains for the Error display and shutdown serving AND gate circuits (K 6, K 7) are taken from the previous module. 4. Circuit arrangement according to claim 2 or 3, characterized in that the AND gate circuits (K \, Κ2, Κ3, Κ4, Κ5, Κβ, Κ 7) a magnetic switch core with three windings (Wl, W2, W3) and a transistor ( 71, 72, 73, 74, 75, 76, 77), the base of which is driven to one of these windings, and that the quantities present as phase-shifted pulse trains in the »/,» - state are fed to the other two windings, whereby through a short circuit between the inputs of the AND gate circuits (Ki, Kl, K3, K 4, K 5, K 6, K 7) an interruption of the pulse trains can be brought about. 5. Circuit arrangement according to one of Claims 1 to 4, characterized in that further pulse trains (SVas. SEH) are further pulse trains (SVas. SEH) until the operating parameter setpoints are reached to suppress the shutdown by the "2 out of 3" selection circuit of the OR gate circuit (O 1) are supplied. 6. Circuit arrangement according to claim 5, characterized in that in the case of a circuit (F i g. 6) constructed from several "2 out of 3" selection circuits, each of the "2 out of 3" selection circuits (AW4i to AW S3) with an input ( Vas) is provided.