DE2245737A1 - PROCEDURE FOR OPERATING A PROGRAM-CONTROLLED DATA PROCESSING SYSTEM - Google Patents

Description

SIEMENS AKTIENGESELLSCHAFT München, 1 & SERI. 97 2 Berlin and Munich Wittelsbachenalatz -2

72/2119

Method for operating a program-controlled Data processing system

The invention relates to a method for operating a program-controlled data processing system with several

processing units that can be switched in parallel and two in parallel synchronously working storage units in which the Information and control signals output by system units operating in parallel are compared and in the In the event of an error, the transfer of the information into the respective corresponding system units is prevented.

A program-controlled data processing system, in particular used as a data exchange system, is known (DBP 1300 138, DBP 1905 659, DOS 1942 189), which is built up from several system units. To this System units include the processing units and at least a storage unit. The processing units have no connection with one another and operate independently from each other with the storage units. A storage unit is from the main memory, for example a Core memory, which contains the data and programs necessary to solve the switching tasks, the memory operation control for the execution of the various memory operations, the memory request control for the allocation of the memory cycles to the requesting processing units and the program request control for requesting programs built by the processing units. The processing units are connected to the storage units via System-iTor connections tied together. Your cycle requirements for the storage

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units are sorted according to the priority of their basket connection treated at the memory. A description of the cycle allocation and the control in memory can be found in DOS 1 944 483, for example.

In the DOS 1942 189th there is also something that has been further developed System described '/.orden in which the storage unit from multiple memory banks is constructed, each storage medium and storage operation control to a logical Combine functional unit. These memory banks are via information channels and control channels with the memory input / output control tied together.

To increase operational safety and availability of such a system, it is known to preprocess all or only certain system units twice

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hen (modular structure). Because of the interchangeability of identical system units, this structure means that if one system unit works incorrectly, its tasks can be carried out by the other. The incorrect operation of at least one of the system units running in parallel or a disturbance in the synchronism is determined by comparing the information given by the system units running in parallel. 7, If the synchronism of system units running in parallel is disturbed or if the information provided is not identical, the comparison result leads to an error message. Even if a parallel run of processing units is not absolutely necessary, the storage units must always be doubled for reasons of availability and rapid error detection. In order to enable the storage units to run synchronously in parallel, they have always had to be identical with regard to their contents. However, not all of the security requirements are stored in the storage units.

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Fixed data and programs alike. Only the more important ones Data and programs must be running in parallel in both Storage units be stored identically. With lower security requirements (e.g. with sufficient Error detection through parity control in the storage units) as well as for test purposes, it is therefore possible to define areas to occupy different - not identical - data and programs in both storage units. This would be it is also desirable that storage space can be saved in this way.

The invention is based on the object of specifying a method with which several parallel running memory inputs units can be assigned identical or non-identical information without affecting the synchronism of the Storage units is lost.

According to the invention, this object is achieved in that a processing unit which requires a memory cycle a request for the allocation of a memory cycle is directed simultaneously to all memory units that the requesting processing unit sends out additional information before the storage cycle is allocated the one storage unit in which the desired storage operation (e.g. read, write) may not be carried out is to be notified that all storage units are simultaneously exchanging the same control signals with the requesting processing unit and that one memory unit notified by said additional information does not carry out the desired memory operation ("Empty Cycle").

The condition for synchronous traffic between the processing units and the storage units is met by daii cycle requirements for identical and non-identical

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see memory areas (two memory areas are identical, if they have the same content) always to both storage units be judged. The memory unit in which the desired operation should not be executed. After the cycle allocation, this memory unit simulates the cycle sequence: Outwardly it behaves as if it were going through the cycle, but it does not perform the operation. In the memory unit runs an '"empty cycle". In this way, the processing units always receive from both Storage units simultaneously control signals, i.e. for example cycle acknowledgments and memory output messages.

In an advantageous embodiment of the invention, a first memory unit divides the memory during a memory cycle does not execute the operation requested by a first processing unit, this memory cycle one second processing unit, the execution of an operation in the first and the non-execution of this operation requested in the second storage unit. In this way it is avoided that a first processing unit Caused idle cycle for other processing units that also have non-identical cycle requirements put, is lost. Thus, this improved method increases the number of memory cycles available in the system by assigning empty cycles.

Further details and advantages of the invention are explained with reference to the drawings. Show it Figure 1 is a block diagram of a data processing system in which the invention is used,

FIG. 2 shows a schematic representation of the time sequence when executing idle cycles for maintenance purposes the synchronization of both storage units and

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Figure 5 is a schematic representation of the time ». Expiry when executing and assigning "idle cycles to maintain the synchronism of both storage units,

In FIG. 1, three processing units YE1, VE2 and VEn are shown, each of which is connected to the two storage units SE1 and SE2 via system / form connections. According to DOS 1942189, the memory units SE1 and SE2 are essentially composed of a memory input / output controller SEAS1 or SSA82 and the actual memory S1 or S2. These memories S1 and S2 can in turn consist of several memory banks. The information and control signals of the memory units SEI and SE2 are compared in the comparators V1, V2 and V3. Comparison errors are · reported by the comparators to the respective processing unit. If comparison methods are to be used for rapid error detection, the memory units SE1 and SE2 must be operated in parallel, synchronously, since in a multi-processing unit system with asynchronous operation there is the possibility of interchanging the cycle sequence on both memory units. Y / as this means and what consequences the reversal of the cycle sequence would have should be explained using the following example. Three processing units VE1, VE2 and VEn may request a storage cycle on the storage units. The processing unit VE1 has a cycle request for a memory cell Ή in the storage unit SE1, the processing unit VE2 requests a write cycle for the memory cell M in both memory units and the processing unit VEn requests a read cycle for the memory cell M in both memory units. The priorities according to which the processing units are assessed during the cycle allocation may fall from VE1 via VE2 to VEn. Request the processing units VEi and VSn

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at the same time cycles on the storage units, so will initially the processing unit VS1 takes into account and receives a storage cycle allocated in the storage unit SE1; the processing unit VEn initially receives the read cycle in the memory unit SE2. Now meet the cycle requirement from the processing unit VE2 in both storage units. It gets because of its higher priority the write cycle for the memory cell M on both memory units, while the processing unit VEn still waiting for the cycle in the storage unit SET v /. Finally, the read cycle for the processing unit V2n executed in the memory unit SE1. The processing unit VEn receives the information read and compares it it with the previously received information from the storage unit SE2. The comparator now reports non-identity of the memory information from the cell M, although the memory cell M is identical in both storage units. Around The processing unit would have to guarantee error-free '.' VEn do without the information comparison and always process the last information received. The synchronous mode of operation is therefore not suitable for the use of comparison methods for rapid error detection . To enable rapid error detection and the security required for important data and programs ensure, so both storage units are parallel and operated synchronously. The synchronous operation of both storage units is guaranteed if every processing unit in the system is connected to both storage units calls for memory cycles at the same time. The following applies restrictively for a storage unit made up of several storage banks, that the cycle requirements in both memory units relate to the same memory bank.

A distinction must now be made between several cases when operating the system. Are the memory areas in both memory

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are filled and grounded with the same programs and data if they are changed simultaneously in both storage units during operation, then the "two storage units." identical at all times. Comparators in the storage units check those of parallel, identical ones Processing units incoming information. Check comparators V1, V2, V3 in the processing units analogous to the information offered by the storage units. In the event of a comparison error message in the Storage units, the error can be localized immediately to the two processing units. A failure effect This avoids affecting the entire system. There is only the following operating option in terms of traffic of the processing units with the storage units: write identically - read identically. The identity of Information and control signals is through comparators V1, V2 and V3 in the processing units VE1, VE2 and VEn monitored. An additional statement about the correctness of information and control signals is obtained through a parity check in the storage units themselves.

In the case of lower security requirements for some of the data and programs, it is advisable to use the memory areas Partly identical in both storage units, partly not to be assigned identically. The condition for synchronous traffic with both storage units is also met here if cycle requirements for identical and non-identical Storage areas are always directed to both storage units. Each processing unit gives with its cycle request the additional information about the type of their traffic (identical in both storage units, not identical the memory unit SE1, not identically to the memory unit SE2). Does the additional information mean that the cycle request relates to identical memory operations in the Refers to storage units (g.3 '. Write identically, identical

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read table), the cycle of both storage units allocated synchronously. However, if the processing unit requests a non-identical execution of the operation, it is Cycle allocation simulates the cycle sequence of the memory unit that is not supposed to carry out the desired operation. The storage unit behaves outwardly as if it were handling the cycle; she leads them However, surgery does not stop there. An empty cycle thus runs in the storage unit »Reverse the processing units with identical memory areas, they evaluate incoming control and information signals from both memory units. Immediate error detection is possible by comparing control and information signals. If the processing units deal with non-identical areas, they compare incoming control signals, however, depending on the content of a register, ignore the information offered by the storage units.

The following operational options arise when the processing units communicate with the storage units: a processing unit requests identical writing and identical reading. The identity of control and information signals from the storage units is thereby determined Comparator checked in the processing unit. An additional A statement is made by checking the parity in the storage units. With this operational possibility So there is no loss of security. The security is the same as with synchronous operation with identical memory contents. The processing unit can also be identical Encourage writing and non-identical reading. In this case, the control signals of the storage units checked for identity by comparators in the processing units. A statement about the correctness of the information can only be obtained through parity control in the storage units. As in both storage units

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is written identically, the programs and data in both storage units are up to date. The processing unit can ultimately also require non-identical writing and non-identical reading. Also in this Pail becomes the identity of control signals of the storage units through comparators in the processing units checked. A statement about the correctness of the information can be made by means of a parity check in the storage units to win. The programs and data are only in one of the Both storage units are up-to-date. This means that storage space is saved at the expense of security.

As described, mixed identical and non-identical Traffic with the storage units of the synchronous operation is maintained by executing idle cycles. The idle cycle goes for other, non-identical cycle requests lost. Figure 2 shows the timing. The processing unit VEn requests a non-identical one Cycle in the memory unit SE1; To maintain the synchronism there is an empty cycle in the memory unit SE2 (shown in dashed lines) executed. The processing unit VE2 requests a non-identical cycle in the storage unit SE2; by executing an idle cycle in the memory unit SE1, the synchronism is maintained. The processing unit VE1 requests an identical cycle in both storage units. With an improved Embodiment of the invention now avoids having to use the idle cycle for other non-identical cycle requests get lost. Namely, if a processing unit requests a non-identical operation execution, so. can at the Storage unit that is to perform an empty cycle, - the Cycle to another non-identical requesting processing unit be awarded. This is shown in FIG. The processing unit VEn does not make identical requests a cycle in the memory unit SEI. To maintain

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To maintain synchronism, an idle cycle would have to be carried out in the memory unit SE2. The processing unit However, VS2 has at the same time directed a non-identical cycle request to the memory unit SE2. The memory unit SE2, which would have to perform an idle cycle, now assigns this cycle the processing unit VE2. A real cycle is now carried out in both storage units SE1 and SE2. The memory cycles requested by the processing units VE2 and VEn are not sequential, but rather settled at the same time. In this way the Increase the number of memory cycles available in the system.

In a data processing system with storage units which are composed of several storage banks, it can it can happen that the cycle requirements of two processing units that are not identically demanding lead to different ones Lead memory banks of a storage unit. So I would for example the non-identical cycle requirement of the Processing unit VSn in the storage unit SS1 lead an empty cycle in the memory bank χ of the memory unit SE2 (Figure 3) and sets up the processing unit VE2 at the same time a non-identical cycle request to the memory bank x + 1 in the memory unit SS2, see above an idle cycle must be processed in order to maintain the synchronism in the memory bank x + 1 of the memory unit SE1 will.

This improved method has the following operational possibilities for the traffic between processing units and storage units. A processing unit may require identical writing and identical reading. The identity is based on control and information signals both storage units monitored by comparators in the processing units. His additional statement

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The correctness of the information can be obtained by checking the parity in the storage units. the
Processing unit can also request identical writing and non-identical reading. In this case only will
the identity of control signals from both storage units is monitored by comparators in the processing units. A statement about the correctness of the information is obtained by means of a parity check in the storage units. Since both storage units are written identically,
the programs and data in both storage units are up to date. However, its processing unit can also request non-identical writing and non-identical reading. In this case too, the identity of
Control signals of both storage units checked by comparators in the processing units. Error detection in information signals is possible through parity checks in the memory units. The programs and dates are
however, only one of the two storage units is up-to-date. There is thus a saving in storage space and a gain in storage cycles at the expense of security.

3 claims
3 figures

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Claims (2)

Claims ι \ l Method for operating a program-controlled data processing system with several processing units that can be connected in parallel and at least two memory units that work in parallel and synchronously, in which the information and control signals output by system units that work in parallel are compared and, in the event of an error, the transfer of the information to the corresponding system units is prevented , characterized in that a processing unit (VE) requiring a storage cycle directs a request for the allocation of a storage cycle to all storage units (SE1, SE2) at the same time, that the requesting processing unit sends out additional information before the storage cycle is allocated, with which a storage unit, in which the desired memory operation (eg reading, writing) should not be carried out, if necessary, is notified that all memory units with the requesting processing unit simultaneously the gl Exchange calibrate control signals and that a memory unit notified by the said additional information does not carry out the desired memory operation ("empty cycle ¹¹ ). 2. The method according to claim 1, characterized in that that a first memory unit which, during a memory cycle, is received by a first processing unit does not carry out the requested operation, allocates this storage cycle to a second processing unit, the execution of an operation in the first and the non-execution of this operation in the second storage unit required ("allocation of idle cycles"). VPA 9/240/0037 - 13 - 40981 Ul 1052 Method according to claim 2 for operating a data processing system, in which each storage unit is made up of several storage banks, characterized in that, that to maintain synchronism between the storage units in the memory bank χ in the second game unit is more likely to have an empty cycle, if the cycle requests of the first and second processing units to different memory banks of the first The memory unit and the second processing unit make their cycle requirements to the memory bank χ of the first Storage unit sets up. VPA 9 / 24Ü / UJ37 40981 kl 1 Q 52 Blank page