DE2244798B2 - In itself fault-protected circuit arrangement with semiconductor components for suppressing interference pulses - Google Patents

Description

3 4

len edge triggered. Edge means the reduction of the switching times. In addition, it is so the state of the transistor 5 from blocked to conducting slowly that possibly still through to this stage or vice versa. In the case of steep edges, that is, interfering signals that come quickly, are not sufficient to switch them through, the evaluation winding outputs 4 control interfered signals. The capacitor 10 is just like the construction, the subsequent storage cores incorrectly 5 part 6 designed as a Miller capacitor,
head for. The input stage with the transistor will control the transistor 5 to avoid these errors. For this purpose, the capacitor 6 is also expediently used as a Darlington stage. This capacitor is implemented. This gives a high current gain known as a Miller capacitor. Such capacitors so that the connected Miller capacitor only needs to be between the base of a transistor and reach small values,
the collector of the same transistor. Components of this In F i g. 3 is the design of the capacitors 6 arrangement, however, have the disadvantage that they and 10 are shown. By being able to change the Zusich in such a way that their effect is the same as guides to the transistors in printed scarf zero. However, this means that the operation of the device is to be carried out, which are rendered superfluous by clever arrangement circuitry. 15 connection of the connecting cables between the base

After the circuit arrangement according to the invention B or B ' and the collector connection C or

voltage, the Miller capacitor 6 is switched so that C ″ of the transistors 5 and 7, respectively, capacitances are achieved.

important currents flow through its coverings. These capacities are due to the design, but achieve

be sen. The collector current of the transistor 5 the required sizes.

leads over one layer and the base current over 20 When using a Darlington amplifier is the other layer. In the event of a short circuit of the capacitor in connection with a resistor, a very low capacitance, the base-collector path is closed for effective interference suppression and the transistor 5 acts as a diode. Sufficient for that. In addition, the Darlington means that no more pulses are delivered to the switching ring amplifier to use a relatively kernl. When a connection of the Kon-25 high base series resistor. The capacitor 6 can therefore be torn off if the collector or base capacitor or 10 is advantageously interrupted in the form of a current and this also leads to a printed circuit being executed.
Circuit breakdown. Behind the output A of the invention

To further suppress the interference pulses, the circuit arrangement can andurch further stages the fast through-switching of the transistors 30 must be ordered in order to produce additional delays, is behind the switching ring targets according to the invention. These steps are then also so peeled 1 a Darling controlled via /? C elements that the delay at the input and at the arranged tone level. This stage is also used to make the exit.

1 sheet of drawings

Claims (3)

1 2 is deleted again. Although this circuit is largely patent claims: going independently of the tolerances of the compo elements, but the silicon transistor 1. In this respect, fault-protected circuit arrangements due to their high cut-off frequency tion with semiconductor components for suppressing 5 disadvantageous than by the steep switching edges of the sikung of interfering impulses from interrupter cores of silicon transistors interfering impulses on the Auswertwick superstructures logical connection modules, especially after the setting has subsided marked that one-pulses can arise. These glitches can hand, the control electrode of the respective semi-lead to undesirable malfunctions, such as Ladder component (5 or 7, 8) with the one io hand of the in F i g. 1 characteristic curve of a Coating of a capacitor (6, 10) and other switching ring core is to be explained in more detail. on the one hand, the collector electrode with the other loading In F i g. 1 with H 1 is the field strength of the setting pulse lag of the capacitor is connected. ses, which after its subsidence in 2. Add to error protected Schaltungsanord- the core, the remanence induction Bl causes, with voltage semiconductor devices according to check 15 Upon application of an erase pulse of the field strength saying 1, characterized in that the basic H 2 is remagnetized the core. The here he and collector supply lines form the capacitor (6, followed useful induction stroke Δ B _n generated in a 10). Evaluation winding a corresponding voltage 3. In itself fault-protected circuit arrangement pulse. If there is only one set pulse, the voltage with semiconductor components according to the An 20 core performs an induction stroke of the amount AB ₅ . spoke 1 and 2, characterized in that the hub Δ B _s induces a small interference pulse in the evaluation winding of semiconductor components in Darlington circuit, which can be processed by silicon transistor circuitry or in a voltage amplifier circuit and subsequent cores are ordered. erroneously drives. 25 Other known circuits therefore also work the slow germanium transistors. The object of the invention is to provide a simple, to create cheap and fail-safe circuitry for suppressing the interference pulses. The invention relates to an inherently faulty 30 The object is achieved in that on the one hand Protected circuit arrangement with semiconductor components - the control electrode of the respective semiconductor component to suppress glitches in Mentes with one layer of a capacitor and Logical connection made up of switching ring cores, on the other hand, the collector electrode with the other link building blocks. Coating of the capacitor is connected. To protect users and control 35 In a further development of the invention, it is proposed or control systems, for example at Kemreak- gen, that the base and collector feed lines gates, in the railway signaling technology or with Pres- capacitor and that the semiconductor building reading streets are fail-safe, binary working lanterns in a Darlington circuit or in a Spangik circuit required, the following condition amplifier circuit is arranged, must satisfy: 40 The invention is based on the knowledge that With a single fault in a component to suppress the interference pulses either the other Logic circuit allows an output that is relatively long on grand control of the switching ring core Input signals carries an O signal, no L signal must be sampled, or that an evaluator only has to obtain. If an error is not noticeable, longer pulses may respond or both 45 measures are not necessary at the same time due to the addition of a further error. L signals arise at an output. An embodiment of the invention To implement such a fail-safe Lo circuit arrangement is below with reference to the It is known gikschaltungen (DT-AS 12 25 078, Fig.2 explained in more detail. Fig.3 shows the design-DT-OS 19 22 125, CH-PS 4 18 398, Siemens-Zeit-dingte embodiment of the error-protected concript 42, 1068, H. 11, pp. 875 to 878), with three 50 capacitors. To use magnetic cores provided with windings, according to FIG. 2, the switching ring core 1 consists of a setting switch on an evaluation winding, only one winding 2, reading winding 3 and evaluation winding 4. Issue a pulse when the two other winding The points indicate the direction of the winding. The set windings either have pulses pending at the same time, or winding 2 is triggered via input E by the tranaber, the pulses on the two windings downstream of transistor 5 with a slow edge. Erander come and thus set the core and how long will this be deleted by the capacitor 6.. The same slowdown of the rapid southern The known arrangements, however, are not transistors able to deal with failure or change of a men. Here is a Dar component to increase the effect with absolute certainty an Aus 60 Lington stage, consisting of the transistors to suppress the input pulse. and 8, used. To increase the time constant is In a further known arrangement according to which the resistor 9 is provided, the one in conjunction with DT-OS 19 22 124, a switching ring core is reliably placed under one pulse by the capacitor 10 and suppressed by a second one. The output of the circuit is denoted by A set- directed pulse of a second winding 65 net. deleted again, with an on the evaluation winding. 2 closer connected transistor will only be briefly explained. The switching ring core 1 is when is controlled through if the previously set core of the capacitor 6 is not available, with a steep