DE2237559C3 - Monolithically integrated circuit arrangement for voltage stabilization - Google Patents

Description

^ Ν circuit arrangement according to claim Λ or 4 characterized in that the emitter zone (/ ■ ') opposite edge portions of all collector / {ones (' ( 'J are equal to each other in length.

The invention is based on a monolithically integrated circuit arrangement for voltage stabilization the end. as from "Proceedings of the IEEE", December IW), pages 21S0 21X1, in particular Fig. 2, known is this known circuit arrangement is shown in Fig. 1 of the accompanying drawings, wöbe.- an additional contradictory land is shown is.

The known stabilization circuit consists of the reference element Z, the voltage LJ _{x of} which represents the voltage to be stabilized. The current flowing through the reference element is essentially determined by the resistance value of the resistor R 1, which is connected as the emitter resistor of the npn-1 transistor T. About the diode-connected pnp transistor V ₁₁ , whose collector-emitter path connects the collector of the npn transistor T with the positive pole of the supply voltage source U _n , and the pnp transistor V ₁ , whose base-emitter path is the base Emitter line of the npn transistor T ₁ , connected in parallel, ensures that a current that is the same as the collector current of the npn transistor T also flows through the collector of the pnp transistor V and thus through the reference element Z.

The resistance R _:. which connects the reference element to the positive pole of the supply voltage source, serves as a starting resistor in order to ensure that the stabilizing circuit is in the stabilizing state when the supply voltage source is switched on. As can be seen, it has a bistable behavior with a non-stabilizing one as the second of the bistable states. Instead of the start-up resistor, a start-up device operating by means of pulses can also be provided.

As can be seen, the known circuit shown in FIG. I for the two pnp transistors is known from the "IEEE Journal of Solid-State Circuits", Vol Principle of constant current source use. The use of a starting resistor in a circuit arrangement for voltage stabilization is known per se from the French publication 2 038 754. This circuit arrangement differs from the circuit arrangement according to Iig. I only through the use of a series connection of resistor and diode instead of the pnp transistor V ₁₁ connected as a diode.

/ ur power supply monolithic intcgricrlcr The known circuit arrangement can be expanded to the effect that not just a single referral. but a Series connection of several Refereii / elements is used, whereby the. respective prevention points the one / a retean / elemenle different sized stabilized tensions take off can. Transistors connected as diodes are used as reference elements in a known manner, either in the direction of flight or in the reverse direction up are betrayed into the Abhruchgehiet.

The invention is thus monolithic integrated circuit arrangement / ur Spürsungsstabilisierung with a series connection of Reicren / elements as Stabilisierelt: mente, on the several stabilized voltages can be tapped, furthermore with an npn transistor, whose Bavis at the tap point the smallest / u stabilizing voltage, whose emitter has a resistance at the circuit zero point and its collector at the base and collector of a first pnp transistor connected as a diode is whose emitter is connected to the supply voltage source c, also with a Starting resistance, which is used to tap the smallest voltage to be stabilized with the supply voltage source connects or with a starting device working by means of impulses, and finally with a second pnp transistor, the collector of which is connected to the series connection of Referen / elementcn. whose Emitter connected to the supply voltage source and its base connected to the base of the first pnp transistor is.

The circuit arrangement, however, has the disadvantage that it stabilizes the voltages that can be tapped off only starts when the supply voltage is slightly higher than the highest to be stabilized Tension. It is often necessary that the lowest voltage to be stabilized after applying the supply voltage Starts as early as possible, so that the basic functions of the integrated circuit can be used immediately to make operational. The voltage stabilization circuit of the type mentioned has the other The disadvantage is that short-term reductions in the supply voltage, as is the case, for example, in on-board networks of vehicles and aircraft often occur the stabilization function of the series connection can go out of operation, whereby all voltages to be stabilized fail.

Ms is therefore an object of the invention to provide a circuit arrangement for voltage stabilization of the stated type such that the each remain stabilized as long by means of the series circuit to be stabilized voltages as the ersorgungsspannung respectively above the value to be stabilized is ^v. In other words, the invention is intended to create a voltage stabilization circuit in which all of the voltages to be stabilized are still present that are below the dropped value when the supply voltage drops.

In a circuit arrangement of the type mentioned, this is achieved according to the invention in that each tapping point of the series circuit via the collector-emitter strccke of a further pnp transistor is connected to the positive pole of the supply voltage source and that the bases of the further pnp transistors are connected to the bases of the first and second pnp transistors.

Through this training it is achieved that each too

maintain stabilizing tension for so long

remains how the supply voltage does not drop below the / u stabilizing value. This gives the advantage that in one with the circuit arrangement according to the invention equipped integrated circuit, for example, existing memory functions so remain undisturbed for a long time, as the supply voltage

niing not below the smallest voltage to be stabilized sinks.

The circuit arrangement designed according to the invention for voltage slimming can be particularly useful realize advantageous in that all

¹ S PNP transistors can be designed as a single lateral transistor with several collectors. In this case, this lateral transistor can advantageously be designed in such a way that the emitter / one is arranged in strips in the center of the base zone, so that the individual

ao nen collector zones along the circumference of the emitter zone and these are arranged opposite and that with the tap of the smallest to be stabilized Collector zone connected to voltage additionally the remaining collector zones in the form of a

a5 enclosed in a closed frame.

As will be explained in detail below, the single lateral transistor can be advantageous however, they can also be designed so that the emitter zone in the center of the base zone is strip-shaped is arranged that the Kollcktorzone of the first, the second and to tap the smallest to be stabilized Voltage belonging pnp transistor along the circumference of the emitter zone and this opposite are arranged that with the

second largest voltage to be stabilized connected collector zone of the collector zone of the second pnp transistor, without facing the emitter zone, is arranged opposite that with the third largest voltage to be stabilized

Bound collector zone of the collector zone connected to the second largest voltage to be stabilized, without being opposite the emitter zone, being arranged opposite, etc. up to with the second smallest voltage to be stabilized connected

those collector zone and that the collector zone connected to the lowest voltage to be stabilized additionally encompasses the remaining collector zones in the form of a closed frame.

Both mentioned advantageous embodiments of the lateral transistor are suitable for the specified one This is particularly useful if the edge parts of the collector zones opposite the emitter zone are un are equal in length to each other.

The invention will now be based on the in the drawing

2 to 6 illustrated further FIGS tert.

Fig. 2 shows the circuit arrangement according to the invention for voltage stabilization in their eyes my shape;

Fig. 3 shows a circuit according to the invention Order for voltage stabilization for two voltages to be stabilized;

F i g. 4 shows the arrangement of the individual zones of the pnp transistors according to an advantageous embodiment leadership style;

Fig. 5 shows the arrangement of the zones of the pnp Transistors according to another advantageous embodiment. and

I-ig. (ι shows the results from all embodiments according to FIGS. 4 and 5 resulting arrangement of tier zones the pnp-Tninsistoreii for the circuit according to I- ig. 3.

The Iig. FIG. 2 shows the circuit arrangement for span stabilization according to the invention in its general form. The interconnection of the two pnp transistors V _n and V ₁ . of the start-up opposing country Rl, the npn transistor / and the E-.mitterwiderstan of the R \ is identical to that of Fig. I, while the reference / element / according to FIG. 1 by the series connection of the reference elements Z ₁ . Z ... Z ₁₁ and Z "is replaced. The order in which the components are numbered is chosen so that the reference element Z _{1 is} connected to the collector of the second pnp transistor V, while the last reference element Z _{11 of} the series circuit is connected to the circuit zero point.

At the series connection of these reference cells, as many stabilized voltages can now be tapped as corresponds to the number of reference cells. In Fig. 2, these voltages are entered with the reference _{symbols C 1} ,, (. ', _... C ₁₁₁ ,, C _vl , and C ₁₁₁ , namely the respective voltage from the collector of the second pnp transistor V ₁ from the point of view of this, it was removed in front of the reference element of the same index.

To solve the problem on which the connection is based and presented above, each tap point of the series connection of the reference elements, i.e. each connection point of two adjacent reference elements, is now connected to the positive pole + of the supply voltage source U _{11 via a further pnp-1 transistor in the manner according to the invention} the collector of this respective transistor at the corresponding tap point, the Fmittcr at the supply voltage source U ₁₁ and the base at the bases of the first and second pnp transistors 7 " _n and 7 '|. Thus, the base-F.mitter path of the respective Another pnp transistor, the base-F-middle section of the first and second pnp transistor in parallel.

In detail, the collector of the further pnp transistor V, is connected to the connection point of the reference elements Z ₁ and Z ₂ , or, in other words, the collector of the further pnp transistor is, viewed from the collector of the second pnp transistor 7 ″, before respective reference clement of the same index.

So is the collector of the further pnp transistor T _n , before the reference element Z _n . ₂ connected, ie at the connection point of this reference element with the reference element Z ₁₁ , not shown in FIG. The last two further pnp transistors V ₁₁ and T _n are consequently connected to the connection points between the reference elements Z ₁₁ and Z ₁₁ , or Z ₁₁ and Z ₁₁ .

For the graphic representation of the reference numbers Z ₁ ... Z ₁₁ in Fi g. 2 the symbols for Zener diodes and diodes were chosen to indicate. that both types of components can be used to form the series connection of the reference elements. The diodes are then polarized in the forward direction and the Zener diodes in the reverse direction. In detail, the reference elements Z ₁ , Z. are shown as Fhißdiodcii, while the reference elements Z ₁₁ .. Z ₁ , and Z ₁ , indicated as Z-diodes -this chosen sequence is arbitrary, however, and any other sequence can be be selected, although the last Rcleicnzelenienl Z _{11 should be} a / -diode or no Flußdiodc, so that the current in the resistor Rl is better adjustable

The I ίμ 3 show! the circuit arrangement for stabilizing voltages C, and f ', derived from the general form of the circuit arrangement for stabilization according to FIG.
In the present case, the series connection of the reference elements consists of the series connection of the two reference elements Z ₁ and Z, for which the /. diode symbols were selected

The series connection of the Hcferenzclemcntc has

»5 thus a single tapping point aiii, at which the stabilized voltage C _v . is grazed off. diesel

Point is in crfindungsgemalicr manner übet the koi lecturer-Lmittcr path of the further pnp-'l ransistois T ₁ with the posi then pole of the supply voltage source connected to C _0. The special coupling of the other components of FIG. 3 is identical to that of FIG

While in the I i g. I to 3 show the circuit arrangement according to the invention for voltage stabilization shown as a sound image, the I ig. 4 to U show the outline of an advantageous structure of the pnp transistors in the monolithic integrated circuit. It is particularly advantageous here if the pnp-I transistor terminals are implemented as a single lateral transistor with the corresponding number of individual collectors.

The characteristics, the structure and the mode of operation of such lateral transistors is from "Proceeding" oil the IF.FF ", December HXvI. Pages 14 ¹ M to 14S »5 known per se. A lateral transistor of a monolithic integrated circuit is understood to be a transistor whose current flowing from the Kmittcr via the base to the collector is essentially parallel to the main surface of the integrated circuit, while, in contrast, the transistors usually formed in monolithic integrated circuits have a collector-Hmitlcr current circuit have perpendicular to this surface.

Such lateral transistor ^ are in particular added suitable. pnp-Transistorcn in monolithically integrated!

Circuits that usually use npn transistors mi

have the mentioned vertical current flow, realize zi. For this purpose, usually n-lciten the. mostly through cpitactic growth

Area of the monolithic integrated circuit

next by introducing the so-called Isolationsdiffusioi

individual ge from each other by p-conductive material separate areas generated.

These are separated from each other by pn transitions

th areas can now either be used to build an npn transistor or to build a lateral!

PNP transistor can be used. Here this is n-lci lende area acts as a collector of the npn transistor

sam or as the base of the lateral transistor. By means of de in the case of the npn-1 transistor, the base zone is formed by liindiffu sion of p-line generating disruptionsci

the p-conducting Ge

bid for the middle zone and the collector zone which are adjacent to each other on the semiconductor surface are arranged at a prescribed distance. here

in the case of the arrangement of the collector zone according to de

mentioned 1st literature passage should be chosen so that si <

»Lic- Fmilterzone as a geometrically closed l'orn

encompasses.

The use of several interconnected in the manner of a multiple constant stream pnp-Transi.storen in an integrated circuit is also already known per se, see »IKEE Journal of Sold-State Circuits ", April 1972, pages 105 to 111, in particular Fig. 4 on page 107. This figure shows a strip-shaped litter zone around which the individual collectors are arranged are.

Notwithstanding this structure, a lateral transistor having a plurality of collectors of the lateral transistor is configured to realize the Stabilisicrungsanordnung invention so that and these are disposed opposite corresponding to those shown in Figs. 4 to 6 different embodiments Although individual ones of the panels along the likewise strip-shaped emitter region E, However, that one of these collector zones, namely the collector zone Cj ₁ of the further pnp transistor T _n connected to the lowest voltage U ^ _n to be stabilized, is arranged opposite both the limitter zone E and surrounds the other collector zones in a frame-like manner with part C ₁₁ .

The embodiment of the lateral transistor shown in FIG. 4 initially shows in detail the insulating zone / which surrounds the entire structure in a frame-like manner and which has been created by the insulation diffusion mentioned. Within this insulation zone is the base zone R. which is provided with the base contact B ' on the right edge. The dashed line indicates the extent of the so-called buried layer BL , which is arranged below the individual zones in the semiconductor body and which, as is known, serves to reduce sheet resistances.

In the center of the base zone, the strip-shaped emitter zone E drawn with hatching pointing to the right can be seen, around which the individual collector zones hatched to the left are arranged, in such a way that, according to the current flowing through the individual collectors, a more or less smaller Part of the collector zone opposite the emitter zone. The value of the current flowing through the collector is determined by the edge length of the part of the respective collector zone opposite the emitter zone.

The arrangement of the collector _{zones C 11 ... Cj 1} _ is arbitrary in the exemplary embodiment in FIG. 4. For example, the collector zone C _{11 of} the first pnp transistor T _{0 is designed in} such a way that it surrounds one end of the emitter zone E in a U-shape, while the collector _{zones C 1} ... C _n _, are also strip-shaped and the emitter zone in each case opposite.

The collector zone C _n , which surrounds the remaining collector zones in a frame-like manner with the part C _n , is designed in the exemplary embodiment according to FIG. 4 in such a way that it has two portions with which it faces the emitter zone E and can thus accept current from this emitter zone. However, this design is not mandatory, but it is also possible to provide this collector zone with only a single sub-area which is opposite the emitter zone E.

As can be seen, the lateral transistor according to FIG. 4 contains six individual collector zones. Thus, the collision zone is Cj, ·. with the collector zone (\, the collector / one (J ₁ , with the collector / .onc C ₄ and the

Collector _{zone C 11} with the Kolleklor / one C, identical.

which he / ugs / cichen are attached in brackets.

The mode of operation of the switching arrangement according to the invention / in stabilization with the form of implementation for the lateral transistor according to FIG. 4 is that when the supply voltage U ₁₁ falls below the value of one of the voltages to be stabilized, for example when the Vcrsor-

to the voltage to be stabilized below the value of the voltage to be stabilized (/ ,, the Kollcklor fimitter voltage of the associated first pnp transistor T ₁ / collapses and thus in the reference element Z, no more current flows, but through the other pnp

»5 transistors 7, .. / 'nor current is fed to the remaining part of the series circuit of the Refcrenzclemente, so that only the stabilized voltage U _s ι is no longer present. Here, the above-mentioned collapse of the collector-emitter voltage of the second pnp transistor T corresponds to an operating mode in which this transistor is saturated and the saturation current, due to the blocking effect of the buried layer, flows off laterally across the isolation zone to the substrate of the integrated circuit.

* 5 would be if the frame-shaped part C _{11 of} the collector / one Cj _{1 did not take over} the saturation current of the respective transistor. The embodiment of the invention according to FIG. 4 is thus based on the knowledge. to supply the saturation current through the mentioned design at least to the reference element of the smallest voltage to be stabilized again, which happens because the collector of the transistor or transistors that have reached saturation then _{acts as an emitter for that part of the frame C n} which this now opposite the collector acting as an emitter.

If the supply voltage U ₁₁ drops further, further voltages to be stabilized can be put out of operation one after the other, but only those will fail whose value is greater than the reduced supply voltage, while the rest are maintained.

Due to the failure of the no longer stabilized

When the supply voltage drops, the total current in the series connection of the reference elements naturally changes in such a way that different currents flow through the other reference _{elements Z, ... Z 11} , with the exception of the reference element Z _{n belonging to the lowest voltage to be stabilized} while the current through da: reference element Z _n remains constant. This leads to a change in the stabilized voltage, which can be disadvantageous depending on the required quality of the stabilization, especially in the case of the flux diodes due to their characteristic curve.

In order to avoid this disadvantage, it is advisable to use the collector zones of the transistors T ₁ ... T ₁

βο according to the in F i g. 5 to be arranged. In contrast to the arrangement according to FIG. 4 only noct the collector zone C _{11 of} the first pnp transistor, di <collector zone C _{x of} the second pnp transistor and di <collector _{zone C n} of the transistor de emitter zone E connected to the smallest voltage U _1n to be stabilized. In contrast, the remaining collector _{zones C 2} ... C _n ., In terms of area, are "connected in series" in such a way that

ίο

sic, starting from the collector / .one (, of the second transistor, follow one another according to the respective index.

On the one hand, the collector / one C. of the wide pnp transistor Y _{1 is arranged} in the same way as the collector / one C _{11 of} the first pup transistor / ,, in such a way that these two collectors / oncn each have the encompass one end of the loop-shaped hniitter / one E U-shaped. The collector / one C, of the second pnp transistor is then encompassed by the collector zone C of the / far highest /.u stabilizing voltage (/, connected transistor I , again U-shaped, which U-shaped encompassing arrangement up to /.ur Collector / one C _n , of the transistor T _n connected to the / wcit smallest voltage to be stabilized U, " , connected.

In the exemplary embodiment of FIG. 5, a further collector zone is indicated compared to that of FIG. 4, namely the collector / ones C ₁ , so that this lateral transistor has seven collector / ones corresponding to seven / u stabilizing voltages. Accordingly, the collector / one corresponds to C _n . the collector zone C ₄ , the collector zone C _n , the collector zone C ₄ and the collector / one C _{n of} the collector zone C _h , which reference numerals are again attached as in FIG. 4 in brackets.

The special arrangement of the individual collector zones as a flat "series connection" ensures that the saturation current flowing immediately to the collector C _{n in the arrangement according to FIG} in turn acts as an emitter. Due to the corresponding spatial arrangement in series and the fact that when the supply voltage U _n drops, the individual voltages to be stabilized inevitably fail one after the other and thus the assigned pnp transistors also become saturated one after the other, the effect of the respective current transfer from one to the other collector zone occurs , starting with the collector zone C ₁ , up to the collector zone C _n .

Thus, however, the series connection of the reference elements in the event of insaturation gcraten of the individual No current is drawn from pnp transistors, but rather the saturation current of the transistor that has become saturated flows back to the series circuit via the collector zone of the adjacent transistor. In order to but occur within the series connection of the reference elements in the event of failure of individual elements to be stabilized Voltages do not show any changes in current, so that the stabilized voltages that are still in effect through the Failure of the others did not experience any change.

Building on the above-mentioned knowledge, the further development of the invention is therefore still possible one step further and expands the principle of the utilization of the without this measure to the Substrate draining saturation current on each of the pnp transistors with the exception of the frame-internal Part having transistor.

Although in the exemplary embodiment according to FIG. 5, the individual areas arranged one behind the other in terms of area

ίο Collector (s) are shown encompassing each other in a U-shape, this training is not mandatory. An arrangement would also be conceivable in which one collector zone is arranged as a strip behind the other. It must only be ensured that the downstream collector zones of the emitter zone E are not directly opposite, but only across the respectively preceding collector zone.

The other details of the embodiment according to FIG. 5 are the same as in FIG

ao also the embodiment according to FIG. 5 the insulating / one /, the base zone B, the buried layer BL and the base contact B ' .

Finally, FIG. 1 shows the arrangement to be derived from FIGS. 4 and 5 for the circuit according to FIG. 3. This ensures from the outset that the collector zone of the transistor connected to the smallest voltage U _sl to be stabilized is in the manner of FIG g. 5 is arranged in terms of area after the collector zone of the transistor T, belonging to the highest voltage to be stabilized, U. For the rest, FIG. 6 corresponds to FIG.

Particularly advantageous conditions result when in the exemplary embodiments according to FIGS to 6 the edge parts of the respective collector zones opposite one another from the emitter zone are of the same length, since the same currents then flow in the individual transistors. This is in Fig. 6 with respect to these dimensions are taken into account, in which the edge lengths are drawn according to this teaching are, taking into account that it goes without saying that in the corner areas shown in dashed lines no injection occurs towards the respective collector zone.

Although in FIGS. 4 to f> the emitter zone as rectangular narrow strip is shown, this training is by no means mandatory. So can of course the emitter zone also in the form of a more or less strongly curved strip or also pre-cut in the form of a bent line

hen will. The related formation of the emitter zone can thus be based on the respective application selected and the area available for the lateral transistor of the integrated Circuit to be adapted.

For this purpose 2 sheets of drawings

Claims (4)

Patent claims: Ionolithically integrated circuit arrangement Voltage stabilization with a Kci- I. Wed Voltage stabilization connection of refers / elements as stabilization belts, on which several stabilized voltages can be tapped, furthermore with an npn transistor. whose base is at the tap point of the smallest voltage to be stabilized, whose> ° emitter is connected to the circuit zero point via a resistor and whose collector is connected to the base and collector of a first pnp transistor connected as a diode, whose emitter is connected to the supply voltage source, furthermore » 5 With a starting resistor that connects the tap of the smallest voltage to be stabilized with the supply voltage source, or with a linear starting device that works by means of pulses and finally with a second pnp- ^ao transistor, whose collector is connected to the series connection of reference elements, whose emitter is connected to the supply voltage source and the base of which is closed at the base of the first pnp transistor, thereby identified. »5 every tap point of the series circuit is connected to the positive pole} +) of the supply voltage source ((/„) via ♦ lic collector-F.mitter path of a further pnp transistor (7 ", ... T _{11) and} that the bases of the other pnp 3 "transistors are connected to the bases of the first (T ₁₁ ) and the second pnp transistor (T 1). 2. Circuit arrangement according to claim I, characterized in that all pnp-Transi-Ktoren (T ₀ ... V ") as a single one; Lateral transistor tn with several collectors (C ₁₁ ... C ₁₁ ) formed child. 3. Circuit arrangement according to claim 2, characterized in that the lateral transistor is designed such that the emitter zone (E) is arranged in strips in the center of its base zone (B) _{, that the individual collector zones (C n} ... C ₁₁ ) along the circumference The emitter zone is arranged opposite it and (that the collector cone (C ₁₁ ) connected to the tap of the smallest voltage to be stabilized (L / _(B )) additionally the other collector zones (C _n ... C,) in the form of a closed frame ( C _n ) encompasses. 4. Circuit arrangement according to claim 2, characterized in that the lateral transistor is designed such that in the center of the base zone (ß) the emitter zone (E) is arranged in strips that the collector zones (C ₁₁ , C ₁ , C _n ) of the first _{, of the second and of the pnp transistor (T 0} , T ₁ , T _n ) belonging to the tapping of the smallest voltage to be stabilized (i /, ") are arranged along the periphery of the emitter zone and opposite this, so that those with the second largest to be stabilized The collector zone connected to the voltage (L / ,,) of the collector zone of the second pnp transistor (V ₁ ), without facing the emitter zone, is arranged opposite one another so that the collector zone (C ₁₁ ,) the collector zone (C) connected to the / by far greatest / u stabilizing voltage, without the emitter / one being superimposed, etc. up to / ur m'iΓ the / by far smallest voltage to be stabilized ung (L ',,,,) connected collector «« *: ι (·) and that the voltage ((/ „) \ crbimdciie Kollcklor- / nnc (C) with the smallest / ti stabilizing voltage (C) additionally the other collectors in Form of a closed frame (C ',.) Around-