DE2226778B2 - Arrangement for the addressed transmission of digital data - Google Patents

Description

is seen that is used to determine the data bit periods of each equally spaced transition recorded,

c) that a further scanning device in each station provided that a special transition in each set · the equally spaced Transitions detected and

d) that a control device is provided in each station, which when detecting the special Transition supplies the signal level of the address signal as an address bit to the address register.

The address signal thus not only contains the address bit or data bit information; it contains also one which cannot be influenced by the modulation with the data bit information and is sinfully available Synchronization information. The synchronization information lies in the equally spaced transitions, while the address bit or data bit information is at the level of the address signal. The important for the transmission of digital data As the exemplary embodiment shows, synchronization information can easily be obtained by monostable multivibrators be separated.

An embodiment is preferred in which the generator circuit periodically generates a sequence of address bits generated, in the bit pattern from address signals forming groups of consecutive address bits occur once within this sequence. For example, the generator circuit should have a sequence of M-bits with a non-repeating sub-sequence of N-bits. Any substring of JV bits should form the address of a single station. With each newly generated bit in the sequence of N-bits, a new address consisting of the N-bits becomes a different, individually located address Station determined.

The invention enables the use of a code comprising characters (i.e. binary digits or Bits) over a transmission channel in a consecutive Row can be transferred. Synchronized with this transmission can be addressed Data at points in time that are determined by the. Address determined be read from the series or included in it. be special in the transmission channel address bits (either "1" or "0") are represented by a code. Of the The code contains the synchronization information which is taken from each individual station and each address bit period in a plurality of equal lengths, extending over the entire address bit period each of these sub-periods results in a data bit period, in which a single data bit can be fed to the transmission channel.

It becomes an address signal format with a plurality of equally spaced signal level transitions in each Address bit period used In this way, a plurality of data bit periods are used in each address bit period Each individually located station has facilities that allow the occurrence of each of these Scan equally spaced signal transitions. In addition, facilities are provided in each station which make a special transition out of the equidistant ones occurring in each address bit period Scan transitions and derive an address bit synchronization from this. That accordingly The signal format selected according to the invention enables data bits to be synchronized with the transmission channel for this purpose each data bit is a special section of a data bit period. In the following the invention will be explained in more detail with reference to drawings.

F i g. 1 shows a block diagram of a data transmission system according to the invention;

Fig. 2A shows a diagram with a typical sequence of M-bits (M-16), the 2 " (N = 4) simply

ίο has existing sub-sequences of N-bits;

Figure 2B shows a block diagram of a preferred one Embodiment of a network with 4-stage sequential logic, which in FIG. 2 A shown M-bit sequence generated;

F i g. 2C shows a block diagram of a preferred embodiment of a network with 6-stage sequence ^{logic which generates an M-bit sequence with 64 (2 e} ) 6-bit sub-sequences that are simply present; F i g. 3 shows curve shapes in a diagram

ao of a preferred code format according to the invention, which contains both address and data information and that it enables stations connected to the transmission channel, in addition to the Address and data information both an address

»Gain 5 senbit and data bit synchronization;

F i g. FIG. 4A shows a diagram with waveforms which explain how from one in FIG. 2A shown Address bit sequence a signal format according to FIG. 3 generated can be;

4B shows a block diagram of an address generator with the follow-up logic from FIG. 2B, which shows that in FIG. 4 A generated signal format shown; F i g. Figure 5 shows a block diagram of a basic modem as part of a typical one on the transmission channel connected station.

In Fig. 1 shows a typical embodiment of a data transmission system. As in the following for a better understanding

v> purifies -is, allows the data transmission described. "ystem transmission of data from a delivery station in a variety of scattered stations to a destination station through a common channel. The destination station is any one of the plurality of stations. The channel can consist of a transmission medium, such as e.g. B. consist of two twisted wires, telephone lines; it can transmit by radio frequency or optical, etc., and it can use combinations of these transmission media. Apart from the type of channel used, the channel is operated using the time division multiplex method. A specific data word address is thus assigned to each specific time segment within an entire cycle of the system. Each remote station can respond to one or more of the data word addresses, and multiple stations respond to a single one of the data word addresses.

The typical in Fig. The system shown in FIG. 1 enables the transfer of addressed data between two Stations 10 in a plurality of stations 10 via a transmission channel 12. The stations 10 can be conventional in different ways. You are e.g. B. in three different ways divided into: a general purpose station 14, a computer station 16, and a data reading and recording station 18.

"General Purpose" Station 14

is] whom on ¹ mei rati sen> to do away with

Sta ode in! rec

Sta mo Be. an Eb leii 12 gu:

g * la ki d (

7 8

each station is designated, which is a basic modem and follows 16 addresses with 4 bits, which exist once. The at least one delivery and / or usage device address generator 20 from FIG. 2B therefore has an over-the-top appearance. As an output device, a general agreement with the special signal format, a station 14 serving my purposes can send a temperature address signal to the transmission channel 12, the temperature transducer which corresponds to one of the measured 5 of the M-bit sequence of the addresses from FIG. 2A Digital signal corresponding to temperature If the individual addresses A 1 to A 16 are also available. The user device is a device that responds to digital data moving 4 bits each through the address window 30, such as e.g. B. a display device causes a different address time gap device or a relay group. a station 10 for transferring the data to the

The term “computer” station denotes an xo transmission channel 12. At the same time, one or Station with a basic modem and a special multiple stations data from the transmission channel or general purpose computer that records 12.

in arithmetic operations z. B. evaluates, smooths or um- F i g. 2B shows a preferred embodiment

calculates. a follow-up logic, which the M-bit sequence from F i g. 2 A

The expression "reading and recording data" 15 testifies. It is true that countless configurations of the Station 18 designates a station with a basic sequence ^ gik a specific M-bit sequence. the execution modem and a device that is directly connected to the forms of FIG. 2 B and 2 C stand out for each-operator is related, such as B. but an input and output panel thanks to a minimal amount of components. One such for generating the desired M-bit sequence. the The device is easily transportable, is also an embodiment of the follow-up logic according to FIG. 2 B points easily at any point on the transmission channel four binary levels 34, which are in the form of a sliding 12 connectable and gives data to the transfer register. An output terminal 36 transmission channel 12 from or takes them up. each binary stage 34 is connected to an input terminal

In addition to the status described above, the following binary level is connected. The data transmission system according to 25 of the binary levels 34 has each functions with an input terminal 38 F i g. 1 an address generator 20, which is provided for shift clock pulses, which is connected to a transmission channel 12 successively address signals shift clock pulse generator. One feeds that define certain addresses. Each of the feedback logic 40 forces the binary stages 34 to output the M-bit sequence shown, which is connected to the transmission channel 12. The return ion 10 has at least one? assigned address. 30 logic 40 responds to an output signal of the fourth If an address in the transmission channel 12, 50 binary stage 34 appears and sends a signal to an input which the addressed station H> either receives data from the first binary stage 34. The feedback to the transmission channel 12 or data to logic 40 is based on the following algorithm: that in the transmission channel 12, depending on whether the verse output signal (ie the 4th binary level 34) station 10 works as a transmitter or as a receiver. 35 is fed to the input (ie the 1st binary level 34) so. The address generator 20 generates a long cycle until an already generated state in a sequence of M binary digits or bits occurs again in the following cycle. Then it is mentioned as an M-bit sequence. The M-bit sequence is preferably returned, except for the output signal itself, so that it does not repeat itself to a large number. If there are more than four binary levels 34, it may sometimes be necessary to fetch sub-sequences of N-bits, in the following 40, the exception in front of one again called -N-bit sub-sequence. Allowing every N-bit catching state to prevent a repetition sequence denotes an address of one of the stations 10 of the cycle before its maximum length. The address generator 20 generates each address one at a time. The maximum length is 2 ^V states at times in each cycle. The address generator 20 is N binary levels 34. The feedback logic 40 in FIG. 1 only has to provide for exceptions as its own with one end of the transmission.

Connection channel 12 connected station is shown He states 8 and 16 in the status table according to

However, it can be connected at any point of the transmission Fig. 2B as the only states of the sequence channel and is preferably not combined with one of 16 states by simply returning the stations 10 of ^the inverse output signal from the 4th binary level

2A shows a preferred M-bit sequence, the 50 34 to the input of the 1st binary level 34. Which defines the addresses of the stations ahead of the state 8 and the state 16 with several bits one after the other. In the following, the M-bit - Outgoing states both have a combination sequence (with M = 16) each with one bit per time - 001 in the 1st to 3rd stages 34. and move the feedback unit to the right in Fig. 2A. Therefore, within logic 40, in the example of FIG. 2 A and the M-bit sequence, each N-bit subsequence (with N = 4) 55 2 B is only based on the combination 001. A NAND only exists once. The sequence therefore corresponds to gate 42, which therefore responds to the combination 001 of 19 bits, which is shown in FIG. 2 A, 16 4-bit in the 1st to 3rd binary level 34. The NAND gate is divided into groups that are labeled A 1 to A 16. 42 outputs a no-off-one important property of the M-bit sequence in FIG. 2 A output signal only in this combination. If the NAND gate 42 is one that each successive bit of the sequence emits a 60 no output signal, a gate 44 results in a new 4-bit sub-sequence forms as an address. In Fig. 2A and a gate 46 a yes output signal of the 4th bi is in an address window 30 with 4 bits, the primary stage on the input of the 1st binary stage 34 to address A 1 highlighted. For every combination of M-Bitfolee that is different from 001 by 1 bit to the right, the NAND gate in the 1st to 3rd binary level 34 outputs a 65 42 output signal on the far left of the address window 30, and a gate 48 and "1" bit and defines the different address, the gate lead 46 to the input of the 1st binary stage A 2 correspond Danrt 16 Adressenbitperioden in 34 em complement of the output of the 4th Bieinem cycle shown in Fig. 2A M-bit närstufe 34 to.

SS ^{for sync} " ^{ng from 10}

corresponding to an adjacent clock bit 1 and two subsequent

t? ίΓ! Network shown with 4-stage two clock bits 1 follow one after the other. To the punk fofgeogak it is ⁸ nu7 line lisfübrungsform. Longer ta.pl p2 p3 and p4 occur so that foils can be defined according to the same algorithm as described above for the address bits and lines (d) and (β) and with a largely equidistant transition of the signal level to ßten todd aT Binary stages of the shift register During address bit 1, before transitions become Sf. In FIG. 2C, another A-- of the signal level at points p \ and ρ2 of m of the sequence logic is shown, which starts with ON to OFF and from points _P 3 and p4 ™ of the shift register cyclically a sequence from OFF to ON. For the other case, the AdresiSTSnirSK-nSdeB sends send. . senbits 0 run the transitions of the ■ S ^ eg Fig. 2C also shows a simple network of one at points ρ 1 and ρ2 from OFF to EN SführS for the exceptions of the sequence and at points p3 and p4 from ON to OFF. wik ™ exceptions are due to the return of the line (J) of Fig. 3 shows an image of a curve-comDlementary output signal of the 6th binary level form with a double level, that of the bit sequence as Sm ^P BngSgTerY. EUnäStufc defined. Is shown from the in _"5 by the curve shape of the line (α) Fie 2 Ceezeieten state table is ersichtiich that corresponds to, but according to the format of the dfc techffite ^ shown exceptions for the feed into the line (d) and (e) reproduced addresses rnH ^ 11 22 27 29 33 43 48 60 62 and 63 pre-bits modulated. The curve shape of the line (/) represents gShensmd. Since the address signal corresponding to the exceptions is that the address generator outputs to the transmission channel 12 in pairs with redundancy in the 6th binary 30 20 from FIG. 2tt? D £ ScSeregSSrs, only the As will be shown, the curve shape of the line IS Ld h Ie states 00001 X, 00010 AT, (J) has the property that both the information about 11011V doi'lOA'and OIOOIA- , through the return data bits as well as through the synchronization of the log *. Since this group has further re-address bits due to each of the transmission redundancies, it can be reduced to three stations 10 connected to the channel 12

0 * 001 * 00 * 10 * 'and 11011 *. The realizing line (J) derivable clock synchronization signal. lichune this sequence is in the block diagram of Fig. The clock synchronization signal of the Zeilt (g) corresponds 7 C dareestellt With the aid of the above-described speaks an output signal of a monostable surrounded AlEorithmus can be, for each value N full- 40 multivibrator whose Yes level a unstable zu-SLesequenceT with a corresponding logic and its no-level a stable ■ VY hen. State represents. The monostable multivibrator

¹ Tu 3 explains the signal format used. This is found in the unstable state during a 7e \\ e (a \ of FIG. 3 shows a stretched section of a slightly shorter period of time than a clock bit penode 1,. From Lr curve shape in Fig. 2 A for the address _{bit 45 denotes MK 1} die Duration in which the monofolae The section corresponds to a combination of stable multivibrator in the unstable state, 10? On three bits ^so & ^{h 2/3 T <<M} Yy < ^T <· ^The monostable multi-

As will be shown below, an address vibrator switches the transmission channel 12 to its stable state bit "1" as a double falling transition of the address signal of line (1) neeelsienal / ^, the suitably arranged over 50 in its unstable condition.

has eanse of the signal level. One Address Bit From the above it can be seen that the

"0" is synchronized by another double-level signal such as clock synchronization signal of line (g) of which the also suitably arranged over- to the address signal of the line (/) runs and entih The illustration shows the pulse edges 60 of the equally spaced

are in lines (d) and (e) of Fig. 3 dar senbitsequence of the address signal in its unst

Provides over the lines (d) and (e) shows a line status switches the clock synchronization signal

(h \ rin 'clock signal that switches a recurring signal in line (g), represented by pulse edges

has pattern as clock bit "1". The clock signal of 62, shortly before the end of each clock bit period T ₁ , m

Zefle (ti) shows equally spaced impulses. The 60 returned to a stable state. Everyone else between

The distance between the leading edges of each pulse is the transitions of points ρ 1, ρ2, ρ3 and p4 des

airTaktbitoeriode of duration Γ designated. TeU address signal of the line (/) is ignored because the

aL-iinittees within each clock period T ₁ are themselves with the output signal of the monostable multivibrator

aosenmue luu _{already attached to the p} j of _{the unstable} state), IA, I ^ DcZCItIUiCi.

Never line ic) of Fig. 3 shows another clock 65 finds.

siimal with a repeating clock bit The solid line of line (g) from Fig.

"0" designated pulse pattern. The clock bits "0" show that the clock synchromesh is already synchronized.

una Vu ύΖ ! complementary. The clock signals of the rungssignal. The dashed waveform in line (g)

11 * 12

shows the manner in which the clock synchronization transmission channel 12 is transmitted. Ei signal is synchronized. The clock synchronization should in particular be reminded that the alarm signal should z. B. at a transition 64 equally-secured equally spaced signal level transitions in time with a 5 ρ 3 and ρ 4 each occurring between the equally spaced address signals of the line (/) at points ρ 1, ρ 1. Transitions at points ρ 3 and ρ 4 Address bit period occur. Enttransition of the address signal in the unstable according to the character of the supplied data bit! switch stand. The dashed clock is the address signal during a partial synchronization signal then remains unsynchronized for several bit periods between successive cycles, but is either on an ETN or pulse edge 66 during the first subsequent io an OFF level at a safe transition . In the following z. B. the inter-clock bit period is synchronized again, in which no vall between the secured transitions of the points transition of the address signal between equidistant ρ 3 and ρ 4 during each address bit period of the transitions at the points pl, ρ 2, ρ 3 and address signal are considered . A-ρ 4 should also occur. Line (J) shows that each time it is emphasized that every transition occurring in this interval address bit period between points ρ 2 and 15 does not affect the transition of the address signal in lines ρ3 and (g) and (/) Derivation shown in FIG. 3 that for this reason the clock synchronization clock and address synchronization signal out signal of line (g) always acts with an address bit. It follows that the interval between the period synchronizes. If the waveform has data secured transitions of the signal level, ie ρ 3 and added, it can take longer than an address period to be used to reproduce data until synchronization is achieved. can.

From the above it can be seen that the line (J) shows an example of a data signal,

Clock synchronization signal of line (g) in FIG. 3 which are fed to the transmission channel 12

can be derived from the address signal of the line (/). Using the data signal of the line (/) should be

Using lines (A) and (1), it should now be shown how the address signal of line (/) is

how the address bit synchronization is achieved reproduction of the data signal is changed. There"

can be. The curve shape of line (A) results in the data signal of line Q) is partially drawn out

if the address signal of the line (/) with the line and partially shown as a dashed line

Pulses of the clock synchronization signal of the line Only the solid parts of the waveform in line

(g) is read into a delaying flip-flop. 3 ° (/) change the address signal of the line (/). Al

The resulting output signal waveform of the Example line is intended to transfer the data to transmission channel 12

(A) of the flip-flop is fed to the level one word 1001 in each case. The transfer

because the address signal shortly before it occurs, a data channel can be generated during each clock bit period.

each leading pulse edge 62 has. In the same bit can be fed, and accordingly be

Way in which the clock synchronization signal of the line 35 the transmission channel 12 during a single

(g) has been formed, the waveform of the address bit period line can be supplied to four data bits. Each one

(A) to be used, an address synchronization signal part 80, 82, 84, 86, each of the data signal

formation signal (line i) . This is done above the waveform in line (j) , occur between

a second multivibrator with a duration MV “ see the secured level transitions to the point

its unstable condition. Each transition within 40 tenpl, ρ2, ρ3 and ρ4 in the address signal of the row

half of the curve shape of line (A) brings up the two- (J) . As long as these secured level transitions in

th multivibrator in its unstable state. The address signal cannot be changed, a

Duration MF ₂ is ^3/4 T _a <CMV ₂ <. T ₀ . The station connected to the transmission channel 12

The output signal of the second multivibrator switches the clock and address synchronization information

half, as in line (/) of FIG. 3 is shown at a 45 mation as shown in lines (/) and (i)

Pulse edge 70 to a level for which is unstable, decrease. The waveform of the signal of the row

State and shortly before the end of the period T ₃ (j) can therefore be used to set the addresses

an address bit period in the stable state signal of the line (/) to change and a mixed «

(Pulse edge 72). Generated at the next transition in the address and data signal of row (Jc)

Waveform in line (h) switches the address bit 50 The mixed address and data signal becomes the

synchronization signal fed back to the level of the transmission channel 12. The curve shape

unstable state. The pulse edges 70 of the mixed address and data signal de

Address bit synchronization signal of line (/) line (k) follows the address signal of line (J) bi:

correspond in time in each successive to the parts of each clock bit period which are in line (j

Address bit period of pulse edge 62 of clock 55 are shown by solid lines. These

synchronization signal. Parts lie between the secured transitions

Using the lines α to 1 of Fig. 3, bis-pi, ρ2, ρ3 and ρ4, and here it follows that «

here only describes how address bits in a double address and data signal of line (k) the data

level signal format (line f) and how the signal of the line (/). the time bit synchronization (line g) and the address 60 The line (/) of FIG. 3 shows a clock synchronization

senbitsynchronisierung (line i) from the addressing signal which corresponds to that of the line (g)

bit signal which is supplied to the transmission channel 12 speaks. This clock synchronization signal is au

can be obtained. So far, the mixed address and data signal has not yet been de

explains how the data is sent to the transmission channel to-line (k) in the same way as the clock

be guided. 65 synchronization signal of line (g) from Adres

It can be derived from the following curve signal of the line (/). On similar

forms in FIG. As shown in Fig. 3, one data bit per way becomes a waveform of line (m) durc

Clock bit period (four per address bit period) via a gate circuit from the waveforms in de

13th

Lines (Jk) and (/) shown signals derived from the waveforms in lines (α) and (c). Tuesday

The derivation of the curve form in line (i) corresponds to the curve form in line (e) of FIG. 4A

the derivation of the curve shape in line (A) from the then from an »Exclusive-OR« link de

Waveforms of the signals ff) and (g). The address waveforms in lines (b) and (d). When di

The synchronization signal of line (f) can be the same from the 5 signal levels of lines (b) and (d)

Signal of line (m) can be derived in exactly the same way as the curve form of line (d) has an ON level;

the signal of line (i) from the signal of line (A) if the levels of lines (b) and (d) differed

was formed. are borrowed, the curve shape of line (e) has one of the following:

As described above, the address is OFF level. The curve form of line (e) in Fi§

Generator 20 from Fig. 1, the transmission channel 12 io 4A is with that shown in line (f) of Fig. 3:

address bits continuously. Each newly generated curve form of the address signal is identical.

Address bit defines a different address. Fig. 4B shows a block diagram of a simple one

with four bits. During each address bit period, generate the address signal of line (<?) Of Fig. 4A

a different station 10 is addressed. The genden apparatus The apparatus assigns the follow log

addressed station immediately recognizes its address and 15 from FIG. 2B and an oscillator 100. To your

responds to it, d. H. it takes while the post-oscillator 100 is a 3: 1 reduction circuit 10 <

following address bit period, either data is connected, which is that in line (b) of Fig. 4A

the transmission channel 12 or outputs data to the clock signal provided. A 4: 1 scale

the transmission channel 12 from. Circuit 102 counts these clock pulses and outputs the data

the transmission channel 12 during the special on the other hand shift pulses to the subsequent logic 32 from. Dii

Part of each clock bit period are fed or sequential logic 32 therefore gives each four through the

from the transmission channel 12 are received oscillator TOO generated clock pulses an addresses

the. The special part of each clock bit corresponds to the bit.

Solid line parts of the curve shape in line The output signal of the 4: 1 reduction switch (J). As will be shown in more detail below, circuit 102 is also an input of each station 10 according to the clock synchronization information shown in line (0st »exclusive OR circuit 110 supplied, which is an output of the sequential logic circuit 32 with which it is entrained from the signal of the transmission channel 12 from the input of the "exclusive OR" circuit 110, three in lines (o), (p) and (q) of FIG. 3 bound, which are therefore connected to an output terminal di: The clock pulse signals of lines (o), (p) and (q) shown in line (d) of FIG. 4A correspond to each other ₀ , r _t and r., In line (b) of Fig. 3 circuit 110 is connected to an input of a second designated subsection of the clock bit penode. "Exclusive-OR" circuit 112. One of the pulses of the clock pulse signal of line {q) corresponding to the second input of the second »Exclusive-OR« - speak the sub-section i _{2 of} the clock bit period and circuit 112 is supplied with the output signal of the "*: 1 occurring between secured pulse transitions pl, reduction circuit 106". The second ' p2, p3 and ρ4 on. They denote those time "exclusive-OR" circuits 112 out there; points at which data can be fed to the transmission channel 12 in line (e) of Fig. 4A shown address signals or removed from it. The output of the second "Exclusive OR" can be. 40 circuit 112 is of course with Jem transmission

FIGS. 4A and 4B together show the arc channel 12 of FIG. 1 connected,

beitsweise and the logical structure of the address F i g. 5 shows the basic modem as part of each ai

generator 20 from FIG. 1. The individual shown in FIG. 4B connected to the transmission channel 12

Briefly said, the task of the apparatus is to control the starting station 10. The in F i g. 5 apparatus shown

The signal of the sequential logic shown in FIG. 2B into the 45 can be used both as a transmitter and as a receiver

Format of the address shown in line (/) of FIG. 3. When operating as a transmitter, station 1

to convert sensignals. The line (σ) of FIG. 4A sends data to the transmission channel 12 when it is ih

corresponds to line (a) of FIG. 3 and outputs an address signal. When operating as a recipient

The station 10 can part of the output by the sequential logic in FIG. 2B when its address occurs

named output waveform again. The line (s) of 50 in the transmission channel 12 four data bits from the

FIG. 4A is identical to line (f) of FIG. 3, recording transmission channel 12. In an out-

and provides the guided system supplied to the transmission channel 12, some stations 10 nu

Address signal. The lines fb), (c) and (d) the transmitter and some stations 10 only receivers

Fig. 4A show in the apparatus of Fig. 4B. It can be seen that advantageous, either for Sen

trending signal waveforms that implement the manner 55 or suitable for receiving

explain in which the signal of line (a) in the for- ming for both operating modes essentially dii

mat of line (s) is converted. need the same components. As before

In particular, if the signal waveform has been described above, the address genes may correspond

Line (b) of FIG. 4A corresponds to that in line (b) of FIG. 3 rator 20 of FIG. 1 at each point of the transmission

clock signal shown. The signal waveform of the 60 supply channel 12 can be connected and still mi

Line (c) of FIG. 4A can be replaced by a 4: 1 sub-any of the described individually located sta

setter circuit from the clock signal of line (b) functions 10 be physically combined. Two or more

are formed. The curve shape of line (c) indicates addressable stations 10 can be connected to a single

therefore space along the transmission channel 12 body during one half of the address bit period

an ON level and 65 during the other half. The term station 10 was used

of the address bit period to an OFF level. Which is why here primarily to denote a

Curve shape of line (d) results from a simple addressable quantity used. Two or more

Way from an "exclusive OR" link converter, e.g. B. to display temperature un

S.

IU

15 16

Pressure, can physically at the same place input terminal of a ^ bit shift register 174 to.

The ^ -bit shift register 174 determines that in the

Bit addresses are identifiable Explanation of Fig. 2 A mentioned address

Each individually located station 10 has a window 30.

more 150 having its input connected to the transmission 5 particular occurs each positive pulse edge which is integrally schlossn supply channel 12. The amplifier 150 waveform (s) simultaneously with the transition in there as an output the in line (Jfc) of Fig. 3 ρ3 in each Adressenbitperiode on. As already shown, mixed address and data signal. The level of the mixed address shows this output signal is fed to a sampler 152 for and data signal (line [k] of FIG. 3) shortly before positive pulse edges and to a sampler 154 for the transition at ρ 3, the state of the address-negative pulse edges. The scanner 152 bits. As can be seen from lines (d) and (e) of FIG. 3 for positive pulse edges and the scanner 154 for, the signal is in the OFF state, negative pulse edges indicate output if the address bit is pulses shortly before the transition an OR gate 156. An output at ρ 3 is "1" and an ON state of the OR gate 156 is connected to an input of a 15 when the address bit is "0" at each through the first monostable multivibrator 158. Sampler 172 for positive pulse edges scanned The first monostable multivibrator 158 is when positive pulse edge of the curve shape (n) becomes unstable for a period of time MV _1. Here, the new address bit applies in the first stage of the 4-bit * / s T _t <MF ₁ < T _t . The first mono shift register 174 is read. The remaining stable multivibrator 158 in its stable state, ao bits in the ^ bit shift register 174, are shifted one step to the right by each switching it off from the OR gate 156. As in the given impulse in its unstable state. As was explained in connection with FIG. 2, every connection with line (g) of FIG Stages of the first monostable multivibrator 158 after a 25 ^ bit shift register 174 are connected in parallel to a certain number of clock bit periods T _t synchronous decoding circuit 176. The decoder with the in each address bit period of the signal in the circuit 176 of each station responds to a specially defined transmission channel 12 of the same secured 4-bit pattern and, if it occurs in 4-bit-spaced transitions at ρ I, pi, ρ 3 and ρ 4th shift register 174 scans, an address identifier The first monostable multivibrator 158 outputs the control signal to a line 178 from. As half of an output signal that corresponds to that in line (0, which will be explained in more detail below, the clock synchronization signal shown in FIG. 3 uses the address identification control signal

The output signal of the first monostable multi-address bit period is either 4 bits from the over-

tivibrators 158 will include a scanner 160 for negative 35 transmission channel 12 (receiver) or

Pulse edges supplied. The sampler 160 for nega- tively 4 data bits to the transmission channel 12

tive pulse edges in turn indicate clock pulses (transmitter),

a flip-flop circuit 162 from. The part of the apparatus just described in FIG. 5

The mixed address and data signal which is used for scanning successively in line (k) of FIG. 3 becomes an input terminal of the 40 transmission channel 12 of defined addresses. The remainder of the flip-flop circuit 162 is supplied. The flip-flop apparatus shown in Fig. 5 begins to work, circuit 162 therefore gives the in line (m) the F i g as soon as the address of station 10 has been scanned. 3 output signal shown. This output and the address identification control signal on the output signal is, as already mentioned, a double-level line 178 appears. The remaining part in signal with a single signal level transition in 45 F i g. 5 has a phase-locked loop circuit of each address bit period, which begins with the transition with a phase detector 184, a multivibrator 186 which is combined with voltage at ρ 3 of the signal in transmission channel 12 and a 3: 1 submenu. If the address bit is "1", then the offset circuit 188 on.

the transition from ETN shown in line (m) runs The phase detector 184 takes an input

after OFF. If the address bit appears as "0", the 50 output terminal of the first monostable multi-

this is how the transition of the signal in line (m) vibrator 158 takes place.

from OFF to ON. signal on. An output of phase detector 184 is

The flip-flop circuit 162 is an output with the voltage-controlled multivibrator 186 versignal to inputs each of a sampling circuit 164 and bound. The voltage-controlled Multivibra-166 for positive or negative pulse edges. The voltage amplitude supplied to gate 186 determines the scanners 164 and 166 for positive and negative Im- pulse rates emitted at its output. The 3: 1 pulse edges give output signals to an OR reduction circuit 188 which counts from the voltage gate 168. The output signal of the OR-gate controlled multivibrator 186 emitted pulses ters 168 is fed to an input of a second mono and is in turn supplied for three from the voltage-stable multivibrator 170, the selected 6c controlled multivibrator 186 delivered pulses rend a duration of MV ₂ in one unstable to an output pulse on a line 190 from. The stand is located. Here, '/ 4 T _a < MV ₂ <T ₀ applies. The phase detector 184 compares the phase of the second monostable multivibrator 170, therefore, the line 190 and, from the first monostable, output signal that is in line (s) of FIG. 3 pulses supplied to the multivibrator and emits an address bit synchronization signal as shown. A 65 voltage signal that corresponds to a difference between the phaser samplers 172 for positive pulse edges that is sampled. The positive pulse edges of the address bit synchronizing voltage signal generated in the phase detector 184 are transmitted as an error signal in the essential sizing signal and lead them to a shift to change the frequency of the voltage

17th

a t oinaantfsklemmen each stage of the 4-bit Datenregi-

controlled multivibrator 186 used on ^mg job is connected. The state of the last Grand of the closed loop of the loop sters 4_B _it _Datenregisters 200 will synchronize the over circuit, the on line f ^lu T, _"channel χι fed via a gate 216, the 190 output pulses with the pulses of the ER- ^^ fl ^ r _b ^ transmitter mono tabuen by the simultaneous Aufsten multivibrator 158. the curve S in _"Dassen the address identification controlling shape of the contact in Fig. 5 output on line 190 uc ν -τ / ajrtüBpuise is controlled, which is to synchronized pulses . in ZeUe (o) of 3 ^{s lgn} ^ ,. _mme 194 of the 3: l. coaster circuit shown, the 3: 1-coaster circuit 188 is the terminal iy "u ^ ^ _p ^ ^ ™" is also still in the lines . (p) and (q) occur aiii of 188 _u j _passing Xaktimpulse the Lnpulse shown the Figure 3 from addition here- 10 g Kemme _{heSaaaoaL is ώε Adre; se} from _a ersichthch that the pulses: der_m the Zede fa) ^ SeUaTstation 10 identifies and operates the d displayed curve shape at the same time with the Tedg ™ -]. _Transmitter so they are during aufeinabschnitten length of each clock period (s. ZeUe [b] of the station 10 as Nasr ^ "g ™ FIG. 3) occur. During this TeUabschnitts other following ^^^^ Janal U from S jedfr Takibitperiode can however Daxcnbits the x _5,216 bits aa ^ ⁰ ^ ^g ^ Setoder Zeüe transmission channel 12 fed or taken out of it off Jatenbitmter ^ ejmd au ^ _ ^ ^^^ _W will. The an aer η g. -> «· 5 p _mn fs _ni rer will those of a terminal 194 of the 3: 1 reduction ^{circuit n} " ^{m A rßlten} ^ ⁸ receivers will be

recordable and in line (q) of FIG. 3 dar- tragungsKamu ι * _P ; " _w ip"f> n nnri

provided pulses a 4-bit data register 200. «the 4-B.t-DatenregiseiJOO ^ emgeksen and continuously

It has already been stated that the but ⁰ ^ JJL ^ JJS ^ ™ and can be used in Fig. 5 nuierhch right S ^"ch ° ^ben · .The 4 BitBatenals example depicted apparatus both as a transmitter register 200 as a receiver. If the then keyed when the address identification apparatus is operated as a transmitter, each control signal of the special station 10 ^ - Ins; 4 data bits in parallel (each via a gate 202) into the "5 special .st the output of the amplifier 150 is read in with 4-bit data register 200 and then connected through an input of a gate 218, the serial shifting at suitable times to the during operation delivered as ^Em P [™ & ^r J * ^ l ™ ^e £ j "l · ^Em transmission channel 12. Ap operates the output of the gate 218 is nut EMEM Dateneuigang ready in Fig. 5 on the other hand ⁸ as a receiver, so the first stage of the advertising 4-bit Since enregisters connected 200 4 data bits from the transmission channel 12 off 3 <> to. Taken as ^ P ^ J ^ ^X ™ t? T ~ at Betneb and read serially into the 4-bit Dalenregister 200 and delay circuit 220 ^ / ^ J ^ S ^ -. You can then use the gate ken via the OR gate 214 Sch ^ betaktirnpulse 204 parallel from the 4-bit data register 200 read at the Schiebeemgange of the 4-bit data register 200 _who de _n ^e The sample and Verzogerungskreis 220 spncht on

First of all, the operation as a transmitter should be described more precisely at terminal 194 of the 3: 1 subdivision. The stages of the 4-bit data circuit 188 appear ^ pulses. The signal occurring at registers 200 read via gates 202 four data signals from terminal 194 is in the crank bits which are fed to transmission channel 12 in the form of line (q) in FIG. 3 shown. Which should be. The gates 202 are corresponding to pulses of the line (?) Define data bit intervals of a 4 ° applied to the gate input terminals 206 and the sample and delay circuit 220 outputs clock signal and the at the same time to the gate input shift clock pulses which occur somewhat within an address identification data bit interval applied to terminals 208 as soon as it is certain that the control signal is controlled. The clock signal supplied to the gate input data bit of the transmission channel 12 at the input of the terminals 206 is available in a gate 218. In a 4-bit data word, the sampling and delay circuit 210 for positive pulses is generated in parallel from the 4-bit data register 200 via the pulse edges and is shown in line (r) of FIG. 3 gates 204 read out. The gates 204 are shown at. The sampling and delay circuit 210, operating as a receiver through the clock signal of the above, responds to the output signal of the second mono-mentioned sampling and delay circuit 210 and stable multivibrator 170, which is shown in the curve - the address identification form of the line (s) of FIG. 3 is reproduced. The 5o control signal from the decoder circuit 176 ge-sampling and delay circuit 210 gives in the end controls. The stages of the 4-bit data register 200 of the clock bit synchronization pulse (line [/]) are sampled at the same time as the clock pulses (line [r]) at its output in line (r) of FIG. 3, the unillustrated pulses, indirectly on the positive edge of the curve, taking the above into account, should follow in line (s). When the gates 702 55 are controlled, the operation of the described arrangement can now be identified by the simultaneous occurrence of the address. Although the verification control signal shown in FIG. 5 and the clock pulse from the basic modem are typical for the arrangement line (/ ·) described, four data bits are read in parallel into the basic modem used in 4-bit connections, ver data register 200 is read. These bits will serve some useful deviations to be lifted out of the 3: 1 divider circuit 6o on each successive one. Although the illustrated base circle 188 via the line 190 emitted pulse modem either as a transmitter or as a receiver to shifted one step to the right. When the line is operated, it is in some cases particularly still desirable with an input of an application to connect the transmitter and receiver-sampler 212 for negative pulse edges to operate as separate units. In addition, it is switched on when operating as a transmitter. The 65 sends (or receives) the output of the sampling and delay circuit 210 basic modem shown in FIG again to shifting address cycle. In some cases it is desirable

It is worth seeing to assign more than one address to a specific station 10. If a particular station y>Z3'klus during each of the address generator 20 to send chi bits, Hann this station must be assigned to two specific addresses. This can be realized in a simple manner, there is provided indan a second decoding circuit responsive to the contents of the ^ bit shift register 174 anrieht upon the occurrence of the second address in the transmission channel 12 _m d a AdressenidentiSzierungs control signal: however, emits Instead each particular individually located station 10 To assign a separate decoding circuit for each of the multiple addresses, a nJnimal component outlay is achieved if, as shown in FIG If five addresses are assigned to certain individually read station 10, then advantageously five consecutive addresses of the in FIG. 2 sequence of the address generator 20 is selected. After decoder circuit 176 detects the first address, station 10 continues to operate during each of its assigned address bit periods.

The data transmission system described above enables efficient transmission of addressed data Data between scattered stations 10 connected to a normal transmission channel 12 are. The roles of the address and data bits are interchangeable. Also can the number of states per address bit period can be increased. Weiterbin can be similar, but somewhat different techniques can be used to mix up the data bits in the address signal. Of the described arrangement can easily be assigned to facilities that selectively determined Suppress V5 addresses within an address sequence, to force an address in any cycle. In this way, the system works with follow-up access or with direct access. Finally, it should be emphasized that the term transfer ao system in this context is general and both real-time transmission systems as well Includes systems that store the information for transmission at a later time, wk ζ. Β Magnetic tape storage units.

In addition 6 sheets of drawings

Claims (10)

Claims; 1. Arrangement for addressed transmission digital data between stations via a transmission channel connected to the stations, with an address generator that successively designates the stations, one at a time Sequence of address bits comprising address signals generated and sent to the transmission channel outputs, with an address register storing the sequence of address bits of the address signals in each of the stations and with a decoder circuit in each of the stations pointing to a responds to a certain sequence of address bits stored in the address register and the station at Enables acquisition of the specific sequence by a control signal for the transmission of digital data, characterized in that a) the address generator (20; Fig. 4B) corresponding to the equally spaced address bits generated in succession in a generator circuit (32) generates address signals which in each address bit period (7 " ₀ ) a set of equally spaced transitions * ⁵ (Pl, P 2, P 3, P 4) between first and second signal levels, by which a set of data bit periods (T ₁ ) provided for the transmission of data bits is defined, with a first group of transitions (Pl, P 2) in each set from the first transitions to the second signal level when the address bit is "1" and transitions from the second to the first signal level when the address bit is "0" and with a second group of transitions (P 3, P 4) in each set of the second changes to the first signal level when the address bit is equal to "1" and changes from the first to the second signal level when the address bit is equal to "0", b) that a scanning device (152 b's 158) is provided in each station (10), which detects each equally spaced transition (Pl. P 2, P 3, P 4) to determine the data bit periods (T ₁ ), c) that in each station (10) a further scanning device (160 to 170) is provided which and detects a particular transition (P 3) in each set of the equally spaced transitions (P1, P 2, P 3, P 4) d) that a control device (172) is provided in each station (10), which upon detection of the special transition (P 3) the signal level of the address signal as an address bit the address register (174). 2. Arrangement according to claim 1, characterized in that the plurality of data bits of a data signal can each be emitted to the transmission channel during a single data bit period (T ₁ ). 3. Arrangement according to one of claims 1 and 2, characterized in that in at least one station (10) a device (200, 216) for modulating the address signal with at least one data bit of a data signal comprising a plurality of data bits during part of each data bit period (T _f ) is provided, the data bit periods (T _t ) being defined by successive, equally spaced transitions (PX, P2, P3, P4). 4. Arrangement according to claim 3, characterized in that at least one station (10) a data register (200) in which the plurality of data bits of the data signal can be stored is that a data clock circuit (184 to 188) corresponding to that of the sampling circuit (152 to 158) detected equally spaced transitions (Pl, P 2, P 3, P 4) between successive, equally spaced transitions (Pl, P2, P3, P4) generates a data clock signal, and that to the control signal responsive gate circuits (216) when the data clock signal occurs bring the address signal to a level determined by the state of each other data bits stored in the data register (200) is determined. 5. Arrangement according to one of claims 1 to 4, characterized in that a separating device (184 to 188; 200, 204) is provided in at least one station (10) which generates data clock signals for displaying data bit periods (T,) and the level of the address signal for separating data bit information is sampled at times which are determined by the data clock signals. 6. Arrangement according to claim 5, characterized in that at least one station (10) a data register (200) in which the plurality of data bits of the data signal can be stored is that a data clock circuit (184 to 188) corresponding to that of the sampling circuit (152 to 158) detected equally spaced transitions (Pl, P 2, P 3, P 4) between successive ones equally spaced transitions (P 1, P 2, P 3, P 4) generated the data clock signal and that on gate circuits (202) responding to the control signal of the decoding circuit (176) when they occur of the data clock signal supply the address signal to the data register (200). 7. Arrangement according to one of the above claims, characterized in that the scanning device (152 to 158) edge scanners (152, 154) which scan every transition in the address signal, and a monostable multivibrator (158) which is activated at each transition in Address signal switches to its non-stable state and in this only slightly shorter than that The time between two equally spaced transitions (Pl, P 2, P 3, P 4) remains. 8. Arrangement according to one of the preceding claims, characterized in that the further scanning device (160 to 170) responsive to the occurrence of the special transition (P 3) upon occurrence of equally spaced transitions (Pl, P 2, P 3, P 4) on the Responds to the level of the address signal and has a further monostable multivibrator (162) which switches to its unstable state when there is a change in the level of the address signal between the occurrence of successive equally spaced transitions and remains _{in this only slightly shorter than an address bit period (T n)} 9. Arrangement according to one of the preceding claims, characterized in that the Ge The generator circuit (32) periodically generates a sequence of 31 bits, the sequence not being generated again. Address bits this sequence and compares it with a sequence generated at the location, occurring only once. _{5 If} ^ _{6 received} and locally generated sequence 10. The arrangement according to a dtr preceding in a sufficient number of bits according to the claims, characterized in that the men, ie when the last 5 bits received with the address signal, a signal form with double level of an address of the individually located station has the same during a first and a second are correct, a control signal is generated that the one section of the address bh period (TJ below each station in the desired manner executes different first or second, an Xdressenbit. Since each station has a repetition pattern representing 5-bit information "1") to define its address, only one additional address bit and the one during the first and second paragraphs is required to form the address intersection of the address bit period (Tj second or a different station. New address first repetition pattern has a 15 senbits will represent address bit »0« in accordance with a slow cycle determined a sufficiently long period and thus the reservation of a special part of the Allow period for a reply message from the addressed station. The invention relates to an arrangement for addressing ao Furthermore, it is known (DT-AS 1 437 221), a The transmission of digital data between multiple stations on the same transmission line to connect via a station connected to the station in order to transfer digital data between the state transmission channel, to be able to transfer functions with an address generator. An address gene in each case also connected to the transmission line which successively designates the stations a sequence of address bits comprising 35 generator successively generates one of the Sta address signals and address signals assigned to the transmission functions. This address channel emits, with a sequence of address bits signals are earthed by the assigned stations Address registers storing address signals knows what the stations digiin for transmission each of the stations and data can be released with a decoding switch. The address signals circle in each of the stations that point to a specific 30 consist of a sequence of address bits; Sequence of addresses stored in the address register - the data signals are a sequence of data bits. To the senbits responds and the station when it detects the decision about the status of the address bits or Correct sequence by a control signal for the transfer data bits, their duration is used. extra release of digital data. long signals indicate the beginning of a data signal There are already countless different types 35 or the beginning of an address signal. Since the digital transmission arrangements or transmission information in the duration of the individual signals transmission systems for the transmission of data and synchronization is not provided, scattered stations. Most of these are prone to failure. The processing and VerSysteme however, they are complex and consequently costly to work with disturbed address bits and data bits in playful. 40 the stations is due to the lack of synchronization However, there has recently been a need for sation. simple cheap data transmission systems, which In contrast, the invention has the task of for the transmission of relatively slowly changing a trouble-free synchronization of address bits data, z. B. between a central station and down and data bits in the stations to enable
side transducers, are emsetzbar. 45 The invention solves this problem on the basis of, for example, in a process control system that of the arrangement explained in more detail at the outset, by periodic transmission of measured values of a multitude
number of individually located converters to the central station may be necessary. In order to keep the costs as low as possible a) the address generator corresponding to the in, a time-multiplexing 50 a generator circuit successive evplex transmission via a normal transmission-generated, equally spaced address bits channel in order to generate the receive signals in this way, which are in each address bit A set of equally spaced superimposed data in the central station for a specific period assigned converter. In steps between the first and second signal levels In other systems, one would also like to have data in such a way that one record for overriding, that it is a data bit provided by the central station to any data bit special, d. H. "Addressed" individually located periods is specified, with a first Station are transmitted to z. B. a set group of transitions in each set of change the setpoint. In more general cases the first goes over to the second signal level, In some applications it is important that the system 60 if the address bit is equal to "1" and from the a two-way transmission of addressed data goes over to the first signal level, see any two stations in the system if the address bit is "0" and where light. a second set of transitions in each U.S. Patent 3,445,815 describes a system, set from the second to the first signal level that ignores the monitoring and control of a multitude 65 when the address bit is "1" individually located stations from a central station and from the first to the second signal level fitted. The system described there is ignored if the address bit is "0", det an address generator that generates a sequence of b) that a scanning device is present in each station.