DE2165923A1 - Computing system - Google Patents

Description

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Texas Instruments Incorporated

135oo North Central Expressway

Dallas, Texas, U.S.A.

Computing system

The invention relates to a computing system for processing functions, each with a plurality of elements. Particularly concerned the invention relates to computing systems for processing vector streams with an ordered array of elements.

The invention was based on the object of an improved computing system of this type to propose which is especially suitable for carrying out vector operations.

According to the invention, this object is achieved by a computing system

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System of the type described above solved, which is characterized by <?; «that receiving devices for the radio. are provided that empower individual elements one after the other and that with the receiving devices there are devices for measuring changes in the gradient of the functic-r- o'r- vert-under.

In a further development of the invention, a computing system> z. Processing of vector streams, each of which is a georväe ;. Field of elements includes, proven to be favorable »which ά *. is carried in that Empfangseinrichtu ■ ..- ^ nf ^r "of the current vector are provided, each having a El rnt c ^r;. V-- are 'received torstromes after the other, and that adjustin * ingT provided in; Determine the peaks in the vector current as a function of the fear of dripping .. ^ directions.

The advantage of such a new and improved ry is that it is suitable for detecting changes in the slope of vector currents, and especially positive ones Determine (peaks) and negative (valleys) maxima of vector currents.

The basics of vector calculation will now be explained to the extent that this is done in connection with the of the present invention.

A vector X is an ordered array of elements (χ, χ, x, * .., χ, »). The variable x. will the i. Element di Vector called X, and the number of elements, which as

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bath

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ν (χ) is given (or simply as v, namely when the associated vector is clear from the accompanying text), the dimension of the vector is called X. A numerical vector X can be multiplied by a numerical quantity k to obtain the product of the scalar and the vector, namely k * X (or kX), this product being a vector Z whose elements have the following relationship :
Z ₁ = k * X ₁

All elementary operations defined for individual variables are, are consequently extended for the vector calculation in such a way that these operations are applied to the individual elements can be applied. For example:

, 111

Z = XXY ^ - * - »· ¹ Z ₁ = X ₁ XY ₁ , \

Z = X * Y <- * Z ₁ = X ₁ * y _{± i} Z = IxI * ■ * ■ ζ ₄ = | χ ₄ I,

= U ₁ Λ

W = (X <Y) «-» ■

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So if X = (1,0,1,1) and Y = (0,1,1,0) then X + Y is: (1,1,2,1) and X ΛΥ = (0,0,1,0) and (X <Y) = - (0,1,0,0).

A matrix M is the ordered, two-dimensional field of Variables.

2 2 _M 2, M ₂ , · .., Γ · ' _{ν (Μ} )

v (M)

The vector

'Λ

v (M)

) becomes the vector of the i row

called the matrix M and written as M " ¹ ". The dimension ν (M) of this vector is called the row dimension of the matrix. The vector (M., M. ² ₅ , .., M.) becomes the vector of

YY J

Column of the matrix called M and written as M. The dimension of this vector u (M) becomes the column dimension of the Called the matrix.

The variable M. ¹ is called the (i, j) th element or the (i, j) th component of the matrix. Operations that are to apply to all elements of a matrix are carried out component by component for the entire matrix. So if 0 is any binary operator, then:

P = MO N

P. ¹ = 3

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Further advantages and details of the invention are explained in more detail below with reference to the drawing and / or are the subject of the claims for protection.
In the drawing show:

1 shows a computing system according to the invention for determining the Peak and valley of a vector stream or a vector track,

Fig. 2 shows a specific example of a vector current and

Fig. 3 shows two "self-loops", each of which is a vector stream or is a vector track.

The drawing also includes a table 1, which provides an explanation the chronological sequence of the operation of the computing system according to FIG. 1 is used.

The devices (hardware) and logic connections (logic) explained with reference to the drawing and shown in it are contained in the processing unit of the program-controlled computer. Input signals are sent to the system via a buffer storage unit and output signals also exit the system via the buffer storage unit. The clock pulses and the control signals come from the command control unit of the computer. The structure of such a calculator is in an earlier one Registration of the applicant (äkt.z ..., Serial No. 7U4 19o) which was filed in the USA on 7/11/6 8.

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As already stated, FIG. 1 shows the computing system according to the invention and FIG. 2 shows a vector trace with a number of peaks and valleys. Table 1 shows the timing of the Search process for a tip for a vector track according to FIG. 2 with the aid of a computing system according to FIG. 1.

In the computing system according to FIG. 1, the input signal from the buffer memory register is applied to an input terminal 19 and from there arrives at the first AB receiving register 21. The AB receiving register 21 is connected to a second CD receiving register 23 connected in cascade.

The tip search operation is used in both fixed-point representation as well as with floating point representation. The following description will now focus specifically on the mode of operation in the case of fixed-point representation, while the method of operation in floating-point representation will be discussed later should be received. The output signals from the AB receive register 21 and the CD receiving register 23 first go through the selection logic 25, in which between fixed point and Floating point representation can be selected. A fixed point representation was chosen in which the input signals from the AB receiving register 21 and the CD receiving register 2 3 are applied to the adding circuit 27. The output of the adder circuit 27 leads to an adding register 29. The sign bit in the adding register 29 is fed to an AND gate 31, whose the output signal of a zero detector circuit 37 is fed to the second input via an inverter. The zero detector circuit determines the zero between the results of the

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Subtraction of the two elements of the vector in the registers and 23. An AND circuit 33 is used to the previous old Sign (which has been stored in the sign delay flip-flop 3) via an OR circuit 35 to the sign delay flip-flop 39 attributed. The outputs of the OR circuit 3 5 and the flip-flop 39 lead to one EXCLUSIVE-OR gate St. The output of the EXCLUSIVE-OR gate 41 forms the input signal for a flip-flop 43 to Peak determination. The output signal of the EXCLUSIVE-OR gate 41 is fed to the flip-flop 43 via an AND circuit 45, which still further input signals are fed, like this should be explained in more detail. Via the input line 47 for an AND gate 49, an item counter can, if so desired switched off after the first peak. If an "O" is applied to line 47, then the search for Peaks in the vector track continue until the last element of the vector is processed and until the indices of all of them Peaks and valleys are stored in the buffer storage unit. However, if a "1" is applied to line 47, then the search process ends as soon as the first peak or valley has been determined. If there is a "1" on line 47, the index of this peak or valley point is saved. In the procedure to be described below, the An "O" is applied to line 47, so that the entire vector trace is checked. The output of the zero detection circuit 37 is also fed to a flip-flop 57, which is an introductory flip-flop. The output of a flip-flop 51 (peak picking zero flip-flop) is applied to an AND circuit 53, and the output of this AND circuit is via a

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OR circuit 55 is applied to flip-flop 57. The output signal this flip-flop 57, which initiates the peak search, is applied to the second input of the AND circuit 5 3 The output signal of the OR circuit 55 is also inverted and applied to an input of the AND circuit 45. That second input signal for the OR circuit 55 is a signal from the microprogram memory, which in the introductory Instruction microprogram is used. The output of the flip-flop 43 is with the buffer storage unit and also with connected to AND circuit 59 so that the index of the peak point is switched through to an EF output register 6 3 can. The output of flip-flop 43 is a reminder for the buffer storage unit that it is time to look at the EF output register 6 3 and determine the index of the tip found in this workflow. That The output signal from the flip-flop 43 increases the count of an accumulator 64 by 1. An accumulator 65 stores how often a peak was identified. The result of the item counting by the accumulator 6 5 can be via an AND circuit 6 7 and passed through an OR circuit 61 to the EF output register 6 3, so that the final result of the item count can be obtained from the EF output register 6 3 and placed at the beginning of the index list or the output signals which have been selected to indicate how many peaks have been selected on that particular vector track, which is currently being processed in the computing system. A signal is applied to the flip-flop 69 from the buffer storage unit, when the end of the iteration process is reached. This is an indication of a final output signal. That

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The output of the flip-flop 69 is sent to the other input the AND circuit 67 placed. Two input signals are applied to the AND circuit 71, namely a gate circuit receiver input signal (gate receiver input signal) and a data present signal, which the flip-flop 73 and indicate that data is available at this level. When working with a fixed point representation instead of a floating point representation, the flip-flops 75 and 77 are skipped. That lies in the direction of the data flow Flip-flop 79 behind flip-flops 75 and 77 in the circuit. When the flip-flop 79 is in the "1" state, this indicates that data is in the adding register 29. The alignment register 24 is a logic circuit used in floating point operations determines the mantissa of the element which has the smallest exponent. The flip-flops 75 and 77 are used in floating point operations to pass the data through the exponent subtraction unit 22 and the adjustment register 24. The output signal of the flip-flop 79 is fed to a flip-flop 81. The flip-flop 81 switches the adder circuit or the Accumulator 82 continues by 1. The index or the address of the element which is compared in the peak search process, is stored in an accumulator 83.

Consider now Fig. 2, which shows a particular vector trace, and Table 1, which shows the timing of the peak search operation for the vector trace in order to better understand the operation of the system according to FIG. Of the Time O in Table 1 corresponds to time O of the vector track in FIG. 2. In the embodiment according to FIG

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the first element of the vector track at time O has the value 3. At time O, element a (3) is stored in AB register 21. At time 1, element a _n (3) is transferred to CD register 23, and element a (3) is transferred to AB register 21 and stored there. At the time, element a (3) is stored in the CD register and element a (2) is stored in the AB register. At time 1, the contents of the CD register (element a) and the AB register 21 (element a.) Are subtracted from one another in the adder circuit 2. Since both a "and a". the value 3

O 1

the result that appears in the adding register 29 is O. The subtraction takes place during cycle time 1, and the result appears in the adding register 29 during the next cycle time, i.e. during cycle time 2. During cycle time 2, circuit 37 provides To determine the 0, the presence of the 0 in the adding register 29 is established. The determination of the 0 or the corresponding signal appears in the flip-flop 51 at clock time 3. The fact that a 0 appears in the adding register 29 has an effect on the flip-flop 51 in that it is in the state "1 "goes, during the cycle time 3, as shown in the table 1 below. If this was the beginning of an operation, no element was previously stored in the CD register and therefore no result was previously stored in the adding register, so that there was no sign in the adding register which the sign gate circuit 31 could influence. Even if a sign were available, it would not affect the output of this circuit at that point in time. It should be noted that in the event that

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that the difference between the two elements is positive or the output of the sign bit is zero. If the If the difference between the two elements in registers 21 and 23 is negative, then the sign bit is a "1".

The sign delay flip-flop 39 was previously set to "O" before starting to process a vector using the fixed circuit. So since the flip-flop 39 is on "O" is, it supplies a "0" to the AND circuit 33 and at the same time a logical "1" is also present at this point in time. from the zero detector logic 37, so that a "0" is applied to the flip-flop 39 via the AND circuit and the OR circuit 35 which thus remains in the "0" state. The sign delay flip-flop 39 therefore indicates at this point that the sign bit was "0" and that thus between the two Elements in registers 21 and 23 had a positive difference or the difference 0 was present. So the sign became not changed for the first item. This can be seen if one looks at the vector track in FIG. 2, in which the element a

0 d. So there is no change;

see these two elements.

and the element a. both are 3. Thus there is no change between

Fig. 3 shows _two loops with a "self-loop" (selfloop) 1 and a "self-loop" 2, where loop 1 is an internal loop, and when this has been passed you can go directly to the "self -Loop "2 go. Thus there is a preceding element in "self-loop" 1 which is earlier than the first element in "self-loop" 2. In Fig. 2 the last element would be an a element (2),

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which is earlier than the a element (3). Between consecutive Loops as between loop 1 and loop 2, insulation is provided, as FIG. 3 shows.

This preceding character is shown in the time table at time 1 and shows a sign of "1", which shows that the difference between the registers AB and CD is a positive 1, as shown at time 1. This difference is positive so the sign is "0" as shown at the time, and "1" is recorded in the sign delay flip-flop 39 as a "1" at time two. At time 2 the element a. to the CD register 23 and the element a ₂ (2) to the AB register 21. Thus at time 2 the AB register 21 contains the element a (2), and the CD register 23 a (3). There is a subtraction in the adder circuit 27, and at the time number 3 the difference (-1) is entered in the adder register 29. This is the first time that we have seen a change in sign, as will be shown by comparing the contents of the adding register, which is -1 at this time. It can be seen that the new sign and the old sign are applied to the EXCLUSIVE-OR circuit 41 by the sign delay flip-flop 39. The input to AND circuit 45 will be "1" indicating that a "1" has been applied to AND circuit 45 from EXCLUSIVE OR circuit 41 indicating a spike. However, this is the first peak which is a false peak in the track, and this is prevented by the signal applied from the OR circuit 55 to the AND circuit 45, with the OR circuit 55 on signal called the PPINL signal

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for the beginning of the tip search to prevent the incorrect display of the first tip. This is achieved by going to the OR circuit 55 and setting the flip-flop 57. The flip-flop 57 is held in the set state as long as how zeros are discovered; however, the flip-flop 57 is immediately reset if a difference is detected which is not zero, so that the output of the AND circuit 53 to the OR circuit 5 5 and the output of the OR circuit 55 to the AND circuit 45 no longer prevents the AND circuit 45 from displaying an indication of a detected Tip or a. to generate established valley.

During the cycle time 4, the flip-flop 39 is then set to "1", and the output from the adding register 29 to the AND circuit 31 is now a "0" which is a positive one Sign indicates, which in turn indicates that the difference between the two elements (element a and element a) is positive is such that the sign is "O". The change in sign at time 4, which is indicated by the output signal in The form of a "1" of the EXCLUSIVE-OR gate 41 was displayed, is now applied to the AND circuit 45. The AND circuit is not blocked by the output of the OR circuit 55. The input to the AND circuit 49 and their Output to AND circuit 45 can be used as a condition to help identify further peaks and troughs Prevent valleys after determining the first peak or the first valley. In other words, this means that "the AND circuit 49 can be used with the right equipment to determine only the first peak or the first valley.

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On the other hand, if the purpose of the operation is to find all the peaks and valleys and find their index addresses in memory, then one will not prevent further identification of the peaks and valleys, and the operation will last for the whole Vector track continued, for example for a vector track as shown in FIG. During further processing of the elements in the cycle of the circuit is obtained by the accumulator 83, which is incremented by 1 for each element, the index of the respectively processed element, so that at the point in time at which the flip-flop 43 is set to "1" and indicates that a peak or valley has been detected, the accumulator 83 has reached a count equal to the index or the memory address of the corresponding element, which corresponds to the fact that the flip-flop 43 is set to "1" was determined as the peak or valley.

At this point in time, the flip-flop 43 will simultaneously switch the accumulator 6 5 by 1, so that this accumulator, which operates as an item counter, the number of peaks found in the vector track shown in FIG or valleys. The output of the flip-flop 43 is also applied to the buffer memory unit so that it can store the in the EF output register 63 retrieves and stores the stored index, since this index the position of the element in the vector track indicates which peak or valley was determined.

After the processing of the vector track has ended, with the aid of a signal from the buffer memory unit to the flip-flop 69 of the Counter reading of the item counter 65 can be called up. To this

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The purpose is the output signal of the flip-flop 69 to the AND circuit 67 created, which has the consequence that the content of the accumulator 65 is transferred to the EF output register 6 3, from where the counting result is read from the buffer storage unit.

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Claims (1)

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3o.12.71 Claims TyJ computing system for processing functions with each several elements, characterized in that receiving devices are provided for the functions, one after the other receive individual elements, and that with the receiving devices devices for determining changes related in the slope of the functions. 2. Computing system according to claim 1 for processing vector streams, each of which comprises an ordered array of elements, characterized in that receiving means are provided for the vector stream, each receiving one element of the vector stream after the other, and that Devices are provided which determine the peaks in the vector current as a function of the receiving devices . 3. Computing system according to claim 2, characterized in that devices for determining valleys in the vector stream are provided. H. Computing system according to Claim 2, characterized in that devices for displaying the number of peaks determined are provided. - 17 - 209830/071 5 A 39 24o b / 15 -Vl- k-146 '' 3o.12.71 5. Computing system according to claim 3, characterized in that devices for storing the number of determined Valleys are provided. 6. Computing system according to claim 2, characterized in that means are provided for displaying the indices of the peaks which were determined in the vector current. 7. Computing system according to claim 1, for processing vector streams, each of which comprises an ordered array of elements, characterized in that receiving means are provided that receive the elements of the vector stream one after the other, that memory devices are provided are, in order to store the element preceding the respectively received element, that comparison devices are provided in order to compare the respective received element with the preceding element, that display devices are provided to be the difference between the received element and the preceding element of the vector stream and that facilities are provided which, depending on the comparison results indicate a negative difference between the elements to indicate a peak in the vector current. 8. Computing system according to claim 2, characterized in that means are provided for the index of the elements of the vector stream while they are being processed in the computing system. - 18 - 209830/0715 A 39 24o b ήθ 3o.12.71 9. Computing system according to claim 7, characterized in that devices are provided which are dependent on
the determination of a peak in the computing system switch through the corresponding index of the element at the peak. 10. Computing system according to claim 7, characterized in that Devices to suppress the display of the first ψ the middle tip of the vector track are provided. 11. Computing system according to claim 2, characterized in that devices are provided for the search process
Abort determining the first peak in the vector current. 12. Computing system according to claim 7, characterized in that devices are provided to the number of in the
Peaks determined by the vector current. 209830/0715