DE2164227C3 - Drift-free analog-digital converter - Google Patents

Description

stored voltage value by one of the »electronics«, Janrgang ivoö, new ζ una 4, each '^

Comparison circuit (3) effected connection with on pages 37 to 40 and 117 to 120 Die dor-; ™

a voltage source (+ U _b ; ~ U _b ) the desired publication is entitled »The basis;,;

Sign for the slope adjustment of the saw 35 digital voltmeter «and comes from Manfred %

tooth tension to the time interval at each Klose. This is followed by the analog-to-digital conversion i | _f

Reference voltage comparison is changeable and in such a way that the measuring voltage with a linear ~ g

that the oscillator (6) runs freely with a constant or step-like increasing reference voltage ' ^{! Π} »

Clock frequency is formed. compared and at the start of measurement em digital impulses' -

2. A transducer according to claim 1, characterized overall 30 scoring element, such as an electronic counter, Φ indicates that the ER is cranked from the integrator (1), the measured voltage in case of equality of ^r handed off voltage (U _c) by Counter end is determined with the changing reference voltage exhibition (n _max ). is read, whereby usually a comparison »

3. Converter according to claim 1 or 2, characterized in that a circuit is provided. The detection of the " ^: " indicates that a control unit (8) is provided, counting which has been entered until the voltage equals, which, by separating the integral pulse, provides a digital measure for the to-tor (1) from its feeding Analog memory measuring analog voltage value of the input

circuit (2) the integrator final voltage (U _c ) voltage IZ ₁ . However, this is disadvantageous in these gmnd- ¹ ^

j then defines when the counter (5) uses its maxi-laying method that both inaccuracies in ^£

paint count content (; j _ma J has reached. 4 ° of the generation of linearly increasing reference span ι

4. Converter according to claim 3, characterized in that, in the steepness of which, as well as frequency- '■ "»

\. indicates that the control unit (8) during changes in the oscillator as a measurement error in the measurement if

s of the measurement phase are included when the result disappears, furthermore measurement $ ■■ results

the input voltage at the comparison circuit inaccuracies, which can lead to considerable ™ errors <ψ

device (3) controlled by this by a sliding 45 can add, by drifting the used- ■ $

Pulse transmission of the counter content to a th component, amplifier, comparison circuit

Memory (7) causes. etc. and by component deviations. 'M

5. Converter according to claim 1, characterized in that in the known analog-digital converter according to ^{| H} |

indicates that the reference voltage source of the aforementioned DT-OS 2108 329 is so vorgegan- ¹ ^

the complementary outcome of the same 50 gene that the 'W

Voltage value by means of an inverting sawtooth voltage at predetermined times ^

stronger generated. with reference signals in opposite polarity ^

fv converter compared according to one or more of the approaches and a feedback circuit provided &

Proverbs 1 to 5, characterized in that Lsi, who works on the oscillator and this in his- ¹ ^

for adjusting to changes in the frequency so adjusted that sawtooth voltage Ά

Refrenzspannunpsquellc decreasing error and oscillation frequency are adjusted to each other

learn a fun or analogue value to be measured <l; ili the number of impulses in a reference / zeitintcr- '*

output voltage (U _x ) is kept at a predetermined number with the aid of the reference voltage. It

voltage source can be generated. measurement errors can be avoided in this way, ^l «

60 which indicate a change in frequency of the oscillator un- ί

depending on a change in slew rate of the sawtooth ^?

tension decrease.

It is known from this DT-OS 2108 329 (see t

The invention also relates to a drift-free S. 18), the reference time interval by Ver '5i

Analog-digital converter with a linearly steep change in the rise of the sawtooth voltage to w

The slope of the sawtooth voltage R

voltage generating sawtooth generator, one of is set so that during the interval a ·;

an oscillator originating clock pulses counting fixed number of pulses is observed.

However, the disadvantage of the known analog-to-digital converter that a pulse generator or oscillator must be used, which is voltage controlled is or the general frequency can be influenced, so that a crystal-controlled oscillator cannot be used. Thus, the oscillator in the known analog-digital converter nor does it have the freedom from tremors which is necessary to achieve a greater resolution. General it should be noted that the known analog-digital converter is extremely cumbersome and has a considerable number of independent circuits which are in turn their own Have drift behavior, so that higher accuracies cannot be achieved either.

An analog-to-digital converter is also known from DT-AS 12 90181 *, with one Sawtooth voltage generating sawtooth generator, the slope of the sawtooth signal from the a counter feeding clock pulses is made dependent in such a way that when changes the clock pulse frequency the slope of the sawtooth voltage is readjusted and you in this way maintains a fixed relationship between the slope of the sawtooth and the clock pulse frequency. Two comparison circuits are required for this; from a sampling circuit is a predetermined Group of clock pulses tapped and fed to a feedback circuit, which consists of summers, integrators and a control gate and which operates in such a way that a reference voltage source is added to the reference signal from the feedback circuit derived signal is added. The sum signal obtained then serves to act on the sawtooth generator, which sends its output signal to both comparators and an additional summing element, which is also acted upon by the reference voltage source is. This circuit is also extremely complex and can rely on drift voltages or other Failure to compensate for errors that result in component changes. It is particularly disadvantageous that two Comparator circuits are used that can drift differently.

Finally, the DT-t \ S 16 16 050 can still take a device for the automatic calibration of analog-digital converters with digital display, the calibration setting being carried out with the aid of a step-by-step electric motor which drives an adjusting device for fichening the analog converter.

The invention is based on the object of creating a digital converter that works reliably and with high accuracy without a major increase in circuitry, which by linking the clock frequency with the steepness of the sawtooth voltage eliminates the errors based on the encryption principle uii ('at the same time the essential drift ve ^r . Changes to components, tempos ι.π urgang u. Ι!) ·], Declining errors beseil i ', t

To solve this problem, the; limiting to ¹ of the initially known as voiai · s.'t / ten drill-free analog to digital converter u κΙ bes. ''Erfindii'.gsgemäß that the Sägezringciu <> · an Ar LLOG memory circuit Settings Associated ι is ι _t son of your ramp each aifinlegi ■ Mer stored voltage value by emc before ck-r test circuit caused connection r ι! a voltage source of the desired sign for adapting the slope of the sawtooth voltage to the time interval can be changed for each reference voltage comparison, and that the oscillator is designed to run freely with a constant clock frequency.

According to an advantageous embodiment, regardless of the triggering of the shift pulse, d. H. the initiated reading of the counter when there is a tie between the measuring voltage and the sawtooth voltage the integration and thus the generation of the sawtooth is terminated by a control unit at the moment when the counter is running Has reached the maximum value. This results in a link between the counter reading and the generated one Sawtooth signal, which is then compared with a fixed reference voltage in the subsequent calibration phase and, if necessary, its slope is changed for the next measurement cycle.

It is particularly advantageous in the subject matter of the application that no attempt is made in any way to the The oscillation frequency of the oscillator can therefore be used to generate the clock pulse using a crystal-controlled Oscillator are used, this also leads to a considerable circuit simplification, a complete one Tremble-free of the generated clock pulses and a larger trigger.

Another advantageous embodiment of the invention is that the analog to be measured Size, namely the input measurement voltage can be generated with the help of the reference voltage source, for example in such a way that the reference voltage source simultaneously feeds a measuring bridge is used, the output signal of which is therefore a measure of the change in the bridge resistances and the supply voltage is. In this case the measuring signal and the reference signal are necessarily in The measurement and calibration phases are the same, so that, as is easy to see, there are changes in the reference voltage source emphasize, it is therefore also not necessary in this case to stabilize the used To operate reference voltage sources an increased effort.

The advantages of the invention are therefore to be seen in particular in the fact that one has an extremely high measurement accuracy achieved without exaggerating the requirements for the frequency constancy of the oscillator must be, since after each measurement phase is forcibly calibrated and frequency changes automatically be balanced. The measuring accuracy of the analog-digital converter is reduced by drifting the Comparison circuit is not affected in any way, so zero point corrections are not required as well each measuring cycle requires the same time, regardless of polarity and level of the measuring voltage.

Further refinements of the invention are the subject matter of the subclaims and are laid down in them

In the following, the structure and mode of operation of an exemplary embodiment dt τ invention are shown on the basis of the figures explained in more detail. 1 shows the circuit of the analog digital converter in schematic representation and

2 shows the functional diagram of the changing voltages in the measuring and calibration phases as a function of the line, the states of the individual switches also being displayed in the lower part.
As can be seen from the circuit of FIG.

The input voltage U _x to be measured is sent via switch 53 to circuit point A and from there reaches the input of comparison circuit 3 via resistor R _a 1 and a reference voltage source 4 with a complementary output. The reference voltage can be applied to circuit point A via switches S1 and S2.

The output of the comparison circuit 3 controls a control unit 8, which in turn controls an up / down counter 5 and a memory 7; the up-down counter is from a clock generator 6 acted upon with Taklimpuls.

The mode of operation is as follows, with the measurement phase being discussed first. Before the start of the The sawtooth generator, namely the integrator 1, is measured by closing the switch 5 that controls it

the reference number U _c . If the counter and integrator pass through the value zero, the counting direction switch 58 in the control unit is switched from "down counter" to "advance counter" and the counter now counts up so that counter 5 and integrator 1 continue to run in parallel. If the output voltage of the integrator U _{c is then} negative equal to the unknown measurement voltage U _x (time / "), which means that the input

If the voltage U _v corresponds to the comparison circuit 3, the comparison circuit 3 then triggers a shift pulse via the control unit 8 which transfers the current counter content to the memory 7. In the memory 7 there is thus a counter reading that

corresponds to the value of the voltage to be measured U ₁ .

For the case that the voltage to be measured U _x

is negative. the pushing impulse occurs already in the Phase in which the counter 5 counted down. the

the integrator 1 has thus reached its lower extreme value, since there is no further value to be integrated More tension is available and at the same time blib d 2'h h lb

The measuring phase is thus ended, and a clear assignment of the frequency of the clock pulses to the The end of the integrator has also been reached; H ,

Infotmaiion for the polarity of the span to be measured

with a voltage source 17 ,, predetermined voltage, the position of the counting direction can be

connection, powered up until it removes its upper switch 58. She will, too, through

Has reached the stop point. This value and thus the shift pulse in a sign memory

the voltage of the voltage source 17 ,, is also taken over

higher than the voltage that is then generated by the reference voltage, however, counter 5 and intensity source 4 and continues by closing the gate, regardless of the off switch 51 or 52 to circuit point A, the shift pulse is resolved by the comparison . The up-down counter 5 is thereby circuit 3 and the takeover of the current from its maximum value n _mas , which it in the previous counter reading in the memory 7 until the counter reaches the measuring phase and the next one has reached its extreme value. Has maintained this eye calibration phase. The measuring phase itself is viewed, the counter clock is then either excluded by an external trigger signal via the control unit and the switch 54 is opened, released or automatically initiated by the control unit 8. To do this, switch S5 is opened and

switches 54 and 52 closed. This is __ ^

Once the inverted, i.e. complementary, reference value, the counter remains, as just mentioned, self-tensioning U _rc , at circuit point A and constantly reaches its maximum value, which is sent to the input of the comparison circuit via resistor R ₀ 3, on the other hand the integrator 1
Via the switch S4 with the constant voltage 40 oscillator and sawtooth generator provided by the analog memory circuit 2 in the form of the Intenung U _{c applied} to its one input and grators 1 are linked to one another, this begins to integrate in the usual way. The control unit now forcibly solves the moment at which the integrator opened at the calibration phase, for which the switch S3 geOutput C of the integrator 1 is also open and the switches S1 and S6 voltage negative, the inverted reference 45 is closed will. Opening the switch; S3 voltage and therefore the voltage at the input that takes the input measurement voltage from the circuit comparison circuit 3 and becomes zero. This voltage point A away, and by closing the switch Sl is designated in the function diagram as U _x and at this point the non-inverted reference is represented by the solid line. The voltage U _rr applied. The switch S6 (at now ° U, at the input of the comparison circuit 3) switches 54 open to 5 °, i.e. an interruption at time f, to zero. At this moment, the comparison circuit 3 switches between the analog memory circuit 2 and the control unit 8, the integrator 1 ', the analog memory circuit with clock pulses of the oscillator or clock generator 6 of a power source selectable sign, nämauf the up-down counter 5. Hch simultaneously with either -t-UB or - connected UB supply ■ svird the switch 52nd open and the switch S3.55 is next, however, at circuit point A, the reference spring, the input measurement voltage U _x with the switching voltage U _rct , and the comparison circuit 3 connects to point A, closed
the voltage at this point at time r

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voltage at switching point A is in the
The diagram of FIG. 2 is indicated by dash-dotted lines, each with a colon between the lines. Integrator 1 and counter are now running

from their extreme values backwards towards zero, where " the counter reading at any moment a measure for 65 and sends a suitable voltage pulse to the

the voltage at the integrator, d. H. for the voltage analog memory circuit, so increases its con-

at circuit point C. In the flow diagram is the constant voltage U _c or reduces this voltage,

this voltage as a dot-dash voltage with After the adjustment, the switches S1

has the opportunity to match this reference voltage with the integrator end voltage on

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^{Flux deviation of 6} ° to be determined. If a discrepancy can be determined, which is almost always the case with an appropriately designed gain of the comparison circuit 3, then the comparison voltage 3 also closes the switch 57 in any direction

and 56 reopened and switches 55 and 52 closed, i. H. the beginning is repeated cycle already described. By closing the Schaller 55, the integrator is on an upper or lower stop point, definitely driven to an extreme point and the counting direction switch put back on "backwards". This also ends the calibration phase, and the measurement phase can be repeated initiated either automatically or by triggering.

The sampling of the analog memory circuit by the integrator 1 is of course extremely high-resistance, otherwise the operating times for the switch 57 and the dimensioning of the analog memory circuit 2 are designed so that the correct voltage U _c after a few measuring

cycles and thus after the end of the measuring phase the integrator voltage U _{c is} negative equal to the reference voltage U _ref .

It can be seen that only a single comparison circuit is required for the measurement and calibration phases so that their drift behavior stands out completely.

It is also particularly advantageous that, for certain applications, the unknown to be measured analog quantity can be generated with the aid of the reference voltage source 4 already mentioned, for example, if it is used as a supply voltage for a bridge, the change in resistance is a measure for the variable to be measured, so that the measurement accuracy also depends on the behavior of the reference voltage source becomes independent.

For this purpose 2 sheets of drawings

Claims (1)

ι ² Counter, one when an input "' .., measuring voltage with the sawtooth voltage Claims: Si ° nalgabe enables the evaluation of the counter contents Ji ■ * - ^ michenden comparison circuit and with two equal I.DriMhtoAnato | .I> ^^ «mtmffli" ^^^ sources of tension in opposite directions a linearly rising, steepness ver 5 B _{the respective at the beginning and end of a} c Sage roidr, j ' _{number of clock pulses} t *, which generates sawtooth voltage tooth generator, one of f ™ ^ «^ KS time intervals in which the measuring * mende clock pulse paying counter with a sawtooth voltage compared ^r Agreement of an input measurement voltage pnaseuegi, with the sawtooth voltage by signaling the io whom «ι. ^ ajog.Digitaiwandler is known from ) ' Evaluation of the counter content enables ^El «™ _{Qg 32} | ^ _{Esenllich for} analog digi ^if Comparison circuit and with two equal ^ large de : U U> ^ ^ ^ ^ ^ Reference voltage sources of opposite Po- »ü« ^ _Gr " _usually ^ f larity. each at the beginning and end of a to ^ S _{d size umzu} _ _ul by a predetermined number before clock pulse i _S ^ tiijd. > P ^ t higher accuracy worked sen certain time interval, in which also ™ ^ ^O _n ^a _{can also be} the converted measurement ξ _{the measuring phase is, process better} with the sawtooth tension ^ ™ / ³ ^^ and .f be compared, thereby g ^ ennzeich- ^ V ™ _known analog-digital converter, '* net that the sawtooth generator (1) has an analogue uDenragciK ^ _ _: ^ _ _{:: u} ^ _ "" u ";L" Tt j .. n ..:.