DE2163831C3 - Receiver for pulse signals that are deformed on the transmission path - Google Patents

Description

The invention relates to receivers for pulse signals deformed on the transmission path with scanning devices to convert the received signals to digital sampling signals and the corresponding Sign signals, with multi-stage storage devices for receiving the signals, with commutator devices for sequential sampling of the signals at each stage, with delay devices for recording the sign signal and generating delayed duplicates of this signal, Multipliers for picking up delayed duplicates and the non-delayed signal, devices for generating profit factors for the stages, accumulator devices for adding up of the formed products and an error scanning generator device.

With the introduction of communication systems with high transmission speeds under

Wireline reversal problems arose due to distortion and intersymbol interference, caused by the overlapping of ringing signals of every single transmitted bit with the signals of bits transmitted later or earlier. Various methods and devices have been used used to make these undesirable effects as small as possible. The device of The "transversal equalizer" is of greatest interest to the present application. The first transversal Equalizer for versatile correction of distortions or intersymbol interference data transfer is disclosed in U.S. Patent 3,274,582.

Also of concern is U.S. Patent 34! 4 8! 9, which relates to a transverse equalizer directed, in which the equalizer tap gain is adjusted so that a corresponding sampling of the Transmission system impulse response becomes zero. Therefore, if the system impulse response is at the clock rate is sampled, all but one of the samples are zeroed by the equalizer. Three bigger ones Disadvantages of the device mentioned are the following:

1. The automatic adjustment process fails when the intersymbol interference becomes severe. This occurs when the sum of the absolute amplitudes of the intersymbol interference terms exceeds the absolute amplitude of the desired pulse response sample.

2. The equalizer causes interference elements outside of the range of the equalizer, thus causing a very undesirable operation when the intersymbol interference is strong and if each tap gain is adjusted so that a corresponding one Intersymbol framer is brought to zero.

3. With strong and medium intersymbol interference causes an adjustment of the profit taps according to the above patent generally a statistical noise which is amplified more than the desired signal component.

US Pat. No. 3,368,168 is of further interest. According to this patent, the scheme for the adaptation of each tap gain first an analog error sampling, multiplied by a digital decision, transmits the sequence of such a sample product through a low-pass filter for approximate averaging (or integration) and samples the output of the low-pass filter to get a Error polarity signal that is used to increase the tap gain loss. the The use of analog quantities has disadvantages in terms of accuracy and device design.

Furthermore, the device according to the US patent correlates an error signal with digital decisions, while it has been found to be more beneficial to add an error signal to the equalizer input and delayed Correlate duplicates of it. In the US patent, every tap gain (or tap damping) adapted to bring an intersymbol framer to zero. It is better if each tap gain is adjusted in such a way that all intersymbol interference terms from -cd to + 00 should be considered, even if the equalizer only has a small number of taps

35 owns. This results in a reduction in all of the intersymbol interference terms.

An equalizer that works in the magazine IEEE Trans. Comm. Technology, Vol. COM-18, No. 4, August 1970, pp. 377 to 395 see in particular FIG. 12.

The input converter supplies ten parallel bits plus one sign bit via gates in corresponding circulation shift registers that serve as data storage. The six most significant bits are stored in a downstream Signalregistcr and provide data that are used for the Bring tap gains up to date. To do this, it is necessary to use the data stored in the signal register and delayed bits in the subsequent multiplier with an error signal! to multiplier., obtained from an error register. In addition, the multiplier has to do a second job perform, namely the full complement of the ten bits plus the sign bit for each signal sample with multiply the corresponding tap gain from the tap gain register by each term of the To deliver convoluted sum that is generated in the downstream accumulator. That over a period of time terms accumulated from 63 samples (as stored in the data memory) then yield the convolute sum to the quantiser. The three most important bits of the value quantized in this way are called the Data decision accepted. The remaining bits then represent - insofar as they are one of zero have a different value - the error, the value of which is then fed to the error register.

Bringing the tap profits up to date is therefore carried out in such a way that the 6-bit plus sign bit representation of each one Sampling containing delay signal registers with the value in the error register by means of the multiplier is multiplied (i.e. as a second multiplication function of this multiplier) and that the resulting error signal is worth the tap gain in a series adder (12 bits plus sign bit) is added, which is stored in the downstream shift register. These values from 12 bits plus sign bit are then circulated.

From page 388 it can be seen that the time interval of T = 312.5 μβ for the representation of 10 bits plus sign bit results in a time of 4.85 μs for each sample. Within this interval of 4.85 μβ as well as for each of the following 63 scans, the corresponding term of the convolute sum is formed by the multiplier. In a second part of this 4.85 μβ, the tap profits are then brought up to date with the same multiplier. Because of this double function, a gate circuit is required to switch the multiplier to the respective function. Furthermore, a great number of multiplications have to be carried out in order to achieve a complete multiplication of the many bit words plus sign for each update of the tap gains as a function of an error signal or as a function of a term that is derived from a previous convolute value and thus comes from the previous symbol period and not from the current one. This also requires the delayed signal register.

So either two multipliers are required or one multiplier and an expensive one

Switching network for the multiplication to form the convolute sum and that to form the to carry out tap gains that have been brought up to date. The structure is therefore complex.

The object of the invention is to simplify this complex procedure and thereby the To reduce circuit complexity and also to make corrections due to the current bundle of files to be carried out on the basis of the previous bundle term.

The object is achieved according to the invention in that the scanning devices receive a digital signal deliver where the i-th sample is equal to

Xi = ΣΙ V. - * t

and the (ι + m) -le sampling is the same

^X i + m ~ Σ! Wi + mk

where Zi ₁ = the fe-th sampling of the system impulse response before equalization and d ^ _k = the received digital symbol in the i'-A-th sampling time, that the sign signal Sgn is x _{j + m} , that the delay device is N stages has, only picks up the sign signal and has a total delay of NI {N> 2) sampling intervals; that the duplicates of the sign signals are delayed by N -1, the fc-th duplicate being Sgn x ^ _k ; that the multipliers take N-2 of these N -1 delayed duplicates and the non-delayed signal Sgn χ, - _{+ m} and a Fchler signal y, to provide N-1 product signal c .Ig ₄ , = Aw ')', Sgn x, _i , where -m <k <n, N = m + η + i and K is a constant; that the devices are provided for the simultaneous generation of a fixed gain factor and N -1 variable gain factor in response to the .Igi.i signal once at each cycle time, the increment of the fc-th gain during the i-th cycle time being the signal. 1g is _ti , where m is the number of profit factors preceding the fixed profit factor and η is the number of succeeding profit factors; that multipliers are provided for multiplying the sampled signal from each of these taps to a corresponding one of N gain factors, to form N products; that the accumulator sums up the JV products formed at each cycle time in order to generate an output signal y, - and a signal 2, - of the q most important bits in the accumulator, if every received D: gita! s: gns! 2 'can assume values; _{that the error sampling generator} device consists of the following parts: a compute-j> iD device, consisting of a storage device containing a signal I ₀ corresponding to the system impulse response and a multiplier connected downstream of the storage device, the computation-yj, Device receives the signal 3, - from the accumulator and forms the product y _iD = J ₀ ^; and from a comparator, which the product yy _iD and another output j>_; of the accumulator in order to form the signal Y ₁ by comparing the recorded signals, which signal is fed to the multipliers (-m ... + n) as an error signal. This incremental way of working avoids the use of multipliers; instead, much simpler OR gates are used. In addition, an error term based on the current Konvolutterm is used to control the tap gains. This makes the equalization more effective.

According to advantageous developments of the invention, instead of the signal Y ₁ , its sign _{signal (Sgn V 1} -) can also be used. The same also applies to the signal x, _ _k . The somewhat reduced accuracy is compensated for by the simplification of the circuit. Advantageously, the value Z ₀ does not necessarily have to be a fixed value. Rather, this value can be made adaptable to the respective transmission conditions.

The present system is based on the adaptation of the gain of the / c-th tapping point g _k to a value which is the cross-correlation function

j = XjA- * (»

- X

to a minimum, where Ij is the error in the j-th sample of the system impulse response, related to the equalizer output, and / ij_ _{4 is} the (j-k) th sample of the system impulse response, related to the equalizer input.

This adaptation criterion was derived in order to optimize the overall receiver effect zj. with the combined effects of intersymbol interference and noise. Furthermore, this criterion leads to the convergence of the automatic equalization process with much greater distortion (or intersymbol interference) compared to the distortion and interference permitted by the zero enforcement method of US Pat. No. 3,414,819. This adaptation criterion differs from the adaptation method according to the just mentioned patent, in which each g _{k is} adapted so that a single l _k is brought to zero. It also takes into account any errors in the pulse response samples. all Ij from j = - χ to j = + ». For this reason

According to this criterion, the adapted equalizer does not bring about a great increase in some undesired ones Intersymbol interference terms while others are being corrected, even then not when the intersymbol interference is strong before equalization.

According to one embodiment of the receiver according to the invention, each g _k is determined by a difference value at a clock time

Ig ₄ ... = fc, (Sgn y.) Sgn x, _ »

(2)

is increased so that each g _k is changed so that previous cross-correlation is minimized.

Three other alternatives to this solution using difference values are:

.Ig _1. , - = K ₃ (Sg _n Vj ■ Iftu = K + Yi Xi- _t .

(3) (4) (5)

where K is a constant to obtain the desired magnitude of the difference value, .τ, · _ _{4 is} the signal amplitude during the (i-Jfc) th clock interval at the equalizer input and Y _{£ is} an error sample derived from the equalizer output.

The invention is combined in the following description on the basis of an exemplary embodiment explained in more detail with the drawings.

It shows

F i g. 1 shows a transmission channel in a block diagram, in which the receiver according to the invention can be used,

F i g. 2 in a block diagram a preferred embodiment of the invention,

3 shows a first in a block diagram Computing device for use with the receiver of FIG. 2,

F i g. 4 in a block diagram a second embodiment of the computing device,

5 shows, in a block diagram, a third embodiment of the computing device I ⁷ Ur partial response signaling,

F i g. 6 shows, in a block diagram, a fourth embodiment of the computing device for partial response signaling;

Fig. Fig. 7 shows, in block diagram form, a proportional incrementing device of the embodiment from F i g. 2 and

F i g. Figure 8 is a block diagram of an apparatus for "learning" a larger sample of a system impulse response for use with the embodiment of FIG. 2.

1 illustrates, in block diagram form, a typical transmission channel 12 to which the described receiver can be connected to receive the output signals of the channel. The broadcast channel 12 is used when the transmission must take place over a bandpass communication channel, such as. B. a sound transmission line used in telephone traffic. Since digital data cannot normally be transmitted directly through an audio transmission line since such lines cannot transmit DC signals, a system of modulators and demodulators is used. Typically, an input signal in digital form containing the information to be transmitted and, in some applications, also the time information, is fed to a shape filter 14 which pre-deforms the digital data to make it more suitable for transmission. The output of the shape filter is fed to a modulator 13 in order to modulate the output by means of a carrier and to generate an output in the audio frequency range. The output of the modulator is then generally fed to a band pass filter 18 to remove signal frequency components unsuitable for the transmission path 15 before the signal is applied to that transmission path. In most applications, the frequency passband of the filter 18 is made approximately as wide as the bandwidth of the transmission path 15. A second bandpass filter 19 receives the output of the transmission path 15 and switches off the noises and special signal components which are outside the bandwidth of the transmission path. The received signal is then processed by the demodulator 16 and by the low-pass filter 20 in order to provide the received baseband signal 30, which is then fed to the transversal equalizer 10.

In most applications it is desirable that the data transmitted be as statistical as possible. A statistical character of the data can be ensured by combining the digital information to be transmitted with the output of a digital pseudo-statistical sequence generator in a modulo-2 adder. A modulo-2 addition of a pseudo-statistical sequence with the input information generates a data sequence that is itself statistical. In order to recover the original information, the corrected received signal can be combined with the output of an identical pseudo-statistical sequence generator in another modulo-2 adder. The apparatus for achieving statistical character is shown in Fig. 1 as the modulo-2 adders 21 and 27, together with identical pseudo-static sequence generators 22 and 24. The design and operation of pseudo-statistical sequence generators are well known to those skilled in the art z. B. in the publication "Digital Communications with Space Applications" by SM G o 1 ο mb et al., Prentice-Hall, NJ (1964), described. The discriminator 11 examines the amplitude of the signal at the output of the equalizer (or samples of these signal amplitudes) in order to determine the value of each recorded character.

The received baseband 30 contains the received data in a distorted form due to the entire impulse response characteristic of the transmission channel 12. In the case of a specific transmission channel the individual components of the signal distortion properties may be known and therefore easily compensated. The distortion properties of the transmission path 15 are general unknown before transmission, and in most cases they change during the time of transmission. The frequency-amplitude and the frequency-delay behavior of the transmission path 15 leads to a noticeable distortion of the transmitted modulated digital signals. If consecutive Data bits are fed to the transmission channel 12 at a sufficiently low rate the fading associated with each bit has the option of before the transmission of the next Bit to subside. The baseband signal is clearly experienced at high transmission speeds Distortion due to interference with the lingering signals from previous and subsequently transmitted pulses, and as a result of undulating distortion caused by Changes in the properties of the transmission path arise. The impulse (or single character) response of the variable channel 12, the automatic equalization is of fundamental importance and is referred to in the following as "system impulse response before equalization".

In Fig. 2, there is shown a digital embodiment of the automatic transverse equalization system of the receiver. The received baseband signal 30 enters a sampler and an analog-to-digital converter 32. This device samples the received signal once per clock time and converts each sample amplitude into a binary number which is referred to as x _{i + m} . The sample timing is controlled so that one sample is near the main peak of the system impulse response. Although the received digital signals overlap in time due to the distortion and the intersymbol interference, the signal is once in

is sampled near the main peak of the received signal component generated by each transmitted character (or symbol). Usually, a quantization accuracy of 12 bits or less is required for each sample. The timing (sampling rate) of a sampler is controlled by timing pulses obtained from a frequency divider 33 generated by the timing recovery circuit 34. The timing recovery device includes a stable clock and a frequency divider chain and synchronizes the output of this frequency divider chain with zero crossings of the received signal. Since these zero crossings contain time flutter, an averaging of multiple zero crossings (or the approximation corresponding to such averaging) is used to achieve correct synchronization of the timing recovery output. This type of timing recovery is well known. In Figure 2, the timing recovery output is a synchronized pulse train having a pulse rate equal to N times the transmission clock rate, where N is the number of stages (or tap gain) of the equalizer. The frequency divider 33, when connected between the timing recovery block 34 and the sampler and analog-to-digital converter 32, divides the timing recovery signal frequency such that one timing pulse is provided at point A per clock interval. Timing pulses that are / V times the rate of the transmitted clock frequency are then delivered to point B. A delay line 26, consisting of a number N = η -r »i + 1 of x _t registers, provide the required signal delays if a digital version is selected for the system, where m is the number of stages preceding the main tap gain and η is the number of stages Main tap is following levels. In the case of an analog implementation, the x, registers are replaced by a multiple tap delay line. Each of the x, registers has an input and an output connection.

The numbers m and π are determined by the size of the intersymbol interference and the accuracy of the equalization required for the respective application. If the portion of the system impulse response that follows the main peak is longer than the portion that precedes the main peak, the equalizer will contain more profit taps preceding the main tap than following it, a property not found in previous automatic equalizers. For a transmission of 9600 bits per second over rented telephone channels one uses m - 14, π = 6, for example.

A commutator 100, which may be an electronic switching device, connects the output of the sampler and analog-to-digital converter 32 in series with the input of the X ₁ registers in response to the timing pulses from the frequency divider circuit 33 at point A. The commutator 100 therefore switches at a rate of one position per clock time interval from the register x _{i + m} - _t to the next lower register in F i g. 2. Each of the X ₁ registers stores a signal sample in the form of a binary number. The number of bits required for each binary number depends on the application and is approximately 8 to 12 bits in the embodiment shown.

When a new sample is read into an x register the old scan is eliminated. During each heartbeat interval the latest replaces incoming signal sample the signal sample that has been stored for the longest time. This occurs in only one Register during a given clock interval time. Then during the next clock interval the next sample is read into the next lower χ, - register, with the old signal sample

ίο is replaced in this register. There are n + m + 1 of these x, registers and to the particular one in FIG. The commutator time (position) shown in FIG. 2 store these register _{signal samples x, _ n} through x _{i + m} which are used to calculate the fth transmitted digit d _{. During the last clock time the sample was χ, _{+ m} into the second register from the top in FIG. 2 has been read in, whereby the scanning x, _ "_, has been replaced in this register. One cycle time later this becomes x _; Registers contain the samples x, - "+ i through x, _{+ m +} i, which are used to compute the (i + l) -th transmitted digit _{di + l.} To get the digital equivalent of a transverse equalizer with N taps, set / 1 + m + 1 = N. A commutator 200 is connected between the multiplier 24 and the outputs of the X ₁ registers. In response to the timing signal from timing recovery circuit 34 at point B , commutator 200 switches at a rate N times the clock rate to detect all N positions during a clock interval. This commutator is arranged such that it begins at the point of a signal sample which has been stored the longest, ie it starts at a lower position during each clock interval than during the previous clock interval. The commutator 200 is preceded n + m + 1 times per clock from the input of the frequency divider 33 and is preceded once per clock from the output of the frequency divider 33, the output of which is fed to the commutator progression circuit 25. As stated earlier, electronic circuits for commutators are well known to those skilled in the art and need not be discussed in detail.

The sign of the sampled baseband signal 30, which is supplied by the sampler and analog / digital converter 32, is fed to a shift register 31 with η + m stages. The output of each stage of the shift register 31 is an input terminal of a corresponding index is provided with exclusive-OR gate OR_ _m to OR. fed. The input to the OR gate OR_ _m comes directly from the sign signal, Sgn x _{i +} ", which comes out of the sampler and analog-to-digital converter circuit32. The second input signal, Sgn V ₁ -, is fed from a comparator circuit 34 to each of the exclusive-OR gates. The output of each OR gate is connected to a correspondingly indexed up / down counter to g_ _m g ". The output of commutator 300 is fed as an input to multiplier 24, which multiplies the input signal from commutator 200 by the input signal from commutator 300 in order to generate a product signal which is fed to accumulator 40.

The g-counters store binary numbers that represent the tap gain settings of the transversal equalizer g_ "through g". During a given clock interval, e.g. B "if the commutator is 200 x, _.

until x _{i +} "scans, the commutator 300 scans g" to g_ "synchronously and these g's are ^{read into the multiplier 24 f:} n. The multiplier 24 multiplies g "times x, _", g "_, - times *, -_" +, etc. The accumulator 40 adds all of these products in a clock interval to in binary form

to obtain.

The output of accumulator 40 is a sequence of binary numbers (approximately 6 to 12 bits per number, depending on the application), each number being an instantaneous amplitude sample of the equalized signal represents, with one sample per cycle. The exit can, however, be taken in a different form by using additional switching means, as explained below. The / th sample, y ;, is the sample of which the i-th digit </ ,, is calculated. The (/ + 1) th equalized signal sample is e.g. B.

M-Hl-

This is a sample from which the digit </ _{i + 1 is} calculated. It should be noted that the commutators are synchronized in such a way that g ₀ z. B. is multiplied by χ, - if y, is calculated, and _{multiplied by X 1+} , if y _{i + 1 is} calculated.

Since the accumulator 40 is a typical digital accumulator, the digital decisions can also be read out of it. If z. For example, if conventional Q-level signaling is used, where Q-2 ^q and q is an integer, the q most significant bits in y, the d, represent the recipient's computation of d _h and these q bits can be calculated directly can be read out from the accumulator. The 3, output is fed together with the Vj output to a calculation circuit 44 which provides as an output a signal y _iD which is proportional to the calculated product of the i th digit d and the impulse response sample / ₀ , separately from that total signal y _{ . The> _ID signal is fed to a comparator 34. The comparator provides an output signal Sgn Y / which indicates the difference in sign between the signals y, p and yj.

Let us now consider the mode of operation of the adaptation of the equalizer, ie the automatic setting of the multiplication factors g in the up / down counters 36 to values which combat the intersymbol interference and the noise brought in by the transmission channel. In the present case, which is shown in the drawings, the output signal _{sample x (+ m of} the analog-digital converter 32 is fed to the commutator 100. At this time, the converter 32 also provides a binary one-bit output Sgn x _{i + m} = S _{i + m} of the shift register 31. Many previous values from S, running down to the shift register, wherein S, the polarity of the / th received signal sample is being scanned with the Taktratc. Each of S ₁ is from one stage of the Shift register led to an input of an exclusive OR gate.

During this time, the calculated digital value d runs from the accumulator 40 to the multiplier 41 where it is multiplied by a constant I ₀ equal to the amplitude sample of the main peak of the impulse response of the system including the equalizer. First, assume that / ₀ is known in advance and can be treated as a constant. This assumption is correct in some applications where an automatic gain control externally connected to the equalizer will _{keep / 0} constant within the required accuracy, although in some applications it will be necessary that the receiver continuously detect / “and keep it up to date As will be explained below.

Assuming that 2, is correct (3, = d ^

the output of multiplier 41 at the i th clock time is a digital representation of y iD, the desired value of the equalizer _{output signal sample} y _; . In other words, the correct output of the multiplier 41 is y _iD , the value of y _h which is obtained for the case of a distortion-free, noise-free channel. The comparator 34 compares j ;, with y _iD and generates a binary output signal Sgn Y ₁ , where Vi = 3Ί- - y _iD . The comparator output is a binary “1” when yi-yiD is positive and a binary “0” when y, -y _{iD is} negative. This comparator 34 can be a binary adder which simply determines the most important bit of _y, _{-y iD} . This most important bit represents Sgn Y ₁ , which is fed to the exclusive OR gate.

Each exclusive-OR gate 32 receives two one-bit binary numbers. The exclusive-OR gate connected to g _k receives e.g. B. the two binary numbers Sgn V ₁ - and S, _ _t . The output from this exclusive OR gate is a binary "0" if Sgn Y ₁ - = S, _ _t , otherwise it is a binary "1". This exclusive OR gate causes the connected up / down counter to count down when Sgn Y, = S, -_ * (when the exclusive OR output is a binary "0") and by a count is incremented when Sgn Y, = S, _ *.

Therefore, with the exception of g _0, every equalizer gain factor, every g, is changed up or down by a small value once at every clock time. Some of the changes will be in the wrong direction, but generally the g will be shifted in the right direction so that after an initial learning period within a few incremental sizes the g will be brought to optimal values

. will. By making the incremental size _{very small with respect to g 0} , precisely optimized fits are obtained.

The profit factor g ₀ is fixed and stored in the _{counter labeled g 0.} The equivalent of being the incremental size of all g except for

^Making SS 80 ' senr small means that g _b becomes equal to a large number in each of the up / down counters. The larger this number, the slower and more accurate the equalization will be. The best compromise between speed and accuracy depends on the application. For fast and sufficiently accurate equalization, g _{0 is set} approximately equal to 2 ¹⁰ in each of the up / down counters, for slow and very accurate equalization approximately 2 ¹⁵ . This iterative, incremental method of driving the g in the up / down counters means that the equalizer is automated.

In the above discussion it was assumed that the _{gain factor g 0 is} fixed and that the decision threshold of the decision device is f

IS

this fixed g _{0 is} correctly matched, either by automatically adapting this decision threshold or by using a suitable AGC in front of the equalizer (AGC = automatic gain control). Instead, the profit factor g ₀ could be adjusted automatically by the same method used for the other profit factors and a fixed decision threshold could be used. Then g ₀ and the other gain factors would be automatically adjusted to these fixed threshold levels, provided that these levels are initially approximately correct.

In Fig. 3, which shows a more detailed block diagram of the Ji ₁ J, calculation device 44 for applications in which a determination of I _{0 is} necessary, the signal 3, from the accumulator 40 is fed to a binary section detector 43 and also to the multiplier 41. The detector 43 detects the sign of the received signal 3, · and generates an output pulse which is a binary representation of the polarity of 2, and feeds this output pulse to a modulo-2 adder 45. With the binary signaling, Sgn 2 _f = 3 and the detector 43 is not required. Even with multi-level signaling, the accumulator 40 could be arranged to output Sgn 3, and the detector 43 would not be needed. The signal Sgn V ₁ - from the comparator 34 is fed to the modulo-2 adder 45. The two Sgn signals, Sgn j>, and Sgn d _h are added and generate the increment signal (Sgn V ₁ ) (Sgn 3,), which is _{fed to the / O} counter 47. This signal is an indication of the polarity of the error of the last previous estimated J ₀ stored in the! (, Counter, and this signal is used to add or subtract a count from the / "counter, in the direction , in which the error of the estimate / _{0 is} reduced. After many small increments, mostly correct, the estimate of / ₀ becomes accurate. The blocks 43, 45 and 47 contain the recognition - / "- means 42. The

S multiplier 41 multiplies the output of the { _O counter 47 by the estimated digital value d _{h to} obtain the output signal y _iD = I ₀ 3.

This incremental procedure is explained in more detail below:

ίο The i th equalizer input sample is

_Xi =

Everyone/

The i th equalizer output sample is

y <

alley

For each of the many possible types of signaling, the desired value of y is _t

y, D =

(10)

all j

where l _{j0 is} the / th sample of the desired system impulse response. The error in the ith sample of the equalizer output is

= y, -y _l0 =

whereby

Everyone/

(12)

is.

From equations (8) and (11) we get

= (- ■ · + l-A + 2 + '-! <*, - ♦, + Wl + hdt-l + Wi-2 + · ■ ·)

(13)

The transmitted pulses, which represent the digital values d , are balanced statistically and in opposite directions around zero. If z. For example, the possible digital values are 0, 1, 2, 3, the values are represented by transmitted pulses of amplitudes -3, -1, 1 and 3, the mean frequency of occurrence of a pulse of a given amplitude being approximately equal to that mean frequency of occurrence of a pulse of the same absolute amplitude but reversed polarity.

This gives you with statistical or pseudo-statistical dual data, if necessary by arranging a random modulator and a random modulator in the transmitter Random demodulator in the receiver can be guaranteed for the statistical mean value of the product

ii = YiXi-ä =

(14)

Everyone/

where K is a constant. This is also confirmed by equation (13), since because of the statistically balanced signaling, the data product terms of the form djij average to zero, with the exception

from i = j, where a mean value of d] results. the end It can now be seen from the correlation function expression in equation (1) that a measure for the by Adaptation of the fc-th profit tapping point g _k size to be reduced _{could be determined by averaging YfX 1} -k over many scans.

Assuming, however, that the product V ₁ X, _{-1 is taken} once for each clock interval and g _k with is added by means of a small increment, one obtains

(15)

ss where k _{t is} a small constant.

Because of the statistical data terms and the noise, many of the individual increments become inaccurate be; but using many small increments provides an averaging process and yields

therefore, because of the statistical relationship given by equation (14), approximately the desired value for each profit tap point g _k.

Since each profit tap point must be driven in the right direction, the incremental The fixed size process expressed by the equation (2) or the incremental process expressed by the equations (3) and (4) also each g _k to approximately the desired value.

17 18

The following matrix is important for the impulse response samples at the equalizer output, the / 's, as a function of the impulse response samples h at the equalizer input and the profit taps g.

g-i ... h-2 A-! A ₀ A ₁ A ₂ A ₃ A4 A5 A ₆ go ... h-3 A-2 A-, A ₀ A ₁ A ₂ A ₃ A ₄ A ₅ gl ... / 7_ ₄ A-3 A- ₂ A-i A ₀ A ₁ A ₂ A ₃ A * G ... fc-, A- * A-3 A-2 A-, go A ₁ A ₂ A ₃

■ •• / -3 / -2 / -, / 0 k I ₁ I ₃ UI ₅

... r_3 t- ₂ r_, f ₀ i, t ₂ t ₃ u I ₅

Note that if a given is adjusted, 25 will yield gains or losses. The outputs of the gain tap point g _k by an increment size g _{k of} the amplifiers with fixed gains are summed up in the sum of the effect on the j-th output sample Ij represented by miser 52 to provide the output y _iD ,
is replaced by Jg _k hj- _k . Therefore, hj- _{k is} a measure of the digital decision <4, - and the signal Sgn V ₁ -effectiveness of each profit tap, Ig ₁ to the correction of the comparator 34 of FIG - 30 recognition Zj, device identical to the response scanning Zj. Hence, it is the criterion for the recognition device of FIG. 2 is. The result of a reduction in the error of the fixed gain of the detection fo device is the tapping adjustment, as indicated by equation (1), output signal Z ₀ , which is the estimated value of / ₀ . Which is expressed, the sequence of the error terms (Ij) with the estimated value Z ₀ is fed as a reference signal of a precise effectiveness of this profit tapping point to the correct- 35 AGC control, which is in front of the sampler and laten. Taking into account the effectiveness of each analog-to-digital converter 32 is arranged to control the gain taps in the process of correlating the amplitude of the adjustment picked up by converter 32 from a tap gain to baseband signal 30 from being controlled. The AGC control is made large, which contributes little, the 53 controls then to reduce the mean signal level of 3, - and intersymbol interference and thus 40 Y _{1 to halve Z 0} to a fixed, preselected level to control noise gain of the equalizer. These ten so that all fixed gains of the amplifier 51 considerations show that this adaptation process is correct, that is, that the received signal level corresponds to an approximate minimization of the combined effects of the scale factor used in the fixed inputs of all intersymbol interference terms and positions.

Noise reveals a fact that is through extensive 45 another method of signal transmission

Analysis and computer simulations was confirmed. the partial response signaling, the controlled intermediate

F i g. 4 illustrates another embodiment uses symbol interference. For each part of the estimator V ₁₀ device 44 of FIG. In case 50 an outbreak of errors in the final out of a Q-level signaling (where Q = 2 *) must cause the digital output circuits. For each shift register 50 the equivalent of a ß-level register. These signaling methods can be the effect window, with possibly q stages per digital mode and the simplicity of the recognition y _il? -Signs are used. The shift register is direction 44, compared to the digital equivalent of a delay line, 55 arrangement in Fig. 4, by directly using the type of which is able to clock the digital symbol with no error time per Stage to delay. reproduction occurs. With the exception of the

The digital decisions run in the shifting-y _jD -device refers to the above-described

register with clock rate and at any given time cancel automatic equalizer of the receiver

is the last η previous digital 60 of each partial response signaling scheme.

Decisions in the shift register. At the time, generally a digital character (or symbol)

to which the digital decision <?, defined at the shift register D _{1 in} such a way that
appears at the entrance, the decision 3, _j,

0 <, j <η (for all integer values of; between ^ _{0. =} Γ ~ [ _d . _{= Y.} ^ _{D <} . ₌ '. _{Y. N} , (16)

0 and n) multiplied by a fixed, previously fixed- 65 j ~ Od ₁
set profit factor Z ^ _D. Amplifier 51 with fixed

Profit, digital multipliers or resistance - with the sum totaling over the full result

Adding networks can be used to provide fixed amounts of (/ _JD ) made in each respective partial response

scheme is used. Usually a partial respondent calculates (D ₁ ) directly instead of (J ₁ ). The controlled intersymbol interference associated with the (/ jo) does not cause error propagation in the [D ₁ ).

There is no loss of generality to assume that I ₀₀ = I ₀ , and in some applications an AGC / ₀ operating independently of the equalizer can keep close enough to a constant value (which is known in advance) to meet the need a recognition io device to eliminate. With this, the recognition YD device simply becomes a multiplier that multiplies D ₁ by the constant / op ~ Ό, as shown in FIG. 5 shown. The signal y _; is fed to the decision device 55 to determine the amplitude level of y _t which is quantized to the same number of levels as the number of possible values of D ₁ -, the quantized amplitude of which is the signal D ₁ -. The decision device estimates the signal D ₁ - from the amplitude level of y i, if D ₁ - is a known function of a transmitted digital character U ₁ for any particular type of partial response signal. The entire automatically adaptable equalizer can then work with any partial response signaling scheme in which Z ₀ is known in advance with sufficient accuracy. The signal Z ₀ is stored and multiplied by the signal Dj in the multiplier 52. The multiplier could be avoided by designing the detector (or multi-level sampler) so that its output signal level is equal to Z ₀ D ₁ -. The summing device 70 subtracts the multiplier y _w from y _{h in} order to obtain the error signal 'Y ₁ -, which is fed to the multipliers which the exclusive-OR gate of the F i g. Replace 2. The equipment in FIG. 5 replaces the estimator Y _iD device 44 and comparator 34 of FIG. 2 if, instead of a fixed increment size of the tap gain, an increment size is to be used for the tap gain adjustment which is proportional to the error V ₁ -.

For most data modems with high efficiency and which require precise equalization, it is necessary to determine Z ₀ or some associated scale factors, such as e.g. B. one of the remaining l _jD . Numerous methods of determining Z ₀ in partial response schemes are available.

F i g. 6 illustrates a method of determining I ₀ and error sampling V ₁ -. The signal sample y i from the output of the accumulator 40 is fed to the summing device 54. Assume first that

We can assume that D ₁ - is mostly correct, and that if it is correct, the relationship

y _f * I ₀ D ₁ .

(17)

At the beginning of the equalization this approximation is sometimes very imprecise, but the determined / ₀ is driven in the right direction due to the statistics.

Summer 54 subtracts from y, the estimate signal

hü = 'kDi, (18)

the creation of which will be described. The output of summer 54 is the signal is valid.

From equation (20) it can be seen that for most samples

Sgn Y ₁ Sgn D _; = Sgn (Z ₀ - Z ₀ ).

Next, the signal Y ₁ - goes to a binary section detector 56 which produces a binary output representing Sgn Y ₁ -. The decision device 58 receives the signal y _i and supplies the output signal D ₁ - the Sgn detector 57. The present detector then supplies the modulo-2 adder with the desired signal Sgn D ₁ . The modulo-2 adder essentially multiplies Sgn D ₁ - by Sgn Y ₁ -. If, therefore, the estimated value Z _{0 is} increased by a very small increment value once per cycle in the direction indicated by Sgn Y ₁ - Sgn D ₁ , most of the increments will lie in the direction which reduces _{/ 0} - / _0. The estimate Z ₀ will eventually become accurate when the increment size is sufficiently small. Incrementing J ₀ is accomplished by using the output of the modulo-2 adder to increment the / "counter 47 once per clock in the direction shown by Sgn Y, Sgn D. The multiplier 41 multiplies Z ₀ from the Z ^ counter 47 by D ₁ from the detector 57 to form y ₁₀ = I ₀ Dj which is passed back to the summer 54.

The device in FIG. 6 replaces the estimated-y _lf) device 44 and the comparator 34 of the F i g. 2. The internally generated D replaces input 5, and the output is Y, instead of Sgn Y ₁ -. Error sampling Y ₁ can be used in place of Sgn Y ₁ in applications where the speed and accuracy of equalization are important enough to avoid the added cost of using multipliers in place of the exclusive-OR gates of FIG. 2 to justify.

Most of the discussions above assumed a fixed increment size in recognizing the (g _t ) and / _0. In any of the above implementation changes, the increment size can be made proportional to the estimated error when adapting the detected size. With a proportional incremental size, the detection can proceed very quickly at the beginning of the activity, if the errors are large, and then becomes very accurate later, since the errors converge to zero and the incremental size becomes very small. In addition to noise, there are numerous error terms in the expressions used for recognition, such as B. / j. Z ₄ , d _i% d _k , j Φ fc- Each of these error terms has a mean value of zero, but a variance that depends on the length of the averaging, integration, or correlation used to determine that variance to zoom out. A very small increment is essentially used in long term integration (or correlation) to reduce the effects of noise and bring the variance of undesirable temperatures to very low values.

The system of FIG. 2 can be modified for a proportional incremental calculation of the (g _k ) by removing the exclusive-OR gate and

each OR gate by the in Fig. 4 is replaced. The signal V ₁ from summing device 70 of FIG. 5 or the summing device 54 of FIG. 6 enters the multiplying-by-Ic ₉ device 60. The multiplier 60 multiplies the variable amplitude signal sample y, by a preselected constant k. Within wide limits it holds that the area in which original learning converges becomes wider the smaller k _{g is} made, and the more precise, but slower, the recognition becomes. A good value of k _g is 2 ~ ⁷ when g ₀ = 1. Next, the quantity Y ₁ Ic ,, is multiplied by the binary number S, _ _{t of} the corresponding stage of the shift register 31 by the multiplier 61 in order to determine the size and polarity of the increment by which the fc-th up / down- Counter g _k of FIG. 2 should be incremented. The output of the multiplier must of course have the same digital format as is required for the output of the respective up / down counter.

An alternative to making the increment size proportional to Y _{1 is} to make it proportional to x, _ _k .

If rapid detection is not necessary, a fixed increment size provides a mode of action that comes very close to the proportional increment size, but leads to less complex devices. In typical conditions, reasonably precise detection can be obtained in about 50 to 100 milliseconds using proportional incrementation versus about V ₄ to V ₂ seconds with fixed incrementation.

An important alternative is to use a relatively large fixed increment during the first To use 50 to 500 milliseconds of original detection and then to very small solid ones To switch increment sizes in order to achieve an exact continuous adjustment.

For economic reasons it is desirable in some applications to use only a few transverse equalization stages. Sometimes a coarse equalization can be tolerated, and in other cases a coarse transverse equalization can be followed by a less expensive type of equalizer that completes the equalization process. However, for coarse equalization, the method for recognizing J ₀ described above is sometimes not sufficiently accurate, since the accuracy for recognizing I ₀ depends on the accuracy with which the equalizer minimizes the undesired intersymbol terms. The following procedure provides an accurate detection of / ₀ without accurate equalization.

This method depends on / ₀ , which is the largest / j in absolute size. If another /, · prevails, this method can be applied to this l _} , since only one /, has to be recognized in order to get a scale factor for any other of the general automatic equalization schemes. If two or more of the largest I _{1 are} nearly equal and a coarse equalization is to be used, the following procedure can be used.

This method is based on the fact that when e.g. B. / _{0 is} the predominant Z ₁ -,

> 'i (Sgn

kl ₀

(21)

where ^ v ^ / \ is the averaging symbol over many signal samples means and ic is a constant.

F i g. Fig. 8 shows a method for detecting before / ₀ under these conditions. The equalizer output sample 3 ', - goes to a binary section detector 56 which converts>>, · to Sgn y i. Next:> ·, is multiplied by Sgn y _t in the multiplier 62 and the product is passed to the summing device 63. Summing device 63 sums the last N products of the last N signal samples. For accuracy reasons, N should be about 10OC or greater. With the exception of a scale factor: the sum is equivalent to the mean given by equation (21).

The costs for the devices can be reduced by employing a long-term integrator. the summing device is used, since a long term integral and a long term sum err are essentially the same.

In addition 6 sheets of drawings

Claims (11)

Patent claims: 1.Freceiver for pulse signals deformed on the transmission path with sampling devices for converting the received signals into digital sampling signals and corresponding sign signals, with multi-stage storage devices for recording the signals, with commutator devices for sequentially sampling the signals at each stage, with delay devices for recording of the sign signal and generation of delayed duplicates of this signal, multipliers for receiving delayed duplicates and the non-delayed signal, devices for generating profit factors for the stages, accumulator devices for adding up the products formed, as well as an error scanning gene: ra »or device, characterized in,
that the scanning devices (32) deliver a digital signal in which the / th scanning is equal to, and the (1 + m) th casting is equal .V ₁ . where Zi ₁ = the fc-th sample of the system impulse response before the equalization and d -, - _k = the received digital symbol in the i-fc-th sample time, that the sign signal Sgn is x / + _m ,
that the delay device (31) has N stages, receives only the sign signal (Sgn) and has a total delay of Λ / -1 (N> 2) sampling intervals; that the duplicates of the sign signals are delayed by (NI), the k-th duplicate being Sgn *, · _ *; that the multipliers (-m ... n) N-2 of these Ml delayed duplicates and the non-delayed signal Sgn χ, + _m and an error signal Y-, record to Ml product signals A _g kj -KY, Sgn *, · _ * to deliver, where -m <k <n, N = m + n + 1 and K is a constant; that means are provided for the simultaneous generation of a fixed gain factor and / V-1 variable gain factors in response to the /! ^ ,, - signal once at each clock time, the increment of the jt-th gain during the / -th clock time the signal Ag ^ ', where m is the number of profit factors preceding the fixed profit factor and η is the number of succeeding profit factors;
that multipliers (24) multiplying the sampled for the SS signal from each of these taps to a corresponding one of N gain factors are present, to form N products;
that the accumulator (40) sums up the N products formed at each clock time in order to generate an output signal y and a signal Ji from the q most important bits in the accumulator when each received digital signal is 2? Can assume values
that the error scan generator device (42, 41, 34) consists of the following parts: a compute-y, D device (44) consisting of a memory device containing a signal h corresponding to the system impulse response (42) and a multiplier (41) connected downstream of the storage device (42), the calculating device (44) _receiving the signal d i from the accumulator and forming the product y iD = l ^ d ; and from a comparator (34) which the product y _iD and another output y _; of the accumulator (40) in order to form the signal Y, by comparing the recorded signals, which signal is fed to the multipliers (—m ... + η) as an error signal. 2. Receiver according to claim 1, characterized in that the multipliers (-m ... n) instead of the signal Y _1, the signal Sgn y received as the error signal for the delivery of NI product signals g _ki = K (Sgn Y ₁ ) Sgn x, _ _t . 3. Receiver according to claim 2, characterized in that the value x, _ _{4 is} used _{instead of Sgn x, _ t.} 4. Receiver according to claim 1 or 2, characterized in that the value Sgn K _{1 is} used _{instead of K 1.} 5. Receiver according to claim 3, characterized in that the error sampling generator device (41, 34) has the following parts: a decision device (58) for receiving the output signal> ·, and for supplying an estimated value D, a quantity D _{1 of} the amplitude level of the signal y _it where D ₁ - is a known function of the transmitted digital characters d i ; Multipliers (41) which _{receive the stored signal / 0} and which form the product / ₀ D, = y _jD ; and summing means (54) for receiving the signal y ₍ and subtracting the signal y _iD therefrom to form the error signal y _t (Fig. 6). 6. Receiver according to claim 2, characterized in that devices (42) for generating the signal / ₀ are present which contain a first detector (43) which the signal 5 _; picks up and generates a signal Sgn 2; that a ModuIo-2 adder (45) is present, which receives the signal Sgn d, and the signal Sgn Y ₁ and forms the binary product Sgn d ₍ Sgn V ₁ -; that the memory device (47) for the signal Z ₀ has stored an estimate and takes in each binary product generated so as to update the estimate I ₀ with a small incremental value proportional to the binary product (Fig. 3). 7. Receiver according to one of claims I to 6, characterized in that the delay line (31) is a transversal equalizer with a plurality of adaptable gain taps (2m ■ · · g.) The cross-correlation function ^ _{makes g 4} as small as possible for the / c-tcn tap gain, where /, is the error in the jth sample of the system impulse response _{, viewed from the equalizer output, and hj- k is} the (j - k) th sample of the system impulse response, seen from the equalization input. 8. Receiver according to claim 7, characterized in that the error sampling generator device (42, 41, 34) in addition to the estimated value device (44) for supplying an estimated signal value y _{iD of} the i-th sampling of the equalizer output a section detector (43) for receiving the output signal 2, - from the accumulator (40) and supplying an estimation signal Sgn 3., which represents the sign of the signal rf, further devices (45) for multiplying the output signal Sgn 2, of the detector (43) with the error signal Sgn y, from the error generalor device (34) to deliver an incremental signal Sgn Y ₁ Sgn 2, which is the sign of the error of the last previous estimate of the amplitude of the main sample of the impulse response of the transmission system Counting means (47) for summing the incremental signals to provide _{a learned output value / 0;} and a multiplier (41) which takes the estimated signal 2 and the learned output value Z ₀ to provide the estimate Y _iD = / ₀ 2. 9. Receiver according to claim 7, characterized by a first commutator (100) for receiving the sampled input signal and for supplying sequential outputs corresponding to each sampling, in each case separated by transmission clock intervals; a plurality of register devices (26) connected to the commutator (100) for receiving and storing a sample of the input signal; by a second commutator (200) which sequentially connects in each case one of the outputs of the register devices (26) in a clock interval to an input of a multiplier device (24), and advances the sequential connection by one register position for each clock interval; a plurality of adjustable gain devices (g _m ... g ") for receiving the incremental signals and for supplying signals proportional to the positions of the gain device; and a third commutator (300) for sequentially connecting each of these supplied gain setting signals to the multiplier devices (24) during each clock interval in synchronism with the sequential connections by the commutator (200) to add a product of each of these gain setting signals and the stored sampling signals form, the accumulator (40) receiving the products so as to form the equalizer output (Fig. 2). 10. Receiver according to claim 7, wherein the increment multiplier device is characterized by a delay line (31) with N taps for receiving the sampled input signals; by a number of N + 1 OR gates, one of which (- m) contains this OR gate as an input of this sampled input signal, while the remaining OR gates (-m + 2 ... n) each have the output of the corresponding Taps of the delay line (31) received, each OR gate still receives the missing signal as an input and the outputs of the OR gate form the incremental signal (FIG. 2). 11. Receiver according to claim 6, characterized by a multi-stage shift register (50) or Delay line for receiving the signal 2, with the clock rate; through a variety of amplifiers (51) with fixed profits, the number of which is 1 greater than the number of stages of the Shift register (50), whereby one of the fixed gain amplifiers, which has a fixed gain (Z _0D ) corresponding to the actual level (/ ₀ ) of the system impulse response, receives signal 2, while the rest of them with an assigned stage of the shift register (50 are connected), the gains (/ _1D, l _{1D...) 0)} are selected dei transmission system impulse response proportional to the actual level (e.g., through summation means (52) for summing the outputs of the gain amplifier (51) for forming the sum of the product signal Y _iD ; by an automatic gain control device (53) arranged in front of the sampling device (32) for adjusting the gain of the received signal in response to an updated signal Z ₀ so as to keep the value of the actual transmission impulse _{response Z 0} at a predetermined level to hold (Fig. 4). i2. Receiver according to Claim 2, characterized by a decision device (58) for receiving the signal y, - from the accumulator device (40) for forming the signal D ₁ -; Directional means (57) for receiving the signal D to form the signal Sgn D ₁ ; Summing devices (54) for receiving the signal y, and for subtracting the signal Z ₀ D ₁ - therefrom to form the error sampling signal Y ₁ ; Detector devices (56) door receiving the signal Y _t to form the signal Sgn V ₁ -; Modulo-2 adder (59) for the multiplication of the signals Sgn D ₁ - and Sgn V ₁ to form a signal (Sgn D ₁ ) ■ (Sgn VJ, which calculates the error between the estimated and actual value of the system impulse response Sgn (/ "- Z ₀ ); a counting device (47) for receiving the displayed error signal and for adding up a count increment in each clock interval to correct the error in accordance with the displayed error signal, the count of the counting device being the signal Z ₀ ; and by multiplier devices (41) for multiplying the signal D _{1 of} the decision device with the counter signal Z ₀ to form the product J ₀ Df, which is fed to the summing device (54) (FIG. 6).