DE2152225B2 - Misfet with at least two insulating layers arranged between the gate electrode and the channel, and a method for its production - Google Patents

Description

The invention relates to a MISFET with at least two arranged between the gate electrode and the channel Insulating layers, with semiconductor material arranged in layers between two insulating layers. she also relates to a method for producing such a MISFET.

From DE-OS 18 03 035 field effect transistors are known whose properties are due to charge storage should be changeable. In e: iner first embodiment there should be trapping points between a SiCv layer and a SiN layer can be produced. The trapping sites arise there uncontrolled and random and should mainly be due to a faulty lattice. You get therefore a low density of traps and therefore long storage times, which is due to the high working speed modern computer is incompatible. - In a second embodiment according to the above DE-OS a thin layer of S1O2 is applied to the channel of the field effect transistor, on top of which a layer which should serve to trap charges, over and over again a thin layer of S1O2 and on top the gate electrode. The layer intended for trapping charges should be made of metal or polycrystalline Consist of silicon. In practice, however, such a layer discharges very quickly, on the one hand over the ambient air with which it is in direct contact and, on the other hand, about inevitable defects (so-called pinholes) in the insulating layers, so that only very short storage times in the order of magnitude of Minutes are possible.

Furthermore, one knows from DE-OS 14 89 107 diodes with a charge storage layer, which consists of a mixture of semiconductor particles with an insulator, z. B. wax, silicone resin, epoxy resin or the like. Is. To introduce a charge, times in the order of magnitude of minutes are required here, what such Diodes e.g. B. makes completely unsuitable for storage purposes.

It is therefore an object of the invention to create a field effect transistor in which the charge traps are reproducible in terms of number and effect.

Based on the MISFET mentioned at the beginning, this object is achieved according to the invention by the im measures specified in the characterizing part of claim 1. The term "cluster" is used here (cf. the literature reference "Atom, Structure of Matter", Leipzig, 1970, page 436) an accumulation or Agglomeration of several particles of semiconductor material to form a larger, coherent one Complex understood. These clusters, which according to the inventor's knowledge act as charge trapping points,

are therefore in the area of the boundary between two adjacent insulating layers, i.e. H. their spatial Arrangement is fixed and essentially two-dimensional and has an essentially constant one Distance from the substrate, naturally, as described below, with several cluster layers different distances from the substrate can be provided. Such a fixed spatial Distribution of the cluster has the great advantage that the charge is approximately uniform and constant Dense in a two-dimensional cluster arrangement is distributed. - Since the clusters are surrounded by insulating layers all around, they can be attached to them Trapped charges do not flow away via the surrounding air, and defects in the insulating layer, so-called pinholes can only influence individual clusters, but not a larger number of them so that very long storage times, on the order of years, can be achieved; H. a inventive MISFET is suitable for. ß. very good as energy-independent storage, but can be used e.g. Belly can be used as a variable threshold voltage FET.

It is particularly advantageous to proceed in such a way that the insulating layers between the clusters include, are at least cluster-poor. So, if possible, there should not be any in the insulating layers Charge traps, so z. B. also no vacancy clusters or interstitial atom clusters are present, so no charges can be captured there; since the occurrence of such accidental arresting stiffeners in If the insulating layers are difficult to control at all, they would make the production more reproducible MISFETs according to the invention at least significantly complicate, and the presence of clusters in These insulating layers would also deteriorate their insulating properties and the leakage of charges facilitate, d. H. the long-term storage properties deteriorate.

The production of the clusters in the area of the boundary between two adjacent insulating layers is according to of the invention possible in various ways, e.g. by chemical vapor deposition as a base serving insulating layer or by vacuum evaporation.

Refinements of the MISFET according to the invention and methods for its production are shown in FIG Characterized subclaims.

For the following description of the exemplary embodiments, the terms according to DIN 41 858 November Used in 1973. Abbreviations include: Use:

FET Field effect transistor MAS Metal-alumina semiconductors MNOS Metal nitride oxide semiconductors MIS Metal-insulating layer semiconductors MNS Metal nitride semiconductors MNCNS Metal-nitride-cluster-nitride-semiconductors MNCOS Metal Nitride Cluster Oxide Semiconductors MNCIS Metal nitride cluster insulating layer semiconductor MINCNOS Metal-Insulating-Nitride-Cluster-Ni trid oxide semiconductor MICONS Metal-insulating-layer-cluster-oxide-Ni trid semiconductors.

In the description, further abbreviations are used which are formed according to the same principle and indicate the basic structure in each case. -

The invention is explained below with reference to the exemplary embodiments shown in the drawing. It shows

F i g. 1 shows a cross section through a MISFET according to the invention,

Fig. 2 eight different embodiments of the gate structure of MISFETs,
F i g. 3 (A) an energy band illustration for the

ίο embodiment according to FIG. 2 (A),

F i g. 3 (B) is an energy band diagram for the embodiment of FIG. 2 B),

F i g. 4 and 5 measured values from an experiment with an MNCNS setup,

6 measured values from an experiment with an MNCNOS structure,

7, 8, 9 measured values from a MISFET, which has the structure according to FIG. 2 (A) used as a gate, and
10 shows the capacitance-voltage family of characteristics of a gate structure according to FIG. 2 (C).

In the following :! Description means insulating layer or insulating coating as a single layer of the insulator, while generically the entire, usually multilayered structure under an insulating coating is understood from insulating layers and semiconductor clusters.

1 shows a cross section through a MISFET with a gate structure according to the invention. This MIS construction consists of a gate electrode 1

So made of metal or doped silicon or germanium, insulating layers 2, 4, clusters 3 made of semiconductor material, a semiconductor substrate 5, which here consists of P-silicon, and a lower electrode 17. The current in of the semiconductor device flows through the line 13, the source zone 14, the one below the gate Channel, the drain zone 16 and the connecting line 15 of the drain. Silicon oxide is used to insulate the connection lines and the substrate, thereby reducing the stray capacitance between them.

F i g. 2 shows various embodiments of the gate structure. The reference symbol denotes in each case 1 a conductor electrode; with 2,4, fi, 8 and 11 will be insulating layers, and with 3 and 7 clusters of semiconductor material. As a conductor electrode are in addition to metals such as aluminum, gold, titanium, platinum, etc. also with impurities from the P or N-type doped, polycrystalline silicon or germanium is used. The clusters shown in FIGS. 2 (A) to 2 (H) are roughly in the shape of

so hemispheres and are made of silicon or germanium manufactured. An electron micrograph reveals that the clusters are compressed as well as Are hemispherical and have diameters in the order of a few nm to 300 nm. the obliquely hatched areas 3 and 7 in Fig. 2 (E) and 2 (F) represent a semiconductor thin film (made of Si or Ge). Due to measurement difficulties, the the exact thickness of the thin film cannot be determined, but it is believed to average im Range from 0.5 to 30 nm.

For the insulating layer 2, which is in close contact with the semiconductor clusters, is either silicon nitride, silicon oxynitride, germanium nitride, silicon oxide, aluminum oxide, or tantalum oxide

b5 titanium oxide is used. Depending on the application a combination of these materials has also been chosen. Generally an oxide produces oxygen, when it is subjected to heat treatment, and

the gas reacts with the clusters and gives them a compressed shape. Because of this, mostly silicon nitride used. Care should be taken that silicon or germanium clusters in the are essentially excluded from layer 2.

In Fig. 2 (A), (C), (D), (E), (F) and (G) is a single layer of silicon oxide, silicon nitride or Germanium nitride-made insulating layer is used under the semiconductor clusters or the semiconductor thin film. In Fig. 2 (B) and (H) multiple layers consisting of the coatings 4 and 11 are used.

In the case of a silicon semiconductor substrate, a silicon oxide coating with a thickness of less than 20 nm, typically between 1 and 5 nm, with an insulating coating made of silicon nitride on top or germanium nitride selected, which coating has a thickness of about 20 nm, typically between 1 and 5 nm, having. In general, a silicon semiconductor easily forms silicon oxide on its surface, and does so the surface stable. However, if the silicon oxide in the heat treatment with the semiconductor clusters reacts, the insulating characteristics, the boundary layer characteristics, etc. deteriorate. To overcome of these troubles, a heat-resistant nitride film 4 on the surface of the silicon oxide 11 becomes "is formed, and then the semiconductor clusters are formed on the nitride film 4.

In Fig. 2 (G) and (H), the insulating layer consists of a nitride coating 2 and another insulating Coating, e.g. B. silicon oxide, doped silicon oxide, or jo a coating with a higher dielectric constant such as tantalum oxide or titanium oxide 8. The nitride coating is formed under the latter coating so that the The insulating layer is monolithic. The thickness of the insulating coating is approximately in the range from 30 to 300 nm, j5 according to the present process technology.

Si or Ge is used as the material for the clusters.

In one embodiment, the clusters of Si are made by silane chemical vapor deposition, vacuum evaporation, or sputtering, and the clusters of Ge are made by vacuum evaporation or pyrolysis of germanium hydrogen. In the case of cluster production by vacuum evaporation, it has been experimentally determined that the surface on which the clusters are to be formed should be kept at a lower temperature without preheating and at about 300 ° C. Also, the chemical vapor deposition with silane in the experimental method was easy compared to the use of a reactive gas such as SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ etc. Provide the cluster with a P or N line. This can change the level in the energy band of the clusters.

F i g. 3 shows energy bands for the structures according to FIG. 2 (A) and (B). In the arrangement according to FIG. 3 (A) a metal gate 1 made of aluminum, a silicon nitride layer 2, cluster 3 made of silicon, a silicon nitride wi layer 4 and a semiconductor substrate 5 are used; this arrangement has the structure MNCNS (metal-nitride-cluster-nitride-substrate). It should be pointed out that the silicon clusters are designed to trap electrons or holes as trapping points, and that bs they have the same ribbon configuration as the silicon substrate.

Fig. 3 (B) corresponds to Fig. 2 (B) and shows a Metal gate 1 made of aluminum, a layer 2 au! Silicon nitride, cluster 3 made of silicon, a layer 4 au; Silicon nitride, a silicon oxide layer 11 and a silicon semiconductor substrate 5, and accordingly has the structure MNCNOS.

If necessary, the semiconductor substrate 5 can au! Germanium, gallium arsenide etc. instead of silicon. Although the band structure is not the same here, the material for layers 2, A should be silicon nitride or germanium nitride, the material for gate 1 should be doped Si or Ge, and that for 3 germanium.

example 1

This relates to FIG. 2 (A). The following «discussion gives the details of making the MNCIS structure and its result. "I" stands for "insulating coating".

A silicon semiconductor with an impurity density of / Vo = I × 10 ¹⁵ cm ⁻³ and a crystal orientation of 100 was used in the experiment. After cleaning the semiconductor substrate, the insulating coatings 2 and 4 were applied by means of solid-state vapor reaction deposition and chemical vapor deposition. The time from 5 seconds to a minute was required for thermal oxidation at 900 to 1100 ° C. In the latter process step, the substrate was placed in either nitrogen or ammonia at 1000 to 1350 ° C. to produce a silicon nitride coating on it. The result was a coating thickness of less than 10 nm at 1150 to 1200 ° C. in 10 minutes to one hour.

A silicon oxide coating with a thickness of less than 20 nm was produced by chemical reaction between Silane at 0.1 ml / min and oxygen from 10 to 500 ml / min with a nitrogen carrier gas at 5 L / min achieved at 200 to 500 ° C.

A Siliziumnitridüberzug was produced in that silane or SiH ₂ Cl ₂ or SiHCl _3, or SiCl ₄ was brought at 500 to 900 ⁰ C for reaction with ammonia or hydrazine. The details are as follows:

Silane or SiH ₂ Cl ₂ :
Ammonia:
Nitrogen carrier gas:

0.2 to 0.4 ml / min
100 to 300 ml / min
2.5 l / min with silicide
0.5 l / min for ammonia
Vertical reaction furnace with reduced nickel oxide as a catalyst to activate the ammonia.

The resulting silicon nitride coating contained no clusters or a negligible amount of Cluster. If less than 100 ppm of oxygen or nitrogen oxide is added to the reaction gas according to the above Process added, resulted in silicon oxide nitride, so an oxide-nitride mixed compound.

Germanium nitride was produced by reacting GeH ₄ or GeCl ₄ with ammonia at 400 to 700 ° C. Germane from 0.2 to 0.4 ml / min was used, with the temperature of the substrate was maintained at the test at 55O ⁰ C. The other data remained the same as when the silicon nitride coating was made.

Chemical vapor deposition using silicon or germanium hydrogen was an effective method for making the clusters, but the use of SiH ₂ Cl _{2 made} it easier to make. In the latter process, a hydrogen carrier gas was used at 0.5 l / min for ammonia and a nitrogen carrier gas at 2.5 l / min _{for SiH 2} Cl _2. A halide of silicon or germanium, e.g. B. silicon tetrachloride, germanium tetrachloride or trichlorosilane can be used in manufacturing, however, silane and germanium hydrogen were chosen because they are easier to process. With these, a gas of silicon or germanium, ammonia or hydrazine, both of which have a smaller gas volume than the former, can be used to increase the cluster deposition. In addition to the above, vacuum evaporation or sputtering can also be used, but for the production of the clusters 3 these require a station which is separate from the station intended for the production of the silicon nitride coating. Otherwise the surface of the clusters will be contaminated or oxidized.

F i g. 4 shows the result obtained with an MNCNS structure which uses a silicon nitride coating by chemical vapor deposition for layer 2 and layer 4. The total thickness of the coating was 125 nm. F i g. 4 is based on the general capacitance-voltage characteristics of the MNCNS structure, as z. B. F i g. 6 shows In FIG. 4 jo, the .v-axis represents the gate voltage or the field strength and the / -axis represents the degree of hysteresis in the form of Δ Ufb (volts), i.e. the voltage difference between the initial flat band voltage Ufb 0 of the capacitance-voltage characteristic and of the flat band voltage Ufb \ after the change in this characteristic curve as a result of the charge injection to the charge trapping points. The F i g. 6 A and 6 B show such characteristics. If positive or negative charges are captured at the clusters 3, or if a positive or negative voltage is applied to the gate connection, the energy band of the semiconductor 5 bends accordingly upwards or downwards at the interface between the insulator 4 or 11 and the semiconductor 5 below. A gate voltage must therefore be applied so that the semiconductor energy band is flat and the injected charges on the clusters 3 are compensated. This tension is called the ribbon tension. So AUfb is the compensation voltage

Ufb \ - Ufbo,

which must be applied to the gate electrode, and ANfb is the amount of compensated charges. The dimension of ANfb is the amount of elementary charges per unit area, so

■ * N _n = ^ j-AUr ₁₁
and

Q = R-AN _n
whereby

</ = Elementary charge (1.602 · 10 " ¹⁹ coulombs), C ₁ = capacitance of the gate insulator per unit area 1-5-).
\ cm V

55

60

b5 The experiments with No. 304 and No. 308 show that when the cluster 3 (denoted by C in FIG. 4) increases in thickness, the hysteresis only increases. The experiments with No. 308 and 309 show that as the insulating layer 4 (denoted by / in Fig. 4) increases, the hysteresis decreases. If the insulating layer 4 is made thinner and the clusters 3 larger, the charge density to be captured is increased. However, if the insulating layer 4 is made too thin, the retention capacity for the trapped charge is weakened.

The in F i g. 4 shows that

4 / V _F ß = 8.2xl0 ¹² cm- ² .

This value is about five times greater than in the case of a conventional MNOS structure, for which applies

ΔΝρβ = \ .. · 2χ 10 ^l2 cm- ² .

F i g. 5 shows the result of an experiment in which the gate voltage was kept constant (U _gmax = ± 50 V, E = ± 4 χ 10 ⁶ V / cm) while AUfb and the precipitation time for the clusters 3 and the insulating coating 4 were changed . When silicon nitride is used for the insulating coating 4, the surface of the silicon substrate underlying the silicon nitride reacts with the oxygen in the air to produce a silicon oxide coating of 0.5 to 2 nm at normal temperature. This oxide coating is removed in ammonia gas at over 1000 ° C in more than 10 minutes, and part of the oxide coating is converted into silicon nitride. The oxide coating, on the other hand, is removed from the silicon substrate with a special cleaning process. If a pure MNS structure is required, the above treatment must be carried out. The oxide thin film which is generated at normal temperatures can be neglected in practice. The so-called natural oxide, as it is here, shows a random thickness profile on the surface of the substrate. For example, the thickness can be 2 nm at one point and 0 nm at another point on the same substrate.

In Figure 5, the silicon nitride coating shows a growth rate of 0.1 to 0.2 nm / sec. The mentioned random thickness should be taken into account at 0 see on the / axis. The point A in FIG. 5 means an NMS diode. The corresponding value of Ufb is 8 V, with ± 4 χ 10 ⁶ V / cm. The hysteresis is very small if the clusters have not been formed by silane precipitation. If the coating 4 (FIG. 2) had been formed as an oxide coating at high temperatures, the hysteresis (Δ Ufb) was less than 1 V at the same field strength for the same thickness.

If silane is precipitated to form the cluster, Δ Ufb increases with increasing time for the precipitation, as is shown in the successive curves 24, 23, 22 and 21 in FIG. 5 emerges. On the other hand, AUfb increases as the thickness of the silicon nitride coating 4 in FIG. 2 (A). When the silicon deposition time was between about 30 and 60 seconds, silicon clusters were formed. Measurements under the electron microscope showed that the diameters of the silicon clusters were between 30 and 150 nm. A silicon thin film was formed when the precipitation time was more than 300 seconds. If the thickness of the deposited film is more than 50 nm, such a film should be called a thick film. - If the average thickness of the downed

Semiconductor film is less than 10 nm, the Cluster generated. When this thickness is between 10 and 50 nm, a semiconductor thin film is formed. Will When the semiconductor thick film is formed in the insulating coating, it is usually used as a silicon floating gate MISFET called. In the formation of the cluster, the introduction of ammonia or hydrazine can be used the same volume as that of the silane gas or with a smaller volume than that of the silane gas Increase the speed of cluster formation.

The silicon clusters are generated when the deposition time is about 300 seconds or more at the same flow rate of silane as in the production condition of the silicon clusters in Fig. 5. (Instead of the term “separation”, the term “precipitation” is used in the following text.)

It is possible to have long storage due to the trapping of the holes or electrons on the clusters reach even if the layer 4 is between the clusters and the substrate 5 or the gate electrode has a number of pinholes or conductive paths.

On the other hand, if there are holes in the layer 4 (Fig. 2 (E)) in the semiconductor thin film 3, they will leak electrons or holes trapped on the thin film to the substrate 5. Therefore, here are the storage properties not particularly favorable for a semiconductor memory.

It has been determined experimentally that when using silicon or germanium clusters, the storage time was more than 2000 hours, but less than 500 hours, e.g. B. only an hour if a semiconductor thin film was used. The result obtained will be the same if the ammonia gas is not added will.

The above experiment proves that the teaching of the present invention is correct. The hysteresis phenomena which in the capacitance-voltage characteristics of the MNCNS structure and the MNCOS structure should not be attributed to the so-called irregularity of the atomic dimensions rather on the clusters which are in the area of the boundary between two neighboring ones Insulating layers are present and which act as trapping points for electrons and holes. So that is a Means at hand, if there is a desire, the size and shape of the hysteresis of the capacitance-voltage characteristic to influence.

Example 2

This relates to FIG. 2 (B), which has a MNCIil2S structure, where Ii and I2 mean the insulating layer 4 and the insulating layer 11, respectively. The material and the method for the semiconductor substrate, the insulating coating, the clusters and the gate conductor are the same as in Example 1. The structure of Fig. 2 (B) brings the peculiarity of locally forming a silicon oxide coating at normal temperature. This type of oxide coating reacts, when the heat treatment is performed for the semiconductor clusters at above 500 ⁰ C in one hour, as was previously described. For this reason, it is extremely desirable to surround the semiconductor clusters with a layer of silicon nitride or germanium nitride.

This is done by the MNCOS or the MNCNS structure according to example 1 in one MNCNOS structure is converted. F i g. 2 (H) shows a MINCNOS structure, i.e. an improved version of the MNCNOS, with an insulating coating of tantalum oxide or titanium oxide 8 with greater specific Dielectric constant is applied to the nitride coating 2 formed on the MNCNOS structure was, d. H. on the clusters. The MINCNOS structure has a thin electrical coating and a thick physical coating and thus protects against mechanical stresses on the Gate portion of the semiconductor device are exercised. In addition, the clusters can be in multiple layers (Fi g. 2 D) are designed to increase their effectiveness. This is a further training of the Invention.

After the complete cleaning of the silicon semiconductor, which has an impurity density of / Vo = I χ 10 ¹⁵ · cm ^-3 and the crystal orientation 100, a silicon oxide coating 11 was formed by solid-vapor reaction in dry oxygen for 100 seconds at 1000 ^° C generated. A silicon nitride coating 4 was then produced by chemical vapor deposition using silane and ammonia in 15 seconds. The experiment also tested S1H2CI2 and SiCU and the results were the same. The clusters were created by a silane precipitation process in 300 seconds. It in turn a Siliziumnitridüberzug 2 was formed by 120 nm on the clusters, wherein the temperature of the substrate was maintained at 650 to 75O ⁰ C.

Finally, an MNCNOS assembly was completed by vacuum evaporation Aluminum electrode 1 was applied to the above arrangement.

AVFB increases with increasing thickness

j5 nitride layer 4 added oxide layer 11 and it increases with increasing precipitation time of silane; the relationships thus correspond to those of FIG. 5.

The F i g. 6 (A) and (B) show the capacitance-voltage characteristics, as they turned out in the attempt.

The ordinate axis indicates the specific capacitance between the gate electrode and substrate in pF / mm 0, the abscissa axis the gate voltage U _g in volts. Δ Vfb increases proportionally to V _gmax (maximum applied gate voltage in V). 6 shows no hysteresis characteristic when V _{gmax is} less than 50V. The critical stress of the test sample according to FIG. 6 is 50 V and the hysteresis, Δ Vfb, increases with the increment of the maximum gate voltage V _gmäx . A capacitance-voltage curve without hysteresis is in

5 »Figure 6 (A); this figure shows that the interface properties between the substrate 5 and the insulator 11, 4 represent an ideal characteristic for a MISFET gate, because the fixed states and the fixed charge Q ₅₁ Zq ₁ which exist at the interface are almost equal to zero. Therefore, a practically mandatory prerequisite for the production of the present structure is the technology for the production of a low-cluster or cluster-free silicon or germanium nitride coating.

The present example shows that it is possible to determine the degree of hysteresis in capacitance-voltage characteristics to influence by changing the manufacturing conditions, e.g. B. the rate of precipitation or precipitation time of a silicide gas, the mixing ratio between the small amount Ammonia or hydrazine, and the distance between the clusters and the substrate 5. It is also possible to influence the degree of hysteresis in that

the precipitation temperature of the silicide gas is changed above 750 ° C or below 650 ° C.

The energy band of Example 2 is shown in FIG. 3 (B), the designations being those of F i g. 2 (B).

Example 3

This example describes the characteristics of a MISFET whose gate consists of the structure as they is shown in Fig. 2 (A). The example uses an N-channel and its basic structure is in Fig. 1 shown; here is the distance between the Source zone 14 and drain zone 16, the so-called channel length, 30 μm, and each gate has a length of 1000 μm.

The substrate is P-type, crystal orientation 100, and its resistivity is 3 to 5 ohm · cm. The F i g. 7 to 9 show the result of this experiment. The gate insulator, corresponding to the silicon nitride layer 2 in FIG. 2, is about 60 to 70 nm thick. This is about half the value according to Examples 1 and 2. The thickness of this layer can be changed depending on the particular use. If a MISFET with P-channel is desired, an N-conductive substrate should be used together with a P ⁺ source and drain zone.

In Fig. 7 the x-axis represents the gate voltage U _g and the y-axis the drain current Id- The drain voltage was kept at a constant value of 100 mV. The iTg-Z / T characteristic remains the same, while the threshold voltage Uto changes from +10 V to - 10 V. The slope of the curve shows that the mobility of the carrier in the canal is 400 cm ² / V ■ see.

The facts resulting from the above experiment lead to a negation of the previously in the Semiconductor technology adopted concept that with high surface states at the interface the Carrier mobility in the channel is low and that with decreasing surface conditions the Carrier mobility at the interface approximates the mobility of the internal carrier.

If a positive or a negative gate voltage is added to the initial threshold voltage of £ / ro = + 2V, the data of the LJg-IO characteristics remain the same if the gate voltage is less than the critical voltage IJ ₀ . If the gate voltage is above the critical voltage, the data shift in the direction of the applied voltage. In the present example, the critical voltage was ± 23 to 25 V.

The indices 1 to 9 in FIG. 7 (the indices are surrounded by circles) show the sequence of the highest gate voltage applied (U _gmax ). With U _g = Q \ and flowing h one obtains the characteristics with the indices 6 and 8; this is the ON state. With £ ^ = 0 V without h , the characteristic curves with the indices 7 and 9 are obtained; this is the switched-off state (OFF). It can be seen from the characteristics that the transition from ON to OFF and from OFF to ON can be repeated so that the MISFET can be used as a random access memory.

FIG. 8 shows the i / cr / o family of characteristics corresponding to index 9 of FIG. 7 with a maximum gate voltage of +40 V. FIG. 8 shows that / o> 0 with Ug> 10 V and I _D = 0 with U _g <+ 10 V. The latter means

• j the switched-off state (OFF).

F i g. 9 shows the LO-Zo family of characteristics corresponding to index 8 in FIG. 7, where the maximum gate voltage is -40 V. This figure shows that / o> 0 with Ug = O and Id = O with U _g < -10 V. The former means the

ίο switched on state (ON).

Example 4

This example describes the structure according to FIG. 2 (C). In the example according to FIG. 2 (A) are the

;: Cluster on the side of the substrate 5; In the present example 4, however, they are on the side of the gate electrode 1. Here, only electrons are present as carriers, and the resulting semiconductor device is then a read-only memory and therefore a less flexible memory device, since there are no "holes" in the Semiconductor devices can be provided which cancel the electrons to be captured.
For the production of the coating 2 only the chemical vapor deposition process can be used, unlike for the

Coating 4. As the coating 2, silicon nitride is formed with a thickness of 1 to 10 nm. He helps create a To prevent external contamination.

The results of the trials were all symmetrical.

jo Fig. 10 ^ shows the influence of increasing thickness of the Layer 2 in Fig. 2 (C). The family of characteristics is similar to that according to FIG. 2 (A) as the thickness of the Layer 4 there. The reference symbols in FIG. 10 have the following meanings

Reference number

Layer thickness (nm)

1.5

2.5

5.0

20.0

The data at U _g = ± \ Q0W were 120 V for AUfb- To increase the charge to be injected, the distance to an injection source, i.e. the distance between the gate electrode 1 and the clusters 7, should be shortened. The trend is similar to the data from Example 1, FIG. 5. The experiment proved that the clusters, ζ. B. the clusters 7 according to FIG. 2 (C), a high one

so yield of usable MISFET, e.g. B. to Manufacture of ROMs or RMMs. As described in Example 1, it is desirable that the Silicide gas a small amount of gaseous nitride, e.g. B. ammonia, when the semiconductor clusters can be generated to obtain a long storage time.

In FIG. 2, the arrangements (E) and (F) represent mixed types in which, in addition to a cluster layer a semiconductor thin film is also used. at

bo F i g. 2 (D) become two cluster layers 3 and 7 uses what is a combination of (A) and (C) to double the respective function.

In addition 6 sheets of drawings

Claims (13)

Patent claims: 1. MISFET with at least two insulating layers arranged between the gate electrode and the channel, wherein between two insulating layers semiconductor material is arranged in a layered manner, d a through characterized in that the semiconductor material is in the form of clusters (3; 7) of silicon or germanium is present that this cluster is in the ι ο area of the boundary between two neighboring ones Insulating layers (2, 4, 6) are arranged, and that these clusters (3; 7) from the insulating layers are surrounded. 2. MISFET according to claim I _1, characterized in that clusters (3; 7) are arranged in the region of the boundaries between a plurality of mutually adjacent insulating layers (2,4,6). 3. MISFET according to claim 1 or 2, characterized in that the clusters (3; 7) have approximately the shape of compressed hemispheres have a diameter in the range of about 1 to 300 nm and have an average thickness of less than 10 nm. 4. MISFET according to one of the preceding claims, characterized in that the semiconductor material the cluster (3; 7) is doped with an impurity, which is a P line or a N line results. 5. MISFET according to one of the preceding claims, characterized in that the layered clusters (7) a distance of less than 20 nm from the gate electrode (1) exhibit. 6. MISFET according to claim 5, characterized in that the distance is 1 to 10 nm. 7. MISFET according to one of the preceding claims, characterized in that the insulating layers (2,4,6), which enclose the clusters (3; 7) between them, are at least cluster-poor. 8. MISFET according to one of the preceding claims, characterized in that the insulating layer has the following structure: a) an at least low-cluster insulating layer (4) formed on a semiconductor substrate (5) from single-layer silicon oxide, silicon nitride or germanium nitride, or from a multilayer Structure (4, 11) made of silicon oxide and / or silicon nitride, b) clusters (3) formed on the insulating layer, c) an insulating layer (2, 6) made of silicon nitride and formed on the clusters, at least with few clusters, Silicon oxynitride or germanium nitride, and d) an insulating layer (8) made of silicon oxide, tantalum? s oxide or titanium oxide. 9. A method for producing an MISFET according to any one of the preceding claims, characterized in that characterized in that the clusters by chemical vapor deposition of the insulating t> o layer can be produced. 10. A method for producing a MISFET according to any one of claims 1 to 8, characterized in that that the clusters on the insulating layer serving as a base are produced by vacuum evaporation. 5 will be presented. " 11. The method according to claim 9, characterized in that that for the production of the clusters a silicide gas or a gaseous germanium compound is used with ammonia or hydrazine in a volume ratio of 1: 1 or less. 12. The method according to claim 11, characterized in that the silicide gas is silane, dichlorosilaii, Trichlorosilane or silicon tetrachloride is used. 13. The method according to claim 11, characterized characterized that the gaseous germanium compound germanium hydrogen or germanium chloride is used.