DE2123998A1 - Pulse generator with an ultrasonic delay line - Google Patents

Description

Pulse generator with an ultrasonic delay line is known oscillators with high frequency accuracy and constancy can be produced if an ultrasonic delay line is used as the frequency-determining element will. E.g. the output of such a line is sent via an amplifier to the Input fed back that impulses arise, each with some oscillations the center pass frequency of the delay line and are contained. at a distance repeat the running time of the delay line.

In a proposed circuit (P 1964 287.6), such a circuit is used Oscillator in television technology as a start-stop oscillator for generating short-term Color carrier oscillations or as a standard oscillator for a heterodyne receiver with grid voting. One makes use of the fact that the repetition period is very constant.

In the latter case, however, one would like each time instead of an impulse with multiple oscillations have only a single pulse edge or a needle pulse. Often it is also desirable that this pulse edge only appears every second the said pulses repeated, so that the frequency of the pulse train halved will. This is currently expedient to have a reception grid for a radio receiver with 9 kHz pitch frequency from a generator with a delay line to generate the first a pulse train with a Frequency of 18 kHz generated. For a pulse generator that oscillates with a repetition frequency of 18 kHz, namely, an ultrasonic delay line with a transit time of 55.6 As use the one from a PAL ultrasonic delay solution by grinding can create.

The invention is based on the object of creating a circuit with the pulse sequence described above, a voltage with halved Basic frequency and only one flank instead of the aforementioned multiple oscillations is produced.

This object is achieved by the invention described in claim 1 solved. Further developments of the invention are given in the subclaims.

In the invention, the properties of a D flip-flop are more advantageous Way used to solve this problem.

Such components are cheaply available in integrated circuit technology. In one embodiment of the invention, only one is used as the peripheral component RC element f ## required.

Instead of the D flip-flop, another flip-flop can be used, when it is operated like a D flip-flop. The accuracy of the time constant RC is only made a minor requirement because the reversal of the logical Condition can take place within a relatively long period of time.

The invention is explained below with reference to the drawing.

FIG. 1 shows a circuit diagram of the invention and FIG. 2 shows curves to explain how it works.

The capital letters indicate at which points in Figure 1 the stresses stand according to Figure 2.

In FIG. 1, a generator 1 is used as the frequency-determining element an ultrasonic delay line 2 contains a voltage composed of pulses 3 with several oscillations 4 each. The pulses 3 are repeated with the Running time To of line 2, which is very constant. The frequency of the vibrations 4 is equal to the center pass frequency of line 2, which is essentially through the converter is intended.

The pulse train 3 is a D flip-flop 5 at a clock input T. fed. The flip-flop 5 has two outputs Q and Q.

According to the invention, the output Q is via an RC element 6.7 with the condition input D connected. The mode of operation is explained with reference to FIG.

It is assumed that the flip-flop output Q is in the logic state 0 and correspondingly Q is in the logic state 1, so that the input thereby the voltage shown at D in Figure 2, which by integration the voltage at output Q, represents the logic state 1. At the time t1 when the first edge of the oscillations 4 of the pulse 3 has a certain value reached at clock input T, output Q is knocked over to Q = D = 1 and accordingly Q goes to 0, while the voltage at input D is above the voltage value 10 there initially maintains the logical state 1. In the following bars through the flanks of the oscillations 4 at times t2, t3, # t4 are not overturned of the flip-flop 5, because the input D represents the logic state 1, accordingly a pulse at input T at output Q can only cause state 1 and Q already has the state 1. Therefore, at output Q, the illustrated pulse 8 occurs with only a rising edge 9. At time A after the end of the pulse 3 falls below the voltage at input D has the value 10, whereby D assumes the logic state 0.

On the first edge of the next clock pulse 3 'at time t1' therefore the flip-flop is knocked over again (to Q = D-0), so that now a falling Edge 11 in the pulse 8 at output Q occurs. Only at time point B does it change due to the integration effect of the RC element 6.7, the logic state at D again to the value 1, so that with the next pulse 311 the process like begins at time t1.

It can be seen that from each pulse 3, which in itself consists of several Oscillations 4 exist, a single flank 9, 11 is generated and also the repetition frequency the pulse train 3 is halved. Since the pulse duration t4-tt of a pulse 3 is essential is less than the period To = t1'-tl, the time constant of the element can 6.7 can be chosen with a large allowable margin so that the point in time A after t4 and before t1, and time B is after t4 'and before tl' '.

Claims (2)

Claims pulse generator with an ultrasonic delay line as the frequency-determining one Element in which, at the interval To of the delay time, pulses from several oscillations with the center pass frequency of the line, characterized by the following features: a) The pulse train (3) is at the clock input T of a D flip-flop (5) is applied, the logic state of which is controlled at the condition input D. b) The D negating output Q of the flip-flop (5) is like that with the condition input D connected that the logic state at this input during the oscillations (4) each pulse (3) remains the same and each time (ate) between two consecutive pulses (3,3 ') changes. 2. Generator according to claim 1, characterized in that the output Q is connected to the condition input D via an RC element (6,7). L e r s e i t e