DE2122592B1 - Circuit for compensating for timing errors in a television signal - Google Patents

Description

constant clock frequency. The voltages from the multiplier 10 and the generator 11 are mixed in a mixer 14. The voltage contained in this mixed product with the frequency η {fa - Af) is converted in a generator 15 into the pulse train 8 with this frequency. It can be seen that the time error Af in the signal 3 with the opposite sign in the pulse train 8 becomes effective. If the line frequency of the signal 3 is too high, ie too short a line duration, the effective running time of the circuit 4 is reduced by the correspondingly reduced frequency of the pulse train 8, ie the signal is brought back to the correct frequency, ie is stretched to the correct line duration.

If the line frequency of the signal 3, -d. H. line duration too long, the frequency of the pulse train 8 is increased, the effective running time of the Circuit 4 is reduced and the signal is gathered to the correct line duration. Correspondingly, there will be time errors

o Other kind of balanced.

1 sheet of drawings

GOPY

Claims (8)

1 2 time electronically increased, so that the signal is stretched to the claims: correct line duration. The electronic delay lines exist z. B. from delay 1. Circuit to compensate for timing errors in circuits with inductors and capacitance diodes, a television signal, in which the running time of an electronically controllable circuit of the last delay device by a time error is based on the object of the invention To create a way in which the new electronic representational manipulated variable is controlled, so that components are used,
characterized in that as a delay This object is achieved by the device in claim 1 an electronic, clocked memory io described invention. Further developments of the invention (4) with a large number of storage elements are specified in the subclaims, and that the cycle is influenced by the manipulated variable. In the invention, therefore, as a controllable 2. A circuit according to claim 1, characterized in that the delay device is characterized by an electronic memory in that the clock is used by a clock pulse and the sequence (8) represented by the memory is determined, which corresponds to the setting time of the signal by a time error ent size is frequency modulated. Talking frequency modulation of the clock pulse train 3. Circuit according to claim 2, characterized thereby controlled. A bucket is preferably drawn as a reservoir, that the clock pulse train used by comparison daisy chain. This circuit can e.g. B. one taken from the television signal (3) a basic transit time of one line, several lines periodic voltage (16) with a in a 20 or fraction of a line and around this Generator (11) generated voltage of constant basic running time around according to the time error Frequency is obtained. being controlled. The invention is therefore for I 4. A circuit according to claim 3, characterized in that the electronic memory known per se is characterized in that a first special, the bucket chain circuit, a new on-voltage with which by a time error Af against 25 reversed area is tapped from the television signal. from the target line frequency fs frequency adulterated The invention will in the following with reference to the frequency f _H + Af derived and illustrated by Verviel- drawing of a block diagram,
In the figure comes from a recording device 1, quenz η · (/ # + Af) is implemented and that by z. B. an optical disc recorder, a line 2 mixes this second voltage with a video signal 3, the line duration of which is subject to fluctuations in the third voltage at the frequency 2 «· fs . This signal is fed to a bucket-chain clock pulse sequence with the frequency η ■ (fu - Af) circuit 4, the mode of operation of which is obtained by symbols. lisch through a variety of capacitors 5 and 5. A circuit according to claim 1, characterized in that electronic switches 6 are shown. One shows that the memory (4) has a basic delay time 35, terminal 7, the corrected video signal ent of one or η line durations. took. The switches 6 are activated by a clock 6. A circuit according to claim 1, characterized in that the pulse sequence 8 is actuated in such a way that it records in time, that the memory (6) a bucket chain- following sections of the signal 3 each from one circuit is. Capacitor 5 to the next capacitor 5 7. A circuit according to claim 1, characterized by 40 being switched on and the circuit 4 after indicates that the manipulated variable by time or a running time of one line at a terminal 7 Leave phase comparison of taken from the signal again. So periodic pulses with pulses of constant The pulse sequence 8 effected at a correct λ Frequency is obtained. Line duration of the signal 3 a delay of the ™ 8. A circuit according to claim 1, characterized in 45 signal 3 in memory 4 by a line duration. if indicates that several memories are connected in series, the line duration of signal 3 is too short, so will are. the frequency of the pulse train 8 is automatically lower. This means that the signal is switched on between the capacitors 5 is slowed down, the running time represented by 50, the circuit 4 is increased and thus In a television signal, which over a difficult line duration of the signal 3 to the correct value Transmission path from a tape recorder is stretched. If the line duration of the device or an optical disc is known to signal 3, the frequency of the pulse train 8 is increased, due to errors in the transmission path or speed, the transit time represented by circuit 4 Fluctuations in the recording medium time and the signal on the correct line duration 3 errors occur by z. B. the real line duration gathered, deviates from the target line duration. This modulation of the frequency of the pulse train 8 In order to compensate for such time errors, a large number is achieved as follows: Known from the circuit at the Leivon. In a known circuit 2 standing signal 3 is in a separation stage 9 device (German patent specification 1 014 153) one of 60 is a line sync pulse sequence 16 with the periodic pulse sequence taken from the signal, error Af compared to the target line frequency fs delayed. B. of line frequency, which the time error falsified frequency fn + Af obtained and included, compared with a constant clock pulse sequence in closing in a frequency multiplier 10 on one of the phase and from this a manipulated variable increased by the factor η increased frequency of the time error obtained. This manipulated variable 65 is also provided with a clock generator 11 which controls the transit time of a transit time line located in the signal path via a line 12 for controlling the electronically controllable delay line. In a device 1 is used and also on a line 13 a signal with too short a line duration is z. B. the running voltage with the frequency 2 · η · fH, so one