DE2121938A1 - Readout memory, especially for code conversion systems and the like - Google Patents

Description

üipL-Ing. Amthor

pipl .-! ng. wolf

6 Frankfurt a M.

Middle way 12

Company AGES Sep.A. - Azienda Generale Elettronica Servomeceanismi Via Castelletto - B 0 B G 0 TICINO (Prov.Novara) - Italy

Readout memory, especially for code conversion systems and the like.

The present invention relates to a readout memory

t ■ -

which is particularly suitable for code conversion systems and the like

It iot known to be code conversion systems or conversion systems a preceding Iblge of code operations on logical blocks are summarized | in those of a certain input configuration an upstream output configuration corresponds to »

Both conversion problems as well as other similar problems can be can thus be attributed to the use of a device that Read-out memory or postage value memory (read-only memory), which

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will"

is called because it is not possible (and neither does it require it will), change the content electrically

If one only considers binary elements, which by the way are the only interesting elements, and if Ii are the so-called "input ^{bits 11} and k are the" output bits ", then and the possible input configurations 2 and each of them correspond to k bits at the output, so that the" Capacity "of the memory is 2 .k bits, ie that 2 .k are the possible cells in which a binary value can be stored ·

The following can be mentioned among the storage systems used

1) - Dicden memory

2) - built-in memory

3) - magnetic storage of various types

The criteria for estimating these stores are very many, the most important however consider the following

a) the costs *

b) the space required

o) the adaptability to different programs d) the speed

The first-mentioned memories, i.e. the diode memories, are expensive and take up a lot of space, although they are very adaptable and are fast, and are particularly suitable for small capacities. . -.

The second-mentioned memories, which are obtained from integrated circuits of great complexity (LSI - large scale integration), especially those of the so-called KOS (metal oxide semiconductors) type

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Bind inexpensive, take up little space, are fast enough, however Little adaptable by doing difficult and costly jobs are necessary in order to make them according to the rules of the Ver_ need to succeed.

The memories of the last-mentioned type, that is to say the magnetic memories, are quite inexpensive, take up relatively little space and are h. some versions very adaptable and fast enough, but their programming requires a long, careful manual work that is subject to errors. This memory is suitable for large capacities.

Dor memory according to the invention aims at combining the advantages of the solutions set forth previously summarized, in particular from the point of a typical consumer, the automatic control technology and the peripheral data transmission and processing, which is therefore interested in a read only memory having the following features t

- low cost

- massive plateau demand

- High adaptability along with a safe and economical manufacturing method suitable for both small and large grosso. Series is suitable

- not too high speed.

The axial se according to the invention is rather characterized by that it consists of at least one printed circuit, the first Comprises a part with components and a second part without components, these two parts together via at least one capacitive Coupling coupled bind.

The memory advantageously consists of a first and a first second printing circuit, which are arranged to match one another

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and each represent one of the parts mentioned, these two circuits being separated from one another by an insulating layer Bind, which extends over at least part of its area!

Further details of the invention can be found in the following individual description of an Ausiese memory, which is shown, for example, in two possible embodiments in the accompanying drawing, in which:

the Fig. 1 represents the memory, the two pressure scarf do * - genes are shown separately next to each other, and Fig. 2 is a variant of the second print circuit *

For the sake of simplicity, the example refers to the Case that there are only 4 "input bits" and 4 "output bits", i.e. with a capacity of 64 bits (Fig. 1).

. According to one known in the addressing of magnetic memories A first decoding of the addresses is carried out during the first term and it v / ground 4 + 4 access circuits to the memory prepare ^ the practical produced by the type 1 and type 2 transistors of FIG Bind

These are arranged on a first press circuit, on which also 16 · .. parallel conductive strips 3 are made so that the circles ir. with the transistors 1 and 2 in pairs each one of the 16 Strip "3 of the printed circuit, which contains the entire circuit, determine. .

The diodes 4 serve as reverse current prevention isolators and are used in all addressing processes. Resistance 5 are not used to generate a current, as is the case in all addressing processes Is common, but a tension front after following procedure!

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Type 1 and Type 2 transistors are usually saturated / When using two-phase timing, the selected transistor becomes type 1 locked at the moment Tl. After failure of the effect of the positive voltage front generated at the collector, the is transmitted through the capacities of the diodes 4 to the strips 3, the selected transistor of type 2 is blocked at instant T2. Only the strip 3 connecting the two selected transistors can be positively charged.

A second print circuit 6 is arranged above the print circuit described so far, which fits together with the first and is separated from it by a thin insulating layer. On this circuit 6 , small areas 7 are formed which lie opposite the strips 3 and are arranged where a "1" is to be written.

On the selected line lines δ is thus through the small Areas 7 induces a charge that is transferred from these lines to the small areas 9, which wildly transfers this charge to the small areas Induce areas 10 connected to the sense amplifiers. These create a positive impulse at the output produces the required code on the four output lines. "More precisely In other words, you get a lower value on the unselected lines Pulse 12, which is due to the small capacities between the chosen Strip 3 and the line lines 8 and other undesirable Couplings arise. This pulse 12 can, however, be separated from the usable pulse 11 in an appropriate amount.

There are also mechanical pressure elements that support the two Hold printed circuits together and also provided shielding elements on both sides to protect the whole thing from external disturbances to make independent.

The advantages of the system are now clearly visible.

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The addressing is just as complex as with a magnetic memory, however, it is obtained with lower current values, in particular in the case of medium and low speeds also the * Dimensions are limited. In a typical embodiment, have the strips have a width of 0.6 mm and the surfaces 7 an area of 0.6 χ 10 mm

With an opposite hole of 6 mm, an insulation

The output has a layer of 0.1 mm and a supply voltage of 20 V. a greater performance than a magnetic core that is normally used for ■ Type of memory used.

Most of the memory remains the same for a particular facility and is already connected to the other circuits. The programming is carried out simply by replacing the pressure circuit 6, which has no components and is therefore very inexpensive. The replacement is particularly easy to carry out due to the small areas 9 and 10, which transmit the signal to the main pressure circuit without connections. The areas 9 and 10 can be made sufficiently larger than the areas 7 so that they do not cause any weakening of the signal. As an extreme case of large capacity, the insulating layer between the faces 9 and 10 can be omitted, a direct contact being obtained which does not have to be perfect and therefore does not cause any problems. The improvement of FIG. 2 is provided for high densities and capacities. In order to write the "ones" and "zeros", instead of the presence or absence of areas 7, areas 7 are provided for the "ones" and areas 7a for the "zeros ^11. The areas 7 and 7a are provided with two line lines 8 and 8a, respectively, which lead to a differential amplifier In this way the effect of the undesired pulses 12 of Fig. 1 is completely eliminated and the whole is made independent of the tolerances of the voltage values and the components.

The memory according to the invention combines all of the aforementioned

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Characteristics, i.e. the cost, the space required, the adaptability fcei of the programming and. the speed * and is particular suitable for medium capacities (in the range of 1000 bits), as encountered in the problems of Co & e conversion.

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Claims (6)

ΡΑΤΕΒΪΑδSPEUECHE / i «) Auslesespeichex, especially for code conversion systems and the like, thereby characterized in that it consists of at least one printing circuit (3,6) which has a first part with components (1,2,4 »5) uM comprises a second part (6) without components, these two the parts are coupled together via at least one capacitive coupling. - -. '.' "" ' 2. Readout memory according to claim 1, characterized in that it from a first and a second pressure circuit (3 and 4, respectively), the are arranged on top of each other and matching and each one of the represent these parts, with these two peelings are separated from each other by an insulation layer, which extends over at least part of their curses 3 · read-out memory according to claim. 1 or 2j, characterized in that the first printing circuit atral conductive strips (3) in one H
Number which is 2 for a binary system, where Ji are the so-called "input bits", and has a plurality of first current-conducting surfaces (10) in a number equal to the "output bits", which are connected to read attenuators. 4 · read-out memory according to one of the preceding claims, daduroh characterized in that the second pressure circuit (6) second stroralaitende Has surfaces (7) which are arranged according to a predetermined system for the purpose of being fitted with the strips (3) and are combined in groups in a number equal to the "output 3 bits", the areas (7) of each of these groups being electrically connected to one another and connected to a further conductive surface (9), 109848/1736
. ■ ■. BATH ORIGINAL 2121838 and each of these further conductive surfaces (9) one of the mentioned first surfaces (10) corresponds to the first printing circuit. 5 · Readout memory according to Claims 1 to 4 »characterized in that that he has a first capacitive coupling between the strip (3) and the second surfaces (7) and a second capacitive or coupling created by direct contact between these further Curses (9) and these first surfaces (10) '. 6. Read-out memory naph the preceding claims, characterized in that the first printing circuit ala addressing part is fixed and, if the programming is changed, for a specific one Setup remains the same, with the second printing circuit (6) is designed in each case as a function of this programming. 7. Read-out memory according to the preceding claims, characterized in that the second printing circuit (6) has first areas (7) for displaying the "ones ^11" and second areas (7a) for displaying the "zeros", the first areas (7) are connected to a first conduction line (8) and these second surfaces (7a) are connected to a second conduction line (8a), which conduction lines lead to a differential amplifier or the like *. .- .: ^ 098 4 8/1 736 L e r s e i t e