DE212021000403U1 - Electronic device, housing and semiconductor chip therefor - Google Patents

Abstract

Electronic device (1) comprising:
- A semiconductor chip (2) with a semiconductor body (22) and an electrical contact metallization (3), and
- A housing (4) with an electrical contact disc (5), wherein
- The electrical contact metallization (3) and the electrical contact disk (5) are in direct contact on a contact surface (45), so that the semiconductor chip (2) is electrically connected to the housing (4), and
- The electrical contact metallization (3) on the contact surface (45) comprises a geometric structure (6) which is designed as at least one recessed area, and
- the electrical contact metallization (3) is of a multilayer type and comprises at least one discontinuous sublayer (33) and at least one continuous sublayer (34), the continuous sublayer (34) is located directly on the semiconductor body (22) and has a thickness (T6 ) of the continuous sub-layer (34) exceeds a thickness of the discontinuous sub-layer (33) by at least a factor of five.

Description

An electronic device is provided. Furthermore, a housing and a semiconductor chip for such an electronic device are also provided.

The document U.S. 2013/0207157 A1 refers to a single wafer reverse conducting power semiconductor device, the device including multiple diode cells and multiple IGCT cells.

A problem to be solved is to provide an electronic device that can be electrically connected in a reliable manner.

This aim is achieved inter alia by an electronic device, by a package and by a semiconductor chip as defined in the independent claims. Preferred further developments form the subject matter of the dependent claims.

For example, the electronic device has geometric patterning on a contact surface to compensate for different sizes of electrodes configured to be pressed against each other to achieve dry electrical contact. By compensating for the different sizes, a contact pressure can be approximately the same for all respective electrodes. The contact area is, for example, an electrical contact area such that the electrical device is configured to be supplied with current through the contact area.

• - einen Halbleiterchip mit einer elektrischen Kontaktmetallisierung, und
• - ein Gehäuse mit einer elektrischen Kontaktscheibe, wobei
• - sich die elektrische Kontaktmetallisierung und die elektrische Kontaktscheibe in direktem Kontakt auf einer Kontaktfläche befinden, so dass der Halbleiterchip elektrisch mit dem Gehäuse verbunden ist, und
• - die elektrische Kontaktmetallisierung und/oder die elektrische Kontaktscheibe eine geometrische Strukturierung, die als wenigstens ein vertiefter Bereich ausgebildet ist, an der Kontaktfläche umfasst.

In at least one embodiment, the electronic device includes:

• - a semiconductor chip with an electrical contact metallization, and
• - A housing with an electrical contact disc, wherein
• - the electrical contact metallization and the electrical contact disk are in direct contact on a contact surface, so that the semiconductor chip is electrically connected to the housing, and
• - The electrical contact metallization and/or the electrical contact disk includes a geometric structure, which is designed as at least one recessed area, on the contact surface.

• - einen Halbleiterkörper, auf den eine elektrische Kontaktmetallisierung und eine weitere elektrische Kontaktmetallisierung auf einer weiteren Kontaktfläche gegenüber der elektrischen Kontaktmetallisierung aufgebracht ist, und
• - ein Gehäuse mit einer elektrischen Kontaktscheibe,

wobei

• - sich die elektrische Kontaktmetallisierung und die elektrische Kontaktscheibe in direktem Kontakt auf einer Kontaktfläche befinden, so dass der Halbleiterkörper elektrisch mit dem Gehäuse verbunden ist,
• - die elektrische Kontaktmetallisierung und/oder die elektrische Kontaktscheibe eine geometrische Strukturierung, die als wenigstens ein vertiefter Bereich ausgebildet ist, an der gesamten Kontaktfläche umfasst, wobei sich die geometrische Strukturierung über der gesamten Kontaktfläche erstreckt, und
• - eine mittlere Breite geometrischen Strukturierung um wenigstens einen Faktor von zwei kleiner als eine strukturelle Größe der weiteren elektrischen Kontaktmetallisierung ist.

In at least one embodiment, the electronic device includes:

• - a semiconductor body to which an electrical contact metallization and a further electrical contact metallization is applied on a further contact surface opposite the electrical contact metallization, and
• - a housing with an electrical contact disc,

whereby

• - the electrical contact metallization and the electrical contact disk are in direct contact on a contact surface, so that the semiconductor body is electrically connected to the housing,
• - the electrical contact metallization and/or the electrical contact disk comprises a geometric structure, which is designed as at least one recessed area, on the entire contact surface, the geometric structure extending over the entire contact surface, and
• - An average width of the geometric structuring is smaller by at least a factor of two than a structural size of the further electrical contact metallization.

Accordingly, it is possible according to at least one embodiment for the geometry to have a smaller periodicity or lateral characteristic length than the further electrical contact metallization when viewed in a plan view of the respective metallization. The average width of the at least one depressed area is smaller, for example by at least a factor of five or by at least a factor of ten, than the structural size of the further electrical contact metallization, for example along the same direction. The periodicity or lateral characteristic length refers, for example, to a direction perpendicular to a length direction of the indentations forming the at least one indented region. By means of such a configuration, the features of the geometric structuring can be considered to be distributed homogeneously on a scale of the structural size of the further electrical contact metallization, so that an exact relative position between the electrical contact metallization and the further electrical contact metallization can become quite uncritical.

According to at least one embodiment, the semiconductor chip is selected from the group consisting of a diode, a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), an insulated gate bipolar transistor (IGBT), a bipolar transistor (BJT), a thyristor, a gate turnoff thyristor (GTO), a gate commutated thyristor (GCT) and a junction field effect transistor (JFET).

For example, the semiconductor chip is an integrated gate commutated thyristor (IGCT) or an IGCT with an embedded anti-parallel diode.

For example, the semiconductor chip and accordingly the electronic device is configured to handle a maximum current of at least 50 A, or at least 0.5 kA, or at least 5 kA. Accordingly, the semiconductor chip and the electronic device can be high-performance components.

For example, the semiconductor chip includes a semiconductor body. The semiconductor body can consist of one or more semiconductor materials. When viewed in a plan view, the semiconductor chip and/or the semiconductor body may have a polygonal shape, such as rectangular, but may also have a round shape, such as circular. If the semiconductor chip is diced from a semiconductor wafer, then the semiconductor chip may be a polygon when viewed in a plan view; if the semiconductor chip is a semiconductor wafer or a major part of a semiconductor wafer, then the semiconductor chip can be a circle or a circle segment, for example with a central angle of more than 180°, when viewed in a plan view.

According to at least one embodiment, the electrical contact metallization is an integrated component of the semiconductor chip. Therefore, the electrical contact metallization may not be removable from the semiconductor chip without destroying the semiconductor chip.

According to at least one embodiment, the housing is of a multi-part nature. Accordingly, the housing can include other components apart from the electrical contact disk.

According to at least one embodiment, the electrical contact metallization and the electrical contact disk are in direct contact on the contact surface, so that the semiconductor chip is electrically connected to the housing, so that there are no additional electrical connecting means between the electrical contact metallization and the electrical contact disk. This configuration is often referred to as a dry contact. For example, there is no solder in a dry contact. The electrical contact metallization and the electrical contact disk can be reversibly removable from one another.

In accordance with at least one embodiment, the electrical contact metallization and/or the electrical contact disk includes the geometric structuring on the contact surface. The contact area can be a plane parallel or approximately parallel to main sides of the semiconductor chip.

The geometric structuring is designed as a recessed area. Accordingly, a contact area between the electrical contact metallization and the contact area is reduced due to the structuring. The structuring is located, for example, within an outer contour line of the electrical contact metallization and/or the electrical contact disk. Therefore, the recessed area is recessed relative to the contact area. For example, the depressed area is produced by removing material from or by patterning the electrical contact metallization and/or the electrical contact disk, but alternatively it is also possible that the depressed area results from the application of additional material to the electrical contact metallization and/or the electrical Contact disk results to produce ridges above a base level of the otherwise thinner electrical contact metallization and/or the electrical contact disk.

In accordance with at least one embodiment, the electrical contact metallization comprises Al and/or Ag. Alternatively or additionally, the electrical contact disk comprises Mo, Rh, Ru, Pd, Pt, W and/or aluminum graphite. For example, the electrical contact metallization comprises or consists of aluminum or an aluminum alloy and the electrical contact disk comprises or consists of molybdenum or a molybdenum alloy, where a thin plating of Rh or Ru can be applied to the molybdenum or molybdenum alloy so that the electrical contact disk im Essentially consists of molybdenum or a molybdenum alloy. In this context, essentially` can refer to a mass fraction of at least 95% or at least 99%.

In accordance with at least one embodiment, the thickness of the electrical contact metallization is at least 5 μm or at least 10 μm. Alternatively or additionally, the thickness is at most 100 µm or at most 50 µm. For example, the thickness is 20 µm.

In accordance with at least one embodiment, the thickness of the electrical contact disk is at least between 0.5 mm and at least 1.0 mm. Alternatively or additionally, the thickness is at most 5 mm.

In accordance with at least one embodiment, an average roughness of an upper surface of the electrical contact disk, which faces the electrical contact metallization, is at least 0.1 μm or at least 0.2 μm. Alternatively or additionally, the average roughness, which is also referred to as Ra, is at most 1 μm or at most at least 0.5 µm. That is, the top surface of the electrical contact disk is comparatively rough. In this case, due to the comparatively large roughness, the upper surface is configured to dig into the electrical contact metallization. For example, the electrical contact disk can penetrate an oxide layer of the electrical contact metallization on the contact surface.

In accordance with at least one embodiment, an average diameter of the electrical contact metallization is at least 1 cm or at least 3 cm. Alternatively or additionally, the mean diameter is at most 25 cm or at most 16 cm.

According to at least one embodiment, an average width of the geometric structuring is at least 0.2 mm or at least 1 mm. Alternatively or additionally, the mean width is at most 10 mm or at most 5 mm.

In accordance with at least one embodiment, an average depth of the geometric structuring is at least 1 μm or at least 3 μm. Alternatively or additionally, the average depth is at most 1 mm, or at most 0.2 mm, or at most 30 µm. For example, the average depth is at least twice and at most 20 times the average roughness of the electrical contact disk. The average depth of the geometric structuring is, for example, a volume of the at least one depressed area divided by a base area of the at least one depressed area.

In accordance with at least one embodiment, a surface proportion of the geometric structuring in relation to an overall size of the electrical contact metallization and/or the electrical contact disk which is/are provided with the geometric structuring is at least 20% or at most 40%. Alternatively or additionally, the proportion is at most 60% or at most 80%. This portion refers, for example, to a surface portion of the depressed area within the outer contour line of the electrical contact metallization and/or the electrical contact disk. Such a proportion allows size differences between the electrical contact metallization and the further electrical contact metallization to be efficiently compensated for.

In accordance with at least one embodiment, only the electrical contact metallization includes the geometric structuring and not the electrical contact disk. Therefore, the electrical contact metallization has the at least one recessed area.

In accordance with at least one embodiment, both the electrical contact metallization and the electrical contact disk are configured to be at the same electrical potential. In other words, both the electrical contact metallization and the electrical contact disk are electrically short-circuited. The electrical short circuit is realized, for example, within a material of the electrical contact metallization and the electrical contact disk itself or can be realized by another component that is adjacent to the electrical contact metallization and the electrical contact disk, such as a heavily doped semiconductor material of the semiconductor chip or an electrical contact plate of the package, will be realized.

According to at least one embodiment, the electrical contact metallization is of a multilayer type. Therefore, the electrical contact metallization comprises at least two sublayers. For example, all sub-layers are metallic layers. For example, all sub-layers follow one another directly in a direction away from the semiconductor body at locations where the respective sub-layers are applied to the semiconductor body.

In accordance with at least one embodiment, the electrical contact metallization comprises one or more interrupted partial layers. That is, the at least one discontinuous sub-layer may include sub-regions that are not connected by a material of the discontinuous sub-layer itself. In other words, the semiconductor body can be free from the at least one interrupted partial layer in places.

According to at least one embodiment, the electrical contact metallization comprises one or more continuous sub-layers. Therefore, the at least one continuous sub-layer can be free from any discontinuities and pinholes.

According to at least one embodiment, the at least one continuous sub-layer is located on the contact surface. Therefore, the at least one discontinuous sub-layer is located between the continuous sub-layer and the semiconductor material of the semiconductor chip.

For example, the at least one discontinuous sub-layer is completely covered and encapsulated by the at least one continuous sub-layer. Alternatively, the discontinuous sub-layer is on the contact surface and partially covers the at least one continuous sub-layer.

According to at least one embodiment, the at least one discontinuous sub-layer and the at least one continuous sub-layer consist of the same material, for example aluminum or an aluminum alloy. As an alternative, the at least one discontinuous sub-layer and the at least one continuous sub-layer consist of different materials.

According to at least one embodiment, the at least one discontinuous sub-layer and the at least one continuous sub-layer have different thicknesses. As an alternative, the at least one discontinuous sub-layer and the at least one continuous sub-layer may have the same thickness.

In accordance with at least one embodiment, only the electrical contact disk includes the geometric structuring and not the electrical contact metallization. Therefore, the at least one recessed area can be limited to the electrical contact disk. For example, the entire electrical contact disk is configured to be at the same electrical potential.

As an alternative to this, the electrical contact disc and the electrical contact metallization can be provided with the geometric structuring and can accordingly comprise recessed areas.

According to at least one embodiment, the geometric structuring consists of at least one of the following basic shapes or includes these when viewed in a plan view of the contact surface: circle, spiral, rectangle, triangle, hexagon, honeycomb. for example, the geometric structuring is of a rotationally symmetric or nearly rotationally symmetric type, or is a honeycomb structure.

For example, such a geometric structuring can be produced by means of etching, milling or turning or also by means of coating or plating into the electrical contact disk and/or the electrical contact metallization.

In accordance with at least one embodiment, the semiconductor chip comprises one or more than one further electrical contact metallization. For example, the at least one additional electrical contact metallization has an even and/or smooth additional contact surface. Flat means, for example, that the respective further electrical contact metallization has a surface that can be approximated by a plane, ie it has no or essentially no curvature when viewed in a cross section perpendicular to the surface of the further electrical contact metallization. Smooth means, for example, that the at least one further electrical contact metallization has an average roughness, Ra, which is at least 20% or 10% or 5% or 2% of the average roughness, Ra, of the at least one electrical contact metallization, and/or the average roughness, Ra, of at least one further electrical contact metallization is at most 0.1 µm or 0.01 µm.

This means that the further electrical contact metallization does not have the geometric structuring, for example, and accordingly does not have any recessed areas. Alternatively, the further electrical contact metallization, contrary to what is the case for the electrical contact metallization, can have a patterning required by the internal electrical scheme of the semiconductor chip.

In addition to the electrical contact metallization and the at least one further electrical contact metallization, the semiconductor chip can also comprise further electrical contact regions which are smaller than the electrical contact metallization and the at least one further electrical contact metallization, for example.

For example, the electrical contact metallization, the at least one further electrical contact metallization and also the at least one further electrical contact area are electrically separated from one another and are therefore not electrically short-circuited. For example, the electrical contact metallization is an anode, the further electrical contact metallization is a cathode and the further electrical contact region is a gate contact.

According to at least one embodiment, when viewed in a top view of the respective metallization, an overall size of the further contact area is smaller than that of the contact area and accordingly of the electrical contact metallization. For example, the size of the contact surface exceeds the size of the further contact surface by at least a factor of 1.5, or by at least a factor of 2, or by at least a factor of 3. Alternatively or additionally, the factor is at most 10 or is at most 5 or is at most 3.

According to at least one embodiment, due to the geometric structuring, a size of the contact surface of the electrical contact metallization or of the electrical contact disk is equal to the size of the further contact surface. For example, this applies with a tolerance of at most a factor of 1.2 or at most a factor of 1.1. Therefore, by means of the geometric structuring, effective sizes of the electrical contact metallization and the further electrical contact metallization are approximately the same. The effective size may refer to a size of a respective mechanical contact area. Accordingly, when the pressure on the particular component is calculated as force per area, the effective size should be considered as the relevant area in the expression force per area'.

In accordance with at least one embodiment, the electrical contact metallization and the further electrical contact metallization are located on opposite main sides of the semiconductor chip. For example, the electrical contact metallization and the further electrical contact metallization are partially or fully arranged in an overlapping manner when viewed in a plan view of the main sides of the semiconductor chip.

As an alternative to this, the electrical contact metallization and the further electrical contact metallization can also be located on the same main side of the semiconductor chip or also on lateral areas of the semiconductor chip.

According to at least one embodiment, the semiconductor chip is configured to be electrically contacted with a contact force of at least 0.3 kN/cm ² and/or at most 2 kN/cm ² or at most 3 kN/cm ² or at most 10 kN/cm ² to become. Accordingly, the semiconductor chip and consequently the electrical contact metallization and the optional at least one further electrical contact metallization are configured to withstand such comparatively high pressures.

For example, this high pressure does not exist in the unassembled electronic device but only in the assembled electronic device. Correspondingly, with the electronic device not yet assembled, the electrical contact disk can be arranged loosely on the electrical contact metallization or only by applying a small pressure of, for example, at most 0.1 kN/cm ² or at most 10 N/cm ² . The same applies to the optional at least one additional electrical contact metallization. Assembled may refer to the electronic device arranged in a stack.

According to at least one embodiment, the housing comprises an electrically insulating casing and/or at least one electrical metal contact plate. For example, the casing is made of a ceramic, but it can also be made of a plastic. The metal contact plate or metal contact plates is/are made of, for example, Cu and may include a coating of, for example, Ni. A thickness of the at least one metal contact plate can be at least 2 mm and/or at most 3 cm.

In accordance with at least one embodiment, the semiconductor chip and the at least one electrical contact disk and the at least one metal plate are arranged in the encapsulation. The semiconductor chip and the at least one electrical contact disk and the at least one metal plate are arranged, for example, parallel to one another and/or congruently or approximately congruently.

In accordance with at least one embodiment, sizes of the semiconductor chip and the at least one electrical contact disk differ from one another by at most a factor of 1.3 or by at most a factor of 1.1 when viewed in a plan view of the contact area.

In accordance with at least one embodiment, the electrical contact disk is located between the semiconductor chip and the contact plate. For example, there is the following stack within the enclosure: first contact plate - first electrical contact disk - semiconductor chip comprising the electrical contact metallization, the further contact area and the opposite further electrical contact metallization - second electrical contact disk - second contact plate.

A housing and a semiconductor chip for the electronic device are additionally provided. By using the package and/or the semiconductor chip, the electronic device as specified in connection with at least one of the aforementioned embodiments is produced. Features of the electronic device are therefore also disclosed for the housing and the semiconductor chip and vice versa.

In at least one embodiment, the housing includes a contact surface with a geometric pattern.

In at least one embodiment, the semiconductor chip includes an electrical contact metallization with a geometric structure on a contact area.

A device stack is also provided. The device stack includes a plurality of the electronic devices as recited in connection with at least one of the aforementioned embodiments. Features of the electronic Devices are therefore also disclosed for the device stack and vice versa.

In at least one embodiment, the device stack includes a plurality of the electronic devices, wherein the electronic devices are stacked on top of each other. For example, the electronic devices touch each other directly without any additional electrical connection means or have pieces for cooling or electrical connection between them. The electronic devices may be arranged in a registering manner. For example, the electronic devices are pressed against each other.

An electronic device, a package, a semiconductor chip and a device stack described herein are explained in more detail below by means of exemplary embodiments with reference to the drawings. Elements that are the same in the individual figures are given the same reference numbers. The relationships between elements are not shown to scale, instead individual elements may be exaggerated to aid understanding.

• 1 bis 8 sind schematische Schnittansichten von Ausführungsbeispielen hier beschriebener elektronischer Vorrichtungen,
• 9 bis 14 sind schematische Draufsichten von Ausführungsbeispielen elektrischer Kontaktscheiben und elektrischer Kontaktmetallisierungen für hier beschriebene elektronische Vorrichtungen,
• 15 ist eine schematische Schnittansicht eines Ausführungsbeispiels eines Halbleiterchips für hier beschriebene elektronische Vorrichtungen, und
• 16 und 17 sind schematische Schnittansichten von Ausführungsbeispielen von Vorrichtungsstapeln, die hier beschriebene elektronische Vorrichtungen umfassen.

In the figures:

• 1 until 8th are schematic sectional views of embodiments of electronic devices described herein,
• 9 until 14 are schematic plan views of embodiments of electrical contact disks and electrical contact metallization for electronic devices described herein,
• 15 12 is a schematic sectional view of an embodiment of a semiconductor chip for electronic devices described herein, and
• 16 and 17 12 are schematic sectional views of example embodiments of device stacks that include electronic devices described herein.

1 FIG. 11 illustrates an embodiment of an electronic device 1. The electronic device 1 comprises a semiconductor chip 2. The semiconductor chip 2 is in direct contact with and located between two metal electrical contact disks 5, which are located between two metal electrical contact plates 42. FIG. The components 2, 5, 42 are located in an electrically insulating casing 41 and are arranged directly one on top of the other and are approximately the same size. The electrical contact disks 5, the contact plates 42 and the casing 42 constitute a housing 4 of the electronic device 1.

As an option there is a further contact 8 which can be accessible through the casing 41.

In 2 a possible arrangement around the semiconductor chip 2 is illustrated in more detail. The semiconductor chip 2 comprises a semiconductor body 22, which is made of Si, for example, and which can comprise differently doped zones, which are not shown. For example, the semiconductor chip 2 is a GTO or an IGCT.

In addition, the semiconductor chip 2 includes a larger electrical contact metallization 3 on a main side and a smaller, further electrical contact metallization 7 on the opposite, other main side. For example, the electrical contact metallization 3 is an anode having a size of at least 2 cm ² and at least 20 cm ² , for example 40 cm ² . The further electrical contact metallization 7 can be a cathode with a size of at least 1 cm ² and at least 10 cm ² , for example 10 cm ² . A thickness of the semiconductor chip 2 is, for example, at least 0.3 mm and/or at most 1.5 mm. The same features can apply to all other embodiments, individually or all together.

the inside 1 The further contact 8 shown can be electrically connected to a comparatively small further electrical contact area 80 in a central area of the further electrical contact metallization 7 . A mean diameter D of the electrical contact metallization 3 and accordingly of the semiconductor chip 2 is, for example, at least 2 cm and at most 20 cm. The semiconductor chip 2, the electrical contact disk 5 and the optical contact plate 42 in 2 not shown may have a circular shape when viewed in a plan view. The same features can apply to all other embodiments, individually or all together.

The, for example, exactly one further electrical contact metallization 7 can have different regions which are separated by indentations when viewed in a cross section. All of these regions can be electrically short-circuited within the semiconductor body 22 or within the further electrical contact metallization 7 when viewed in a plan view. A structure of the additional electrical contact metallization 7 can by the internal structure of the semiconductor chip 2 in contrast to a geometric structure turing of the electrical contact metallization 3 are specified.

Power semiconductor devices such as the electronic device 1 with pressure contacts may suffer from contact degradation from too low a clamping pressure. The pressure at a given contact force is increased in the electronic device 1 by reducing the total contact area, i.e. a contact area 45 between the electrical contact metallization 3 of the semiconductor chip 2 and the electrical contact disk 5 of the housing 4, in order to achieve a reliable and stable dry electrical interface contact form.

Press-pack power semiconductor devices with dry interfaces between the package parts and the silicon device metallization, typically a Mo disk 5 in contact with an Al metallization 3 of the Si-based semiconductor chip 2, sometimes suffer from too little contact pressure to form a stable reliable dry interface . For a good contact, for example to an aluminum metallization, the native oxide of aluminum must be penetrated through the contact partner, i.e. through the Mo-based electrical contact disk, and a stable contact over time must be established without leading to a degradation mechanism , such as galling, i.e. lateral movement of the contact partners due to insufficient friction, leading to oxidation of the interfaces, such as thermal local contact overload, i.e. too low density of α-sites, and/or such as electromigration, which is caused by local high current densities and local Temperature extrusion are triggered.

• - extern: eine Vorrichtung muss in einem Stapel mit anderen Vorrichtungen geklemmt werden, die eine Beschränkung der Klemmkraft haben, zum Beispiel eine Diode, die in einem Stapel mit einem IGCT oder GTO geklemmt wird, der bezüglich einer maximalen Klemmkraft durch die geringe Fläche einer Kathodenmetallisierung beschränkt wird;
• - vorrichtungsintern: in einem GTO oder IGCT wird die maximale Klemmkraft durch die mechanische Stabilität der Kathodensegmentmetallisierung beschränkt, zum Beispiel unter Bedingungen des zyklischen Durchlaufens einer Belastung, wobei ansonsten eine inakzeptable Verschlechterung der Kathodenmetallisierung resultiert.

The too low pressure can have reasons like:

• - external: a device must be clamped in a stack with other devices that have a clamping force limitation, for example a diode clamped in a stack with an IGCT or GTO limited in terms of maximum clamping force by the small area of a cathode metallization is restricted;
• - device internal: in a GTO or IGCT, the maximum clamping force is limited by the mechanical stability of the cathode segment metallization, for example under stress cycling conditions, otherwise an unacceptable degradation of the cathode metallization results.

The contact area of the cathode metallization is typically significantly smaller than the anode contact area, typically three to five times. The homogeneous anode side metallization therefore experiences a much lower overall clamping pressure between the electrical chip side contact metallization 3 and the Mo-based electrical contact disk 5.

Recent developments in power semiconductor devices have focused on increasing the power handling capability by increasing the current carrying capacity and increasing the maximum operating junction temperature of the devices. This leads to additional stress on the contacts, mechanically due to softening of the metallization due to higher temperatures and contact deterioration such as α-site overload or electromigration due to higher temperatures and an increase in current density, compare Black's law.

• - Dies gilt nur für ideale nichtoxidierte Oberflächen. Bis das Oxid durch die Rauigkeit des härteren Kontaktpartners penetriert wird, ist die lineare Abhängigkeit nicht gültig. Dies ist in 3 veranschaulicht, wobei eine dünne Oxidschicht 31 noch nicht durch eine Aufrauung 55 auf einer oberen Fläche 50 der elektrischen Kontaktscheibe 5 penetriert wird.
• - Niedriger Druck führt zu einem niedrigeren Reibungskoeffizienten. Dies erlaubt eine Bewegung zwischen der elektrischen Al-Kontaktmetallisierung 3 des Halbleiterchips 2 und der elektrischen Mo-Kontaktscheibe 5. Dies kann zu Reibkorrosion an der Kontaktschnittstelle 45 führen.
• - Die geringe Dichte von α-Stellen führt zu lokaler Temperaturzunahme und lokaler hoher Stromdichte, was Elektromigration zusammen mit lokaler Überhitzung hervorrufen kann.

The interface resistivity of a dry interface is defined in the first order by the clamping force, up to the yield point of the softer contact partner. Reducing the contact area would not improve the interface resistance according to this first-order law, but:

• - This only applies to ideal non-oxidized surfaces. Until the oxide is penetrated by the roughness of the harder contact partner, the linear dependence is not valid. this is in 3 illustrated, wherein a thin oxide layer 31 is not yet penetrated by a roughening 55 on a top surface 50 of the electrical contact disk 5.
• - Lower pressure leads to a lower coefficient of friction. This allows movement between the electrical Al contact metallization 3 of the semiconductor chip 2 and the electrical Mo contact disk 5. This can lead to fretting corrosion at the contact interface 45.
• - The low density of α-sites leads to local temperature increase and local high current density, which can induce electromigration together with local overheating.

• - eine Anodenseitenmetallisierung eines IGCT oder eines GTO, da die Klemmkraft typischerweise durch die mechanische Stabilität der Kathodenseitenmetallisierung beschränkt wird, die insgesamt einen erheblich geringeren Kontaktbereich aufweist und aufgrund der Segmentierung eines hohen Metallstapels fragiler ist;
• - eine Metallisierung einer frei gleitenden Seite einer gebondeten Diode, die mit geringen Klemmkräften verwendet wird, zum Beispiel, wenn sie mit einem IGCT geklemmt wird; für eine frei gleitende Anodenseite kann die Wahrscheinlichkeit einer Elektromigration höher sein;
• - eine Anoden- und Kathodenseitenmetallisierung einer frei gleitenden Diode oder einer frei gleitenden Plus-Diode, die mit relativ geringen Drücken geklemmt wird.

In the case of the electronic device 1 described here, a geometric structuring 6 of the electrical contact metallization 3 and/or the electrical contact disk 5 is used for dry electrical interfaces in order to avoid the effects of “too low pressure”. For example, the contact interface 45 that may otherwise suffer from the effects of 'under pressure' is:

• - An anode side metallization of an IGCT or a GTO, since the clamping force is typically due to the mechanical stability of the Cathode side metallization is limited, which has significantly less overall contact area and is more fragile due to the segmentation of a tall metal stack;
• - a metallization of a free-sliding side of a bonded diode used with low clamping forces, for example when clamped with an IGCT; for a freely sliding anode side, the likelihood of electromigration may be higher;
• - an anode and cathode side metallization of a free floating diode or a free floating plus diode clamped with relatively low pressures.

A first way to increase the pressure of a dry contact interface 45 for a given clamping force between the electrical contact metallization 3 and the electrical contact disk is to reduce the effective contact area by patterning the electrical contact metallization 3, see FIG 4 .

Accordingly, the electrical contact metallization 3 according to 4 the geometric structuring 6, which corresponds to a partial removal of the electrical contact metallization 3. Accordingly, the semiconductor body 22 is exposed in places independent of possible layers, such as passivation layers on the semiconductor body 22 . The individual areas of the electrical contact metallization 3 are electrically short-circuited, for example by means of a heavily doped semiconductor material 23 on the upper side of the semiconductor body 22. However, the heavily doped semiconductor material 23 can be a continuous layer close to the electrical contact metallization 3, whereby a form of the geometric patterning 6 is not prescribed.

A width W of the depressions that form the geometric structure 6 is between 0.2 mm and 5 mm, for example. A mean depth T6 of the geometric structuring 6 is in 4 equal to a thickness T3 of the electrical contact metallization. The thickness T3 is, for example, at least 5 µm and at most 30 µm. The roughening 55 on the upper surface 50 of the electrical contact disc 5 has, for example, an average roughness of between 0.1 μm and 0.5 μm, whereas the electrical contact metallization 3 is, for example, of the planar type, that is to say an average roughness of, for example at most 1 µm or at most 10 nm. The same features can apply to all other embodiments, individually or all together.

An average penetration depth of the roughening 55 into the electrical contact metallization 3 is, for example, at least 4 nm or at least 10 nm and/or at most 0.1 μm or at most 40 nm. The same is possible in all other exemplary embodiments.

the as in 4 The arrangement shown can increase a thermal impedance and an electrical conductivity, for example to the non-metallized areas of the semiconductor chip 2 . This can be true if the lateral conductivity in the Si-based semiconductor chip 2 is low, for example for a transparent emitter of an IGCT. Thermal and electrical behavior can be improved using a second way of balancing the contact pressure, see 5 .

Correspondingly, the electrical contact metallization 3 comprises a discontinuous sub-layer 33 directly at the semiconductor body 22 and a continuous sub-layer 34 on the discontinuous sub-layer 33. For example, the discontinuous sub-layer 33 is thinner than the continuous sub-layer 34. For example, the thickness T6 of the continuous sub-layer 34 exceeds a thickness T3 minus T6 of the discontinuous sub-layer 33 by at least a factor of five and/or by a maximum of a factor of 30. For example, the thickness T6 of the continuous sub-layer 34 and therefore of the geometric pattern 6 is at least 0.5 µm or at least 1 µm and/or at most 10 µm or at most 5 µm. For example, the thickness T6 exceeds the mean roughness of the roughening 55 by at least a factor of three. The same features can apply to all other embodiments, individually or all together.

Otherwise applies to 5 the same as for 1 until 4 .

• - einem niedrigeren spezifischen Kontaktwiderstand aufgrund einer besseren Penetration des nativen Oxids der Al-basierten elektrischen Kontaktmetallisierung 3 des Halbleiterchips 2;
• - einem höheren Reibungskoeffizienten zwischen der elektrischen Kontaktscheibe 5 und dem Halbleiterchip 2, was zu idealerweise keiner Bewegung zwischen der Kontaktscheibe 5 und der elektrischen Kontaktmetallisierung 3 während des zyklischen Durchlaufens von Belastungen führt, so dass Fressen vermieden werden kann;
• - aus mechanischen Gründen kann eine Musterübereinstimmung der Metallstruktur auf der Kathoden- und der Anodenseite eines GTO oder eines IGCT wünschenswert sein; ansonsten könnte eine hexagonale geometrische Struktur 6 verwendet werden.

For example, introducing the geometric structuring 6 leads to:

• - A lower specific contact resistance due to better penetration of the native oxide of the Al-based electrical contact metallization 3 of the semiconductor chip 2;
• - a higher coefficient of friction between the electrical contact disk 5 and the semiconductor chip 2, which ideally results in no movement between the contact disk 5 and the electrical contact metallization 3 during stress cycling, so that galling can be avoided;
• - for mechanical reasons, pattern matching of the metal structure on the cathode and the anode side of a GTO or an IGCT may be desirable; else ten, a hexagonal geometric structure 6 could be used.

Since the requirement for the placement accuracy of the structured metal is not very high, most likely less than 100 µm, a cost-effective process of structuring, such as shadow masking of the respective metal, is possible. It is also possible to distribute the contact points through a defined structure of the upper surface 50 of the electrical contact disc using, for example, turning or etching of either the bulk metal or its cladding 51, cf 7 .

Another possibility is to shadow mask the electrical contact disk plating 51 . Although etching/shadow masking the top surface 50 of the electrical contact wafer is conceptually no different than doing the same on the die side, machining the respective surface offers a relatively inexpensive process for obtaining a controlled contact point distribution. An example of such an assembly is in 6 shown.

Accordingly, the geometric structure 6 can be obtained by machining. Both milling and turning can produce controlled surface structures. Turning is only capable of concentric circles. A milled surface, in contrast, can produce a wide variety of different straight patterns, but has difficulty with concentric distribution patterns.

In 7 it is illustrated that both the semiconductor chip 2 and the electrical contact disk 5 have a geometric structure 6 . In order to enable a defined size of the effective contact area at the contact area 45, one geometric structuring 6 has a much larger structural size or periodicity than the other geometric structuring 6, for example.

In addition, 7 Illustrated as an option that the electrical contact disc 5 comprises the plating 51 . For example, the plating 51 has a thickness of at most 0.3 μm compared to a thickness T5 of the electrical contact disk 5 of, for example, between 1 mm and 5 mm, compare also 8th . The plating 51 may include or consist of Rh and/or Ru and/or Pt, while a thick bulk electrical contact disk may include or consist of Mo or W. The same features can apply to all other embodiments, individually or all together.

Otherwise applies to 7 the same as for 1 until 6 .

In the embodiment of 8th Both the plating 51 and the bulk electrical contact disk body comprise the geometric patterning 6. The geometric patterning 6 may be sinusoidal when viewed in a cross-section.

Additionally, on a rear surface 52 opposite top surface 50, the electrical contact disk may be polished and accordingly planar in nature.

There may be the contact plate 42. A thickness T4 of the contact plate 42 is, for example, at least 3 mm and/or at most 2 cm. The contact plate 42 may include a coating 44 on a side facing the electrical contact disk 5 . For example, the coating 44 is made of Ni and/or has a thickness between 2 μm and 20 μm. For example, the side of the contact plate 42 facing the electrical contact disc 5 is not structured and is accordingly of a planar nature. The contact plate 42 can be made of Cu or of a copper alloy. The same features can apply to all other embodiments, individually or all together.

Otherwise applies to 8th the same as for 1 until 7 .

In 9 until 14 Various possibilities for shaping the geometric structure 6 are illustrated when viewed in a plan view. In these figures, the geometric structure 6 is represented in a simplified way as a line.

According to 9 the geometric structuring 6 comprises a plurality of, for example, concentric circles. In 10 the geometric structuring 6 is of a spiral type. In 11 a rectangular grid is used that can reach as far as an edge of the electrical contact disk 5 or the electrical contact metallization 3 . According to 12 the geometric structuring 6 does not extend to the edge of the electrical contact disk 5 or the electrical contact metallization 3 and is of a triangular type. In 13 the geometric structuring 6 is of a honeycomb type. Finally, see 14 , the geometric structuring have 6 different structural units that may include interruptions.

all in 9 until 14 illustrated variations can in the Ausführungsfor men off 1 until 8th be used. Also combinations of the individual examples 9 until 14 can be applied.

In 15 It is illustrated that the smaller additional electrical contact metallization 7 and the larger electrical contact metallization 3 can be located on the same main side of the semiconductor chip 2. The sizes of the contact surfaces 46, 70 are again approximately the same by means of the geometric structuring 6.

Otherwise applies to 15 the same as for 1 until 4 .

16 Figure 11 illustrates an example of a device stack 9. The device stack 9 includes a plurality of the electronic devices 1 in face-to-face contact with each other. For example, the electronic devices 1 are pressed and clamped together in a congruent manner with a comparatively high pressure of, for example, 1 kN/cm ² . This pressing together causes the roughening of the electrical contact disk to be pressed into the electrical contact metallization.

17 Figure 9 illustrates another example of a device stack similarly 16 , but using intermediate devices 95 between the electronic devices 1. The intermediate devices 95 are, for example, a cooler for extracting dissipated power from the electronic devices 1. Alternatively or additionally, the intermediate devices 95 may be electrical contact bars or electrical insulators or mixtures thereof.

All electronic devices 1, housing 4 and semiconductor chips 2 off 1 until 15 can for the device stack 9 out 16 and 17 be used.

Unless otherwise indicated, the components shown in the figures preferably follow one another directly in the specified sequence. Components that are not in contact in the figures are preferably spaced apart. If lines are drawn parallel to each other, the corresponding surfaces are preferably oriented parallel to each other. Likewise, unless otherwise indicated, the positions of the drawn components relative to each other are correctly reproduced in the figures.

The invention described here is not limited by the description given with reference to the exemplary embodiments. Rather, the invention includes any novel feature and any combination of features, including in particular any combination of features in the claims, even if that feature or combination itself is not explicitly recited in the claims or embodiments.

This patent application claims priority from European patent application 20193656.4, the disclosure of which is hereby incorporated by reference.

Reference List

1

electronic device

2

semiconductor chip

22

semiconductor body

23

heavily doped semiconductor material

3

electrical contact metallization

31

oxide layer

33

broken part layer

34

continuous sub-layer

4

Housing

41

electrically insulating casing

42

electrical metal contact plate

43

passivation

44

coating

45

contact surface

5

electrical contact disc

50

upper surface

51

plating

52

back surface

55

roughening

6

geometric structuring

7

further electrical contact metallization

70

further contact surface

8th

further contact

80

further contact area

9

device stack

95

intermediate device

D

average diameter of the electrical contact metallization

T3

Electrical contact metallization thickness

T5

Thickness of the electrical contact disc

T4

thickness of the contact plate

T6

mean depth of the geometric structuring

W

mean width of the geometric structuring

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US20130207157A1 [0002]

Claims (15)

Electronic device (1) comprising: - A semiconductor chip (2) with a semiconductor body (22) and an electrical contact metallization (3), and - A housing (4) with an electrical contact disc (5), wherein - The electrical contact metallization (3) and the electrical contact disk (5) are in direct contact on a contact surface (45), so that the semiconductor chip (2) is electrically connected to the housing (4), and - The electrical contact metallization (3) on the contact surface (45) comprises a geometric structure (6) which is designed as at least one recessed area, and - the electrical contact metallization (3) is of a multilayer type and comprises at least one discontinuous sublayer (33) and at least one continuous sublayer (34), the continuous sublayer (34) is located directly on the semiconductor body (22) and has a thickness (T6 ) of the continuous sub-layer (34) exceeds a thickness of the discontinuous sub-layer (33) by at least a factor of five. Electronic device (1) according to the preceding claim, wherein the electrical contact metallization (3) comprises at least one of Al and Ag and the electrical contact disc (5) comprises at least one of Mo, Rh, Ru, Pd, Pt and W. Electronic device (1) according to one of the preceding claims, wherein a thickness (T3) of the electrical contact metallization (3) is between 5 µm and 50 µm and a thickness (T5) of the electrical contact disk (5) is between 0.5 mm and 10 mm, wherein an average roughness of an upper surface (50) of the electrical contact disk (5), which faces the electrical contact metallization (3), is between 0.2 µm and 1 µm, and wherein the upper surface (50) is designed to penetrate an oxide layer (31) of the electrical contact metallization (3) on the contact surface (45) due to the average roughness. Electronic device (1) according to one of the preceding claims, wherein an average diameter (D) of the electrical contact metallization (3) is between 1 cm and 25 cm, and wherein an average width (W) of the geometric structure (6) is between 0.1 mm and 5 mm, an average depth (T6) of the geometric structure (6) is at least 0.1 µm and at most 30 µm. Electronic device (1) according to one of the preceding claims, wherein an area proportion of the geometric structuring (6) of an overall size of the electrical contact metallization (3) which is provided with the geometric structuring (6) is at least 20% and at most 80%. Electronic device (1) according to one of the preceding claims, wherein the entire electrical contact metallization (3) is set up to be at the same electrical potential. Electronic device (1) according to one of the preceding claims, wherein the at least one discontinuous sub-layer (33) and the at least one continuous sub-layer (34) consist of different materials. Electronic device (1) according to any one of Claims 1 until 6 , wherein the at least one discontinuous sub-layer (33) and the at least one continuous sub-layer (34) consist of the same material. Electronic device (1) according to one of the preceding claims, in which the entire electrical contact disc (5) is set up to be at the same electrical potential. Electronic device (1) according to one of the preceding claims, wherein the geometric structure (6), viewed in plan view of the contact surface (45), consists of or comprises at least one of the following shapes: circle, spiral, rectangle, triangle, hexagon, Honeycomb. Electronic device (1) according to one of the preceding claims, wherein the semiconductor chip (2) comprises a further electrical contact metallization (7) with a flat and smooth further contact area (70), wherein an overall size of the further contact surface (70), seen in plan view, is smaller than that of the electrical contact metallization (3) by at least a factor of 1.5 and at most a factor of 5, and wherein the contact surface (45) has the same size as the overall size of the further contact surface (70) due to the geometric structure (6), with a maximum tolerance of a factor of 1.2. Electronic device (1) according to the immediately preceding claim, wherein the electrical contact metallization (3) and the further electrical contact metallization (7) are on opposite main sides of the semiconductor chips (2) are located, the semiconductor chip (2) being set up to be electrically contacted with a contact force of at least 0.3 kN/cm ² and at most 2 kN/cm ² . Electronic device (1) according to any one of Claims 11 and 12 , wherein an average width of the at least one depressed region is smaller by at least a factor of two than a structure size of the further electrical contact metallization along the same direction. Electronic device (1) according to one of the preceding claims, the housing (4) comprising an electrically insulating casing (41) and an electrical metal contact plate (42), wherein the semiconductor chip (2) and the electrical contact disk (5) and the metal plate (42) are arranged in the casing (41) and are aligned parallel to one another, wherein, seen in a plan view of the contact surface (45), the sizes of the semiconductor chip (2) and the electrical contact disk (5) differ from one another by a maximum of a factor of 1.3, and wherein the electrical contact disc (5) between the semiconductor chip (2) and the contact plate (42) enemies. Semiconductor chip (2) with a semiconductor body (22) and an electrical contact metallization (3), wherein - a contact surface (45) of the electrical contact metallization (3) is set up to be brought into direct contact with an electrical contact disk (5), - The electrical contact metallization (3) on the contact surface (45) comprises a geometric structure (6) which is designed as at least one recessed area, and - the electrical contact metallization (3) is of a multilayer type and comprises at least one discontinuous sub-layer (33) and at least one continuous sub-layer (34), the continuous sub-layer (34) is directly adjacent to the semiconductor body (22) and has a thickness (T6 ) of the continuous sub-layer (34) exceeds a thickness of the discontinuous sub-layer (33) by at least a factor of five.

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