DE2113831A1 - Junction field effect transistor and process for its manufacture - Google Patents
Junction field effect transistor and process for its manufactureInfo
- Publication number
- DE2113831A1 DE2113831A1 DE19712113831 DE2113831A DE2113831A1 DE 2113831 A1 DE2113831 A1 DE 2113831A1 DE 19712113831 DE19712113831 DE 19712113831 DE 2113831 A DE2113831 A DE 2113831A DE 2113831 A1 DE2113831 A1 DE 2113831A1
- Authority
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- Prior art keywords
- layer
- metal
- masking
- transistor
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 19
- 230000005669 field effect Effects 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 230000000873 masking effect Effects 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 claims 11
- 239000011241 protective layer Substances 0.000 claims 3
- 239000000758 substrate Substances 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 229910052715 tantalum Inorganic materials 0.000 description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 description 3
- 238000007669 thermal treatment Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 101150034459 Parpbp gene Proteins 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003442 weekly effect Effects 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Description
SESCOSEM - SOGIETE EUKOPSHUS DE SEMI-GOiCDTJCTEURS ET DE MICROEIECTROtflQUESESCOSEM - SOGIETE EUKOPSHUS DE SEMI-GOiCDTJCTEURS ET DE MICROEIECTROtflQUE
101, Bl. Hurat101, p. Hurat
Pa r i 3 16e*ine /FrankreichPari 3 16e * ine / France
Unser Zeichen: S 2615Our reference: S 2615
Sperrschicht-Feldeffekttransistor und Verfahren au seiner HerstellungJunction field effect transistor and process for its manufacture
Zur Herstellung eines Sperrschicht-Feldeffekttransistors wendet man in der Regel Photοgravurverfahren an. Bekanntlich bedingen diese Verfahren die Verwendung mehrerer aufeinanderfolgender Maskierungen und zwar in der Regel vier.Photo-engraving processes are usually used to manufacture a junction field effect transistor. As is well known These methods require the use of several successive masks, as a rule four.
Diese Verfahren sind daher kompliziert und kostspielig.These procedures are therefore complicated and costly.
Die vorliegende Erfindung "betrifft ein Verfahren zur Herstellung von Sperrschicht-Feldeffekttransistoren, das nur eine geringere Anzahl von Maskierungen benötigt.The present invention "relates to a method for Manufacture of junction field effect transistors that only require a small number of masks.
Da3 erfindungsgemässe Verfahren kennzeichnet sich im wecentlichen dadurch, dass während einer Verfahrensstufe das Plättchen, auf welchem der Transistor erhaltenDa3 method according to the invention is characterized in weekly by the fact that during a procedural stage the plate on which the transistor is received
Dr.Ha/KÜDr Ha / KÜ
109842/1638109842/1638
21133312113331
werden soll, mit einer Schicht eines im Verlauf einer "bestimmten thermischen Behandlung oxydierbaren Hetalla bedeckt, auf dieser Schicht eine Maskierung abgeschieden wird, welche aus einem während dieser thermischen Behandlung nicht oxydierbaren Schutametail besteht und dass das Ganze dann dieser thermischen Behandlung unterworfen wird, wobei das oxydierbare Metall oxydiert und so in den nicht durch die Maskierung geschützten Bereichen eine dielektrische Schicht bildet, während es in den geschützten Bereichen unverändert bleibt, worauf man mit dem Schutzmetall elektrische Anschlüsse zu den verschiedenen Bestandteilen des Transistors bildet.should be, with a layer one in the course of a "certain thermal treatment oxidizable Hetalla covered, a mask is deposited on this layer, which is made of a during this thermal treatment non-oxidizable protective detail and that the whole is then subjected to this thermal treatment, the oxidizable metal being oxidized and a dielectric layer forms in the areas not protected by the masking, while it forms in the protected areas remains unchanged, whereupon electrical connections to the various electrical connections are made with the protective metal Forms components of the transistor.
Die Erfindung wird anhand der folgenden Beschreibung in Verbindung mit der Zeichnung besser verständlich:The invention can be better understood from the following description in conjunction with the drawing:
In der Zeichnung zeigen:In the drawing show:
Fig. 1-6 einen Querschnitt durch ein Halbleiterplättchen während verschiedener Herstellungsstufen einer ersten Ausführungsform des erfindungsgemäßen Verfahrens.1-6 shows a cross section through a semiconductor wafer during various stages of manufacture of a first embodiment of the method according to the invention.
Fig. 7,8 u.9 ein Halbleiterplättchen unter den gleichenFigs. 7, 8 and 9 show a semiconductor die among the same
Bedingungen während der verschiedenen Stufen einer zweiten Ausführungsform des erfindungsgemäßen Verfahrens.Conditions during the various stages of a second embodiment of the invention Procedure.
In Fig. 1 wird ein Siliciumplättchen 1 mit einer P(+)-Dotierung epitaktisch mit einer Siliciumschicht 2, jedoch mit IT-Dotierung,bedeckt.In FIG. 1, a silicon wafer 1 with a P (+) doping becomes epitaxial with a silicon layer 2, however with IT doping, covered.
Auf das Ganze wird dann eine dünne Schicht 3 aus SiliciumA thin layer 3 of silicon is then placed on top of the whole
109842/1638109842/1638
mit einer unter 1 Mikron liegenden Dicke aufgebracht (diese Schicht kann nach üblichen Diffusionsraethoden erhalten werden). Diese Schicht besitzt eine P(+)-Dotierung. applied with a thickness of less than 1 micron (this layer can be applied using conventional diffusion methods obtained). This layer has a P (+) doping.
Das Ganze wird dann (Pig. 2) durch Oxydation mit einer Siliciumdioxidschicht (SiOp) 4 bedeckt. Diese Schicht dient als Schutz für die folgenden Behandlungsstufen.The whole is then (Pig. 2) covered with a silicon dioxide layer (SiOp) 4 by oxidation. This layer serves as protection for the following stages of treatment.
In Fig. 3 wurde die Schicht 4 in den Bereichen 5 und 6, die nicht mit der Schutsxaaskierung bedeckt sind, ausgehöhlt .In Fig. 3, the layer 4 was in the areas 5 and 6, which are not covered with the Schutsxaaskierung, hollowed out.
Die Siliciuiaschicht 3 wurde dabei in den Bereichen 5 und freigelegt. In diese Bereiche erfolgte eine Diffusion. Dadurch werden zwei N + dotierte Anschlußstellen 8 und geschaffen, welche quer durch die Schicht 3 hindurch verlaufen und bis zu der Schicht 2 vordringen. Die !!+-Dotierung ist wesentlich stärker als die P+-Dotierung.The Siliciuiaschicht 3 was in the areas 5 and exposed. Diffusion took place in these areas. As a result, two N + doped connection points 8 and created, which run transversely through the layer 3 and penetrate to the layer 2. the !! + doping is much stronger than P + doping.
In Pig. 4 wurde die SiO -Schicht entfernt und gemäß der Erfindung durch eine Schicht 10 aus einem während einer geeigneten Wärmebehandlung vollständig oxydierbarem Metall ersetzt. Dieses Metall kann beispielsweise Tantal, Hafnium oder Zirkon sein.In Pig. 4 the SiO 3 layer was removed and, according to the invention, by a layer 10 of one during one suitable heat treatment completely oxidizable metal replaced. This metal can, for example, be tantalum or hafnium or be zircon.
In Pig. 5 wurde eine Schutzmaskierung aus einem durch die Wärmebehandlung nicht angreifbaren Metall abgeschieden. Ein Teil 11 dieser Maskierung bedeckt den eindiffundierten Bereich 8, ein anderer Teil 12 bedeckt die Diffusion 9. Ein Teil 13 der Maskierung befindet sich zwischen den Teilen 11 und 12.In Pig. 5, a protective mask made of a metal that cannot be attacked by the heat treatment was deposited. A part 11 of this masking covers the diffused area 8, another part 12 covers the diffusion 9. Part 13 of the mask is located between parts 11 and 12.
1098A2/16381098A2 / 1638
Diese Maskierung besteht zum Beispiel au3 Aluminium. Dieses Metall ist gegen eine Oxydation bei 500° ü in einer oxydierenden Atmosphäre beständig, während das Tantal unter diesen Bedingungen vollständig in Tantaloxid Ta?0,-übergeführt wird.This masking consists of aluminum, for example. This metal is resistant to oxidation at 500 ° in an oxidizing atmosphere, while the tantalum is completely transformed into tantalum oxide Ta ? 0, -converted.
In Fig. 6 würde das Plättchen der vorstehend besprochenen Wärmebehandlung unterworfen.In Figure 6, the wafer would be subjected to the heat treatment discussed above.
Das Aluminium sowie die durch die Teile 11, 12 und 13 der Maskierung geschützten Teile der Tantalschicht 14, 15 imd wurden nicht verändert.The aluminum as well as the parts 11, 12 and 13 of the Masking protected parts of the tantalum layer 14, 15 imd were not changed.
Der Rest der Tantalschicht wurde zur Tantaloxidschicht 17» die ein Dielektrikum bildet.The rest of the tantalum layer became the tantalum oxide layer 17 » which forms a dielectric.
Man erhält so einen Sperrschicht-Feldeffekttransistor, dessen N + dotierte Kontaktstellen 8 und 9 Source und Drain bilden und wobei der P(+)-Teil der Schicht 3, welcher die Kontaktstellen 8 und 9 verbindet, eine Steuerelektrode des Transistors bildet, während die andere Steuerelektrode aus der Schicht 1 besteht. Die Zugänge werden durch die Anschlüsse 11 - 14, 13-15, 12-16 gebildet, wobei jeder dieser Anschlüsse aus einer von einer Aluminiumschicht bedeckten Tantalschicht besteht.In this way, a junction field effect transistor is obtained, the N + doped contact points 8 and 9 of which have their source and drain form and wherein the P (+) - part of the layer 3, which connects the contact points 8 and 9, a control electrode of the transistor, while the other control electrode consists of layer 1. The entrances are through the Terminals 11-14, 13-15, 12-16 are formed, each of these terminals being covered by an aluminum layer Consists of tantalum layer.
Die folgenden Figuren der Zeichnung zeigen die verschiedenen Verfahrensstufen einer zweiten Ausführungsform des erfindungsgemässen Verfahrens. Bei der soeben beschriebenen Methode wurden zwei aufeinanderfolgende Maskierungen benötigt. Die ;jetzt beschriebene Methode ermöglicht die Verwendung einer einzigen Maskierung. Man erhält einen Transistor mit einer einzigen Eingangssteuerelektrode an der Unterseite des Plattchens.The following figures of the drawing show the various process stages of a second embodiment of the invention Procedure. The method just described required two successive masks. The method now described enables the Use a single mask. A transistor with a single input control electrode is obtained the underside of the plate.
109842/1638109842/1638
21133312113331
Das in Pig. 7 dargentellte Auogangsgsbilde besteht aus einer Silicinmaühicht mit (N+dotierung ICO, die mit einer P-dotierten Siliciumuohioht 101 mit einer Dicke .in der Größenordnung eineα Mikron bedeckt ist.That in Pig. 7 shown output screen consists of a Silicinmaühicht with (N + doping ICO, which with a P-doped silicon tube 101 with a thickness .in the Of the order of α micron.
Die Schicht 101 wiederum iat mit einer Schicht 102 aus einem während einer geeigneten Wärmebehandlung vollständig oxydierbaren Metall bedeckt, d.h. mit einem Metall der vorstehend angegebenen Gruppe,The layer 101 in turn consists of a layer 102 one completely during a suitable heat treatment covered oxidizable metal, i.e. with a metal from the group specified above,
In Fig. 8 ist die Schicht 102 mit einer metallischen Maakierungsschlcht 103 bedeckt, die gegen eine Wärmebehandlung beständig ist; das Metall ist beispielsweise Aluminium.In Fig. 8, layer 102 is metallic Maakierungsschlcht 103 covered against heat treatment is constant; the metal is for example Aluminum.
Das Ganze wird dann der Wärmebehandlung unterworfen (Pig. 9) , in deren Verlauf da3 durch die Maskierung geschützte Tantal unversehrt bleibt und mit dieser Maskierung einen metallischen Kontakt 104 bildet.The whole is then subjected to the heat treatment (Pig. 9), in the course of which da3 is masked protected tantalum remains intact and forms a metallic contact 104 with this masking.
In den nicht geschützten Teilen der Maskierung bildet sich eine Tantaloxidschicht 105 Tao0c. A tantalum oxide layer 105 Ta o 0 c is formed in the unprotected parts of the masking.
Man erhält so mit einer einzigen Maskierung einen Feld effekttransistor vom Verarmung3typ mit zwei Source und Drainkontakten 103 - 104 über dem Kanal P und einer Eingangssteuerelektrode N + auf der Unterseite des Plattchens.A field effect transistor is thus obtained with a single mask of the depletion type with two source and drain contacts 103-104 across channel P and one Input control electrode N + on the underside of the plate.
Wenn man einen Kanal mit N-Leitung erhalten will, muß man natürlich die Leitungstypen der verschiedenen Zonen umkehren.If you want to get an N-line channel, you have to you of course reverse the line types of the different zones.
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Man beaitat somit eine Methode, die e3 erlaubt, die Gestehungskosten von Sperrschicht-Feldeffekttransistoren herabzusetzen.One thus offers a method that allows e3, the Reduce production costs of junction field effect transistors.
Die Erfindung betrifft natürlich auch nach diesem Verfahren hergeateilte Feldeffekttransistoren.The invention naturally also relates to this method split field effect transistors.
109842/1638109842/1638
Claims (6)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7010340A FR2081249A1 (en) | 1970-03-23 | 1970-03-23 | Junction field effect transistors - using tantlum oxide dielectric and needing fewer masks |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2113831A1 true DE2113831A1 (en) | 1971-10-14 |
Family
ID=9052716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19712113831 Pending DE2113831A1 (en) | 1970-03-23 | 1971-03-23 | Junction field effect transistor and process for its manufacture |
Country Status (2)
| Country | Link |
|---|---|
| DE (1) | DE2113831A1 (en) |
| FR (1) | FR2081249A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2419019A1 (en) * | 1973-04-20 | 1974-10-31 | Matsushita Electronics Corp | METHOD OF MANUFACTURING A BARRIER FIELD EFFECT TRANSISTOR |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5124341B2 (en) * | 1971-12-24 | 1976-07-23 |
-
1970
- 1970-03-23 FR FR7010340A patent/FR2081249A1/en not_active Withdrawn
-
1971
- 1971-03-23 DE DE19712113831 patent/DE2113831A1/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2419019A1 (en) * | 1973-04-20 | 1974-10-31 | Matsushita Electronics Corp | METHOD OF MANUFACTURING A BARRIER FIELD EFFECT TRANSISTOR |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2081249A1 (en) | 1971-12-03 |
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