DE2113751A1 - Circuit arrangement for a high-speed, high-resolution analog-digital converter - Google Patents

Description

Circuit arrangement for a high-resolution analog-digital converter high speed

The invention relates to a circuit arrangement for a high ^ - resolving analog-digital converter with high puncture speed.

Regardless of the process for converting a Analog signal is applied to a digital signal provided that the components used, such as comparators, amplifiers, controlled attenuators, etc. the limit of their puncture speed operated, the fact that when increasing the resolution of the analog signal such a transducer becomes slower in its puncture. This can be explained by the fact that all occurring within the vendor Analog signals cannot change abruptly, but require a certain settling time. It should Settling time is understood to be the time that the analog signal needs to reach a stationary end value so close that the difference is less than the analog value that corresponds to the last digit of the digital signal, i.e. corresponds to the least important bit position. If the resolution of the analog-digital converter is increased, i.e. the analog signal becomes converted with greater accuracy into the digital signal, which is becoming longer, then the analog value, the corresponds to the least important bit position. This increases the settling time and the puncture speed of the analog-to-digital converter decreases.

VPA 9/110/0071 RH / Au

209840/0920

- 2

To circumvent this problem and a high puncture speed It has been proposed to maintain the resolution despite the high resolution, with the aid of several analog-to-digital converters connected in parallel evaluate several bit positions of a digital signal corresponding to an analog signal at the same time. For the same purpose has already been proposed, one bit position for several To evaluate analog signals at the same time. In both cases, however, the effort is very high. In addition, there is the second one Case that the achievable accuracy is limited to a certain value (approx. 8-9 bit) because the analog signal from stage must be passed on to the stage via delay elements or sample and hold circuits.

In contrast, the present invention solves the problem of a to combine high resolution with high puncture speed without significantly increasing the effort.

For this purpose, in a circuit arrangement for a high-resolution analog-digital converter with high puncture speed proposed according to the invention that several analog-to-digital converter stages are connected in parallel, each of which is preceded by a sample and hold circuit, the inputs of the Sample and hold circuits are connected to an input for an analog signal and each have a control input of the sample and hold circuits is connected to a control member which controls the sample and hold circuits so that the analog signal from the sample and hold circuits Query staggered over time and entered into the individual analog-digital converter stages staggered in time is that the outputs of the analog-digital converter stages continue to lead, in particular via a buffer memory each, to a main memory which has an output for a digital signal connected is.

VPA 9 / II0 / 007I '- 3

2098A0 / 0920

With such an analog-to-digital converter constructed according to the invention can be implemented with relatively little effort. «very high-frequency analog signals with high resolution in Transform digital signals.

An embodiment of a circuit arrangement according to the invention is shown in the drawing as a block diagram.

As an example, there are four analog-digital converter stages connected in parallel, whose internal structure is not essential to the present invention. They are in the drawing with 1 to designated. Their inputs are each via a sample and hold circuit 5 to 8 - symbolically drawn as a controlled switch, connected to an input 9 for an analog signal. the Control inputs of the sample and hold circuits 5-8 lead to a control element 1o. The outputs of the analog-digital converter stages 1 to 4 are each via a buffer 11 to H and above one controlled switch 15 to 18 each with a main memory tied together.

The control inputs of the controlled switches 15 to 18 lead to the control member 1o. The main memory has an output for a digital signal, this digital output 2o having, for example, twelve single outputs for a digital signal Has 12 bits.

The analog signal applied to input 9 is taken from the sample and hold circuits 5 to 8 interrogated staggered in time, for which purpose these are controlled accordingly by the control member 1o. Through this If the analog signal is offered to the individual analog-digital converter, levels 1 to 4, staggered in time. Processes any Analog-digital converter stage, for example 12 bits, then becomes at a certain point in time the analog-to-digital converter stage For example, just process the 9 bit of your input signal, while the analog-digital converter stage 2 is processing the 6th bit, stage the 3rd bit and level 4 the 12th bit.

. 2 0 9 8 4 0/0920 VPA 9/110/0071 - 4 -

The analog signals processed in this way then also appear as digital signals in staggered form at the outputs of the analog-digital converter stages 1 to 4. They are then preferably stored in the buffers 11 to 14 and via the Controlled switches 15 to 18 are transferred to the main memory 19 in a staggered manner. The appropriate control the controlled switch 15 to 18 takes place in turn via the Control element 1o. The digital signal can then be completely picked up at the output of the main memory 2o.

1 claim
1 figure

VPA 9/110/0071 2 0 9 8 4 0/09 2 U

Claims (1)

Claim Circuit arrangement for a high-resolution analog-digital converter with high operating speed, thereby characterized in that several analog-digital Yfandlerstufen · (1 - 4) are connected in parallel, each of which is preceded by a sample and hold circuit (5 - 8), the Inputs of the sample and hold circuits (5-8) are connected to an input (9) for an analog signal and each have a control input the sample and hold circuits (5-8) is connected to a control element (ίο) which controls the sample and hold circuits (5-8) so that that the analog signal from the sample and hold circuits (5-8) interrogated staggered in time and the individual analog-digital converter stages (1 - 4) is entered staggered in time, so that the outputs of the analog-digital Y / andler stages continue (1-4) lead to a main memory (19) via an intermediate memory (11-14) each, which has an output (2o) for a digital signal. VPA 9 / 11o / oo71 20984070920 Blank page