DE2102828C - Data receiver for distorted digital input signals - Google Patents

Description

The invention relates to a receiver for the detection of digital data bits from a distorted waveform having digital data bit information and inter-symbol interference containing input signals, consisting of a delay element for receiving the input signal, the output terminals of which are separated from each other by a delay of at least one data bit interval, and also a the delayed input signals and a corrected system output signal receiving correction circuit, an adder receiving the output signals of the correction circuit, a sample value taking sample values of the amplitude of the summed output signal of the adder in bit intervals, one serving to determine whether the sample value signal has exceeded or fallen below a certain amplitude value Threshold detector, which according to the determination of the correction circuit for a corrected system output signal returns.
A number of methods are already known.

31 4

around which are generated at low transmission frequencies on the input signal r '(t) and that em Vw-

Transmission path occurring distortions is intended to be more correct, which leads to the V = '

yaw. If, for example, the characteristics of a transferred signals with a preselected V ^e «™

transmission conduction is known, then it is possible to amplify factor G , and that the ^s « ^m £« ™ ^ ₁

occurring equalization by a corresponding 5 output signals of the amplifier and the to ι,

to compensate for the opposite pre-distortion. corrected input signals' «™ ™ * j * j. _Solid .

This means that the transmitted signal is so distorted. The receiver according to the invention is used ζ «r

is that the predistorted signal by the on the position of digital data bits from a m _[ its Vv'euen

Line occurring delay in a signal with the shape distorted input signal,. ^d «« Jj ^ * ^

desired wave phone., is converted. This to digital data information and a

However, the method is arf limited to the cases where it contains interference. In a ^ ° ™

di Kdt d transmission line in accordance with the time of the system is a low-pass filter

Method, however, the cases arf limited, in which interference ent ^^

the characteristics of the transmission line in accordance with the time of the system is a low-pass filter J stood and known what the noise components from the

To the duS Vereögerungen _au f a higher-removed input signal whose frequencies oterhrib tragungoleitung induced distortions to 15 of the bandwidth of the receiver ¹ ^ - ^ Ρ ΑΞί correct, are trans with other methods signal is then ^d ^ .e-caps used Verzogerun equalizer. A transversal diverter, which contains the signal by « ⁿ £ distorter, contains a delay line with taps number of bit intervals, and a plurality of multiplying circuits, of which the circuit then receives the ^" β each to a single tap the delay a ° signal and the ^{line-belongs in its waveform} J. But also transversal equalizers are trapped signals together with ^a . ™ limited in their use, because a strong transient signal, which comes from the output of the distortion of the signal n ^ can be compensated, feedback .st. ^ correction circuit without at the same time an attenuation of the then corrected output signal of the receiver takes place, so that there is a risk that the * s to create a correction signal, which the be . Signal is lost in the noise spectrum. The use of the already evaluated data bus «fdeparted by attenuators (see, for example, German intermediate symbol. Interferences. The On this Offenlesungsschnft 1487 784) appears otherwise created correction signal is then unfavorable because with the same only a delayed and non-delayed filtering is possible step-by-step. 3 "signal subtracted by essentially ^d " entire.

There is also a known SchV. Arrangement (see clearly contained in the signals ^ ¹ «^^ ¹ ^ see Offenlegungsschrift I 762 361), in which the referencing is to be eliminated whereby a *« 1 * α «grain impulse behavior of a The transmission channel is used to create a matched, delayed and filtered signal to create a correction. The partially corrected, undelayed. filtered signal to derive that-if it is with the received 35 signal then around a .Y ⁰ W * ¹ ^? ™ "i signal is combined - a recovery of the gain factor is amplified so that the linear separations enable transmitted data to be received in largely undistorted form between the various values d» and a cross. The correlation of this is stored with the received 4 <> then the output signal at the V ^^ ™ * J? ™ signaler, so that Impulse- partially corrected, filtered signal hums. behave. to get the transmission channel. The agent of the B.tfrequenz ablas »» the scan Querkorreiation Hadurch is achieved that each of the circuit w.rd ^{dM "d"} AusglingsagM ^ Sumimergerade received abtasteten data bits sampled with the circuit. A ^ ™ "« "^ * ^ ™" previously received converted signal digital multi-45 finally used to convert the * ™ & * & - is unu the i'products integrated over the time signal at the summing switch ™ 8 From this, a correction signal is then used to determine whether the scanned signal is over or passed by multiplying the measured pulse values with the data stored below a predetermined value and the products

can be summed up. This correction signal will then write 5 »drawings in detail. 1Here are subtracted from a received signal to be a part having the same reference numerals To form a correction signal that plots the output signal. It shows Qv ^ temimnulses with

of the system and the stored signal. Fig. 1 a representation «^ £ *" ™ ^{ριι | Μ8 with}

In view of this prior art, it is the associated, temporal purpose of the present invention to provide a receiver 55 F. G. 2 a pictorial representation of possible emplacements of the type mentioned in the introduction in such a way that "signals" start in a two-digit time interval even when _intersymbol intervals occur before a correction, ciima i _e in one

very good signal separation is possible. Fig. 3 possible receive ^ne ^ 'e / in one

This is achieved in that Zwe.-Z.ffer-Ze.t.ntervall ™ ch ^p asseren enes Ie ^ us, the input signal also the correction circuit to-6q of the receiving, the d ^ e ^ by the present invention, it rertete from ^

is hiert, whereby partially corrected delayed delay circuit for the in F 1 g. 4 input signals r '(tT) and a partially corrected receiver,

5 ^U 6

F i g. 7 a graphical representation of the reception usually results in the largest "intersymbol"

Characteristics of a second embodiment, perturbation involving the digit r / < affect

F i g. 8 is a block diagram of a second receiver adversely from previously evaluated digits </ "_" _di-t

embodiment , _{dt- 3} etc. In a receiver with a very low

F i g. 9 a block diagram of a circuit in which 5 error rate it is then possible to use these earlier digits

second receiver embodiment of FIG. 8 for decisions and the well-known pulse sampling

Corrected previous decisions to use values c to remove much of the "Inier ·

F i g. 10 a block diagram of a logical signal symbol fault to eliminate [s. Equations (1), (2

tion for the second, shown in FIG. 8 shown receiver and (3)]. A device in the inventive

embodiment, ₁₀ recipient removes this to previous decision-makers

11 shows a block diagram of a third belonging »IntersymboU disturbance. The two signal

guiding form of a receiver and samples r <-j and η are then transformed ir

F i g. 12 is a block diagram of a correction circuit for the third, in Fig. Education represented 11 ^r <'=''' + ^c -2dtu + c-, tf _(, (4) management form of a receiver. 15 ri = · · · + c- _t di + _t + c ^ i / i :, f c _o dt. (f>)

In Fig. 1 shows an example of such a pulse reproduction. The samples of the amplitude In F i g. 3 is a two-dimensional signal image of the reproduced pulse, which is represented in digit time intervals of r \ , and ri after the two signal intervals have been made are ... c- », C ^ ₁ , C ₀ , C ₁ , c" .. ., sampled values by a correction device in the manner shown in FIG. 1 is shown. The main _ao recipients have been processed. In contrast, the sample value of the reproduced pulse which corresponds to the one shown in FIG. 2 is now an evaluation of each digit is used, is C ₀ , applicable separation between the possible, for although one or more other samples d _t = 0 received signals and the possible, the reproduced pulse are used for </ <= 1 received signals performed; here we can; the entire received signal contains under as ^{at s} ' nd all possible combinations of the remaining »IntersymboU disturbance elements for different digits considered, an» IntersymboU disturbance. If a number of digits is a division line A in FIG. 3 is transmitted between the two or read from a memory, signal words are drawn in. The described then reads the / -th Sienal order supplies the optimal dividing line, which the r ^ -ΣkCkdi-k U) ₃₀ minimum distance between the received au 'signal and the dividing line to a maximum value where Ck is the Jt-th sample of the received Im - sets (namely the distance between the division pulse, i.e. the / th line read out from the memory and the possible received signal, which is a digit; the samples of the entire signal are closest to the division line). As a result, the maximum margin for the noise is obtained in the middle of the received digit time intervals 35, decreased. Because of the »IntersymboU interference, a simple equation for the horizontal Ab Each received signal value is dependent on a number of digital values of the received signal relative to the dividing line A values. To evaluate each received reads as follows:

Digit the receiver uses the received signal Y ₍ = r ' + Gri - η (6)

r (t) and a delayed replica of this signal 40 _W0De j '''

r (l - T), where the delay T is equal to a baud G = -cot & (7) (or digit time) interval. To evaluate the

The recipient uses / -th digit dt ri and r <-j, and / 7 the intersection of dividing line A with the

which the instantaneous amplitudes of r (t) or r! _, - axis and Θ the angle between the division

r (t-T) at the time of sampling for the evaluation 45 line un I is the r ' ,, axis. To delete this

of dt represent. These two samples are used on equation G and ri to get the best,

the samples of the reproduced pulses and straight-line division of the signal range duruzuzuzuführung.

related to the transmitted digit values as follows: In order to then highlight an error for the noise

Calling J ₁ J jj, the noise must be the received signal

Π-! = C-SiZi ₊₁ + c-jrfj + Corfi -! + Cidt-2 + c, rfi_3, (2) _{5o over the} line. If the signal is plus

η = c-jt / t + g + c-jt / i + x + c _o di + Cji / j-j + Ctdt-t. (3) Noise at the receiver input is reflected on the

is on the wrong side of the optimal dividing line,

It is assumed here that the characteristic then is not a simple reception

Samples of the pulse reproduction c_, until c _% are, catcher, which an error with the help of a decision

what is correct in the memory read application example 55 feedback circuit according to the described

was. Can avoid arrangement.

In Fig. FIG. 2 is a representative, two-dimensional diagram in FIG. The preferred recording of these two signal samples shown in FIG. The received data is presented. The distance between each axis represents a signal 9 represents a signal with a distorted waveform, the two instantaneous signal amplitudes r <- _t and η contains digital data information and »IntersymboU-Aus these two instantaneous signal amplitudes disturbance components. The filter IC is used to evaluate the recipient's number ώ. The small ones for attenuating the noise components outside circles and the crosses X represent possible received signal bandwidths without thereby representing the emp signals for dt = 0 or d _x = 1. The 65 captured signals are changed. Particularly in the case of zero values and the one values arranged in such a way that a read-out memory is turned with the sequence shown in FIG. 1 a separation and detection of not easily reproduced pulse shape has the filter can be guided. flat amplitude-frequency characteristic at fre-

frequencies between zero and about 250 kHz. Via ZeileinrichtungTaktimpulsc for the temporal sampling, 25OkHjE, the filter attenuation increases rapidly with this sampling increases with the Sprcher rotation decreasing frequency; synchronize points at frequencies above 500 kHz, at which the corresponding attenuation is approximately 30 db. For others the data bits were recorded. The sample value uses the filter in general above the 5 for the evaluation of the / th digit dt would then be flat bandwidth in which approximately 90% of the signal occur just before the apex of the energy contained, and increases rapidly Fre system reproduced pulse at dt [the part r (t) sequences above this bandwidth. belongs to dt] has reached its apex. More accurate

The output signal r (l) at the filter 10 is expressed, the optimal sampling time then roughly corresponds to a delay circuit 20 and a corio of the time at which a difference is fed to the reproduced correction circuit 30. The delay ^ - sampled pulse amplitudes of the F i g. 1 shows a circuit 20 in FIG. 4 represents the signal delayed by a maximum value. The sampling time can also baud time interval T without somehow changing the signal to be derived from a controlled, stable oscillator. At the same time, the digit dt must then be the one that evaluates syn signalers (z) and r {t ~ T) with the received bit frequency, which is chronized on the one.

output or output of the delay circuit 20 The externally derived time pulses are united

in Fig. 4 appear. The amplitude samples are fed to the pulse delay circuit 52, which the signals r (f) and r (t-T), which theoretically (not physically sets delay of these supplied time pulses, kaiisch) in the middle of the / -th baud time interval from around the To excite scanning device 50 and are taken to be η and η,. ao any delay in the received signal

The actual physical sampling occurs bc- to compensate, which has arisen while the knowledge has passed through the system after further operations on r (/) and signal. r (/ - T) , but it sets the sampling (or momen- Since the required delay usually exactly

tanen) amplitudes and are non-continuous and determined in advance in applications for off values that are based on an evaluation of the digit dt , as reading from memories', the pulse These two sample values can relate to the delay circuit 52 one simple conventional given pulse samples and the transmitted apparatus for delaying low frequency clock digit values, as previously represented by equations (2) pulses by a certain amount. In and (3) have been expressed. The correction data transmission systems, where the required interconnection 30 receives as input values the signals 30 delay with the channel changes, can have an author (/) and r (t - T) and a decision feedback system. Time recovery by synchronization signal. The decision feedback signal sieren a stable clock with the help of zeroing the receiver evaluation of the last received signals of the received signal are reached, genes number, which is explained in more detail below when an automatic time display is used. 35, a fixed time delay is used,

The signals r (t) and r {l-T) include portions of to obtain the sampling time, which is about c _o -c _u like pulses not only the evaluated number, but described above, to a maximum value set by various "IntcrsymboU - Malfunction. After the scan, the signal that the

When the decision feedback signal is fed to the subtracting circuit η 60, the value of the correction circuit 30 is processed, it is in 40 r _t ' + Gr',,. The subtracting circuit r / 60 subtracts converted signals which are modeled on almost the entire disturbance a fixed predetermined voltage value before the. In particular the "Intcrsymbol" - amplitude of the narrow pulse at the scanning disturbance, which is established from the digits evaluated earlier. The amplitude of the impulse that emerges is simulated. The simulated subtracting circuit / 7 at the time of the evaluation of the elements are then subtracted from the signals r (t) and r {t— T) 45 Men digit oct carries in order to obtain corrected signals r '(t) and r' (tT)

to accomplish. The moment amplitudes of these corri- Yt - r ', ., + Gn' - η , (9)

yaw signals in the middle of the i-th digit time

intervals are expressed by equations (4) and (5) where G is set to -cot © and θ is io. The procedure for performing this 50 F i g. 3 phase angle shown is. By means of a correction for earlier decisions, a comparison of equation (9) with FIG. 4 is explained below. The corrected signal r '(t) will then know how the device supplies the received signal in an amplifier 35 with a gain set to the value G in, the voltage Yi at the time of the evaluation of the digit dt ; transforms the signal r '(tT) . Here, the value Y _{t is} proportional to which is then fed to a summing device 40, 55 horizontal distance between the received output signal which supplies the following output signal: Signal used for evaluating the digit d _t

,,, τ \ λ r _r '(t \ m has been, and the dividing line in FIG. 3.

r (/ 'HWW- W Normally the value G is set permanently

A scanning device 50 scans with the top and calculated in advance. Due to the known transmission bit rate, the output at the 60 data which the summing device 40 reproduced by the system from. The reference clock pulses for the pulse and the baud frequency can be used to control the sampling time in general from the display of the signal range as shown in FIG. 3 received by the association's separate institution. If the turn of the equations, such as the arrangement described, for example in an equations (4) and (5), are drawn in; as rotating storage is used, the S can be ₅ can then approximately optimal, the Signalbenuch data bits feed normally be distinguished on the prepared points dividing line in the drawing, aufgezeichnet- in the memory rotation during the necessary settings of the values G and η reading out of the memory generated then an external can then query from this representation

of equation (7) and the associated definition of values G and 17 can be obtained.

The signal Kf is fed to a threshold value detector 61, whose threshold value is set to zero. If the signal Yi is positive, then the threshold detector generates a positive output pulse indicating that the digit is </ i - 1. If, on the other hand, the threshold value detector generates a negative output pulse, it can be seen from this that the digit di has the value dt = 0.

Usually the threshold detector generates an output pulse of one polarity for i / <0 and an output pulse of opposite polarity if </ (is 1. However, two different signal values V _x and V ₁ can also be used to represent the two binary digits.

In the F i g. 3 and 4, the values of G and 17 are set to the best possible division device ' ¹ "of the signal range. In order to then cause an error, the noise must bring the received signal over the division line. If the signal plus noise at the, receiver input on the wrong side of the optimal dividing line, then the recipient makes a mistake.

The subtraction circuit / 7 can be saved if the threshold value detector is on the voltage / 7 instead is set to the value zero. The SLnwciiweridetekior then becomes a binary room signal! generate (e.g. a positive pulse) when the output voltage at the threshold detector exceeds the value / 7; otherwise the threshold detector would be a binary mark * - generate a signal (e.g. a negative pulse).

In Fig. 5, the correction circuit contains a three-bit shift register 31 which contains the bit decisions of the threshold value detector as input values. Two summing amplifiers 32 and 33 receive the signals r (t) and r (tT), respectively. Resistors R ₁ and R _t are used to provide a voltage (or current) gain proportional to the displayed pulse samples C ₁ and C _1, respectively, of the FIG. 1 are. By means of resistors R ₃ , K ₄ and R _s , voltage amplifications are set which are proportional to _{the widths c 0} , r and c _{z, respectively.} The first bit signal at the shift register 31 is fed to the summing circuit 32 via the resistor R _1. The second bit signal of the shift register 31 is also fed to the summing circuit 32 via the resistor R _2. The value r '(t) is present at the output of the summing circuit 32. The first, second and third bit signals are fed to the summing circuit 33 via resistors R ₃ , R ₄ and A _{s, respectively.} The signal r '(t-T) is then present at the output of the summing circuit 33; \.

From equation (3) it can be seen that the feedback signal which is required to correct η or r (/) for the »IntersymboU disturbance Cirff-i caused by the previously evaluated digits dt-i and d _t - _t + c _t dt-2 . From Fig. 5 it can be seen that this signal is then subtracted by the buzzer amplifier 32 from the value r (t). Similarly, summing amplifier 33 subtracts the required feedback correction

cd + cd ~ + cd-

from the value r (tT) to get din VvW (ZT). These processes at the summing amplifiers 32 and 33 have the effect on the sampled signal Y that; lbe. as if Jer value η directly into the value r { and the value / ·; , is converted into the value η , instead of using partially continuous signals at this point [s. Equations (2) to (6)]. Although the circuit arrangement in front of the sampling circuit with

If the signals are partially continuous, only the instantaneous values of these signals are ultimately used affected by the sampling times.

The in F i g. The circuit shown in FIG. 5 was provided for the special case in which there are two characteristic pulse samples which follow the value c _0; here the value <· _{0 is} the main pulse sample which is used to evaluate each digit. If the value c is followed by n characteristic pulse samples, then the shift register is completed in this case to // - \ - 1 slaves, two signal samples then being used to evaluate each digit. The number of resistors that leads into each summing amplifier is then increased accordingly. In the general case the signal will

^LaClt '''■"' * ^V '« "' ■» + '" ^{V c} « ^rf «--i

subtracted from the value r (tT) and the signal

subtracted from the value r (t).

The delay circuit 20 in FIG. 4 must be an analog low-distortion signal or a digital device that approximates a slight distortion delay of an analog signal. The delay circuit should have an approximately linear amplitude-frequency characteristic and a approximately linear delay-frequency characteristic over the bandwidth of the characteristic signal frequencies own. In Fig. 6 is one such delay circuit shown in the form of a bridge circuit. The transfer function of this bridge circuit reads:

whereby

U) _n

+ ι

ω η

ω »

l / ■ * y L

tr ^and

LC run

"I"

is.

The designations L, C and R correspond to ii F i g. 6, ζ is eil “damping factor, co“ is the “interruption * frequency”, and K represents a constant. If the values of the elements L and R are chosen so that the factor £, = 0.7, then the phase curve is largely linear from a frequency range ω = 0 to ω = ω », and the amplitude is constant within this« frequency. If the frequency ω _η ai is then set to be the most characteristic signal frequency or higher, the signal is delayed with negligible distortion. The maximum · is by a step (the bridge circuit) erreichbai ^v ^ ögerung then ^ -, where / "," d most characteristic Fri-iquenzkomponente is. When turning the read-only memory, where the most characteristic frequency is around 250 kHz, the ma *

Π ^ϋ 12

times, achievable by a stage delay changes in the number of stages, which in turn

about t microsecond. For a signal baud of the length of the trailing edge of the system pulse

The duration is 1.4 microseconds.) For example, it depends.

, η ",. ,. In Fig. 9 is a correction circuit, for example

the value «., set to _QJ , and it is displayed on two ₅ i | _{t> in the four} characteristic c-values

Steps a delay of 1.4 microseconds will be followed by _{the value c 0.} The digits evaluated earlier

suffices. The entries in the shift register act for each delay stage, so that there is one

stronger than driver stage, around a ground or given digit </ < is evaluated, the last five

to prevent performance and thereby the preceding digits </ <- until dt- _& are in the

to change the function of the bridge. i ° shift register are located. The resistors A ₁ to A ₄

The execution of the calculations can instead be set in such a way that voltage gains c,

on the horizontal distance Y _x to the dividing line up to r ₄ , with these c values representing the four

are also based on the perpendicular distance U _t , as represent given pulse samples based on the

in Fig. 3 can be seen. When the adjustments, value c _? Follow. By means of these resistances and the

To get the optimal dividing line, correctly 15 summing amplifier 34 gets the signal

are set regardless of whether they are set to,. _H,,,,

based on the value Y ₁ or Ut , the best implementation < ^Λ ' ^{f αΛί} ' ^ ^{3+ c} * ^dt <

under the combined effect of the »IntersymboU- subtracted from the value r (t) to give the value / · '(/)

Interference and noise achieved when only two received. In the same way, the resistances are Ä _s

Signal samples (two signal-space dimensions) ^ao to R ₀ set in order for the gains C ₀ to c ₄

used to evaluate each digit. Provide the proportional voltage gains.

Implementation is best on a receiver These resistances subtract in conjunction with

possible that the continuous signal via a summing amplifier 38 one of the signal

2-baud time interval for performing each Ent- * _{d + d + d +} j _{{ rf}

divorce stop. ^a 5

The mentioned approach for establishing a proportional voltage from the value / · (/ - T) to um

To obtain dividing (or dividing) line with two signal r '(<- T). The resistors in FIGS. 5

Room (or area) dimensions can be increased by one and 9 by amplifiers with preset

Number of signal-space dimensions and by one amplification gain, with each gain

number of separation planes or hyperplanes increased 3 ° proportional to the c-value, which is below the corresponding

will. The number of dimensions is then shown in the figures, corresponding to the resistor R

the number of signal samples that is to be evaluated.

each digit can be used. In Fig. 7 is a second signal r '(t-T) in FIG. 8 shows the summation waveform that is fed to binary signals with two circuits 72 and 73. The signal r '(t) dimensions and two dividing lines A and B is applied to amplifiers 70 and 71 with gains 6'. In Fig. 7, in particular, signals are shown or C ₂ fed. The output of the amplifier 70 is set within a 27 * -second interval is to be received at the input at the summing circuit 72, where T is the time per received together with the output of the amplifier 71 and is 1.4 microseconds when using the leads which is the summing circuit 73 as an input to the first read-only memory which is led for display 4 <>.

purposes in this disclosure. The desired angles θ and γ in FIG. 7 will be

Division line A forms an angle Θ with the axis calculated in advance or in some other way.

r, '_ . "while the dividing line B determines an angle γ with; the gain values C ₁ and C ₂ dei

the axis / ·, ', forms. The dividing line A intersects FIG. 8 are equal to —cot © and —coty. The C ₁ and

the r \ , axis at point 77, while the division * 5 C ₂ values can be obtained by preparing a signal

line B intersects the r, ', axis at point tj. area representation can be obtained, as for example veisi

If in Fig. 7, the received signal plus g in F i. 7, where the two dividing lines are drawn in this way

Noise in the area to the left of the two lines A are that it best suits the signal range for dt = (

and B falls - then the obtained digit will separate as dt = 0 from the signal range for <tf < = 1; the hints

interpreted. Otherwise, the obtained digit 50 β and γ can be measured in the illustration

interpreted as dt = 1. From the position of the signals in the output of the summing circuit 72 becomes the Ab

F i g. 7 it can be seen that a better separation of the sensing circuit 74 is supplied, which the amplitudi

Signal range is obtained when two lines A and B samples this signal once per baud. At the same time

Used in place of any single dividing line, a sampling circuit 75 samples the output de

werdui. ^5S summing circuit 73. As with the previous ii

In Fig. S is a basic version for the in F i g. 4 described amplifiers are the Abtasi

F i g. 7 operation disclosed with two division line values controlled by reference clock pulses, which bycl shown. The data signal obtained is fed to a specific pulse delay circuit 79

Filter circuit 10 supplied to the in F i g. 4 may be hesitated. The scanning control is then such

provided filter circuit corresponds; from here is sent ^6o that the values c ₀ to c _t nearly to a "

the signal to a delay circuit 20 and set to maximum value, this c value a correction circuit 30. The correction - the sample values of the in FIG. 1 illustrated system circuit 30 also receives the decision impulse.

Feedback signal The latter is changed in the correcting circuit 36 subtracted from the gate circuit 30 and a fixed voltage η and r (t-T) subtracted from the signals r (l) ⁶ 5 output of the sampling circuit 34, by the Signals r '{t) and which are equal to the distance from the origin in FIG. r '{t-T) . The correction circuit 30 is the same as in FIG. 5 up to the intersection of the line A with the r, L, axis, apart from possible ver. As soon as there is no noise, it is off

13 Si 14

output voltage ampUtude at the subtracting-n-switching shows the baud time, and creates three output tags 36 (the corrected Aotastamplitude) proportional signals r {tT), r {t-lT) and γ (/ - 3Γ)). For each of the distance U _u namely the horizontal distance baud delay in the delay line of the signal obtained from the lines, two bridge circuits of FIG. 6 are used independently, which of the signals in FIG. 7 is received Der 5 Each of the signals r (/), r (f-D, r (r-2r) and r (f-371 i / i threshold detector 76 generates a positive will of the correction circuit 110 together with an output pulse when the signal amplitude U ₍ plus decision feedback signal supplied. Noise is positive; on the other hand it generates a signal-space dimensions. For purposes of

The subtracting circuit 37 in Fig. 8 subtracting 10 of the illustration may be two characteristic pulse

From the output of the sampling circuit 75, a sample value follows _{the value C 0.} The previous ones

Signal rj equal to the distance from the origin digit decisions at the threshold detector

to the intersection of line B with the r / _, - axis in F i g. 11 reach the shift register 45; to a

in Fig. 7 is. The output amplitude of the signal-given time are the last five

pulse at the subtracter-rj circuit 37 is pro j ₅ digit decisions d _t - _x , «Ze- ,, t / 1-3, di- _A and dt- _s in

proportional to the distance from the origin to that of the shift register 45. The resistors A ₁ to A ₅

O intersection with the r /, axis. The K-threshold are set so that the gains match the values

value detector 77 generates a positive output _{- c s} to c_ _{2 are} proportional. In connection with these

pulse when the signal amplitude V _{1 is} positive; A summing circuit41 subtracts resistances

on the other hand it produces a negative output 20 a voltage proportional to pulse.

At the same time, the (/ threshold detector and c- ₂ </ f-, + c ^ di-i + r _o </ j- ₃ i adi- _A + c _a </ <- _& the K threshold detector 77 of the output Logic-

circuit 78 each have a pulse. The output is, from the value r (t-3T) to get / - '(/ - 37 ").

Logic circuit 78 is used to evaluate each result. The summing circuit subtracts in a similar manner

hold digit d _t based on the polarities of these 42 in conjunction with resistors R _e to A ₉

two pulses to the {/ threshold detector and to a voltage proportional to

the K threshold detector. call the obtained signal _{d + d + c} ^ _di _ _{3 +} ^ _{4 f} plus the noise on the left rope of the two

Lines A and B , then these two polarities are 30 of the value r (t - 2T) to get r '{t -2T) ,

negative, and the output logic circuit becomes dt - 0 The resistors A ₁₀ to A ₁₂ combine with the

decide. If these two polarities are not negative summing amplifier 43 subtract a voltage,

are then the output logic circuit dt = 1 which is proportional to

decide. . , j, j

In Fig. 10 is a schematic block diagram 35 ° '* * * ³

of output logic circuit 78 is shown. An AND- is, of the value r (iT), while resistors A ₁₃

Gate 80 receives output signals at its inputs and A _{14 is} combined with a summing amplifier 44

the threshold detectors 76 and 77. The output has a voltage proportional to

of AND gate 80 is assigned to a gate 81 and a _c j , _{c d (}

Inverter circuit 82 is supplied. The voltage source 40 11 **

84 has two outputs V ₁ and K ₂ , which is on gate 81, of the value r (i) to obtain r '(f). From the

or 83 are created. The gate 83 also receives equations (1) to (5), it results that the correction

the output from the inverter circuit 82. The off for the previous decision circuit the four

gates of gates 81 and 83 are then together - signal mappings r (f), r (f - T), r (t— 27 *) and r (r— 3T)

switched to form the system output. If 45 corrected for the entire "intersymbo disorder that."

during operation the two threshold value detection is based on the previously evaluated digits, if

gates generate an output signal, then that opens a given digit d _(is evaluated. Here is

AND gate 80 the gate 81 and leaves a span of interest that this correction process is not nui

voltage V _x through to the output. When considering the pulse value following the value r, this voltage represents

then d _v = 0. If one or both threshold value samples occur, but also with the

detectors do not generate an output signal, then value c ₀ opens previous samples,

the inverting circuit 82, the gate 2, allows a span. The r '(t- 37> signal in Fig. 11 becomes immediate

Voltage V ₂ to the output and represents di − 1. A summing circuit 114 is supplied. The signal

Instead of the voltages V ₁ and K ₈ , r '(t-IT) can also be used in the summing circuit 114 via a

a negative and a positive pulse used 55 amplifier 113 with a set gain Eq

are fed to a binary space or a binary. The Signa! r '(tT) becomes the summing

Marking or vice versa. circuit 114 through an amplifier 112 with a

In Fig. 11, a receiver embodiment is applied to adjusted gain Gl. The Signa

shown, the four signal-space dimensions (four r '{l) is the summing circuit 114 via a

Signal samples for the evaluation of each digit) 60 stronger 111 with a set gain G2

used together with a divisional hypocrebcne. fed. The output of the summing sound wire

A filter circuit 10 receives the data signal 9 and a sampling circuit 116 fed to the output

lets the signal after filtering become the delay signal of the summing sound at one clock frequency;

line 100 and to the correction circuit 110 through. scans through the Taklimpiilse of an external

The filler cladding 10 is the same as in FIGS. 4 65 source is determined. Hei application of a pulse control

and 8. The output signal at the filler sound 10 delay, the Taklimpiilse are delayed and here

denotes the value r (i). The delay line 100 introduces delays in deir for various signals

delays the signal by a multiple of the time T, where 7 reaches * system; this largely eliminates the opli

(ΰ

15 16

Male sampling control is achieved in which C ₀ to C ₁ approximately then these calculations can even be set to a maximum value in advance. The output carried out and the settings in advance of the sampling circuit 116 will be set to a threshold value rather than when it is supplied by the hardware detector 118 , the value of which, set to rj , is determined in the receiver and is automatically entered. 5. In this case the subtraction circuit, the calculations are usually carried out by an iterative process with the aid of a computer, as shown in the earlier receiver designs. The simplest one has been left out and the threshold method is to set all G values and the value η detector to π instead of zero. If the input voltage Y _{of the threshold value io setting exceeds the value π due to low growth rates in the detector, darn the direction in which Y _f increases so long, the threshold value detector generates a positive pulse, which d ₍ = 1 until Yt stops increasing. If then each indicates Em. Otherwise, the threshold value setting is set once and in the following all detectors generate a negative pulse indicating d ₍ = 0. Settings are set several times, then The output of the threshold value detector, which represents the output signal of the system that can be almost optimally adjusted, will be reached on the previous one.

decision correction circuit 110 described above. Once the hardware is established, there is another

fed back. Adjustment method in it, experimentally one

To be made on the basis of the gain settings G and setting, whereby an »eye conflict

the threshold value detector setting π is a hyperao ration «representation of the signal Y ₁ can be observed.

plane created in four-dimensional signal space. If each setting is made so that the

Voltage Y ₁ , on which the / "th digit decision opens the" eye configuration "to a maximum

based, sets the distance from the / -th received, and if after that all settings

Signal (after correcting the previous digits a few times, then also-

divisions) in the separate from the signal space 25 if optimal settings are achieved.

Hyperplane, this distance being parallel to the

rj 'axis is measured. In the case of more than two right distance from the received signal to the

Signal space dimensions and any system hyperplane separating the signal space. Then will

impulse behavior is the calculation of the gain the G settings direction cosine of a normal setting G and the value 17, which is the optimal 30 times to this hyperplane. If an opposite polarity

Separation hyperplane results in less long. If signaling is used, then the input

the system impulse behavior is known in advance, position r / can be set to zero.

For this purpose 4 sheets of drawings

Claims (6)

Patent claims: 1. Receiver for the detection of digital data bits from a distorted waveform having digital data bit formations and inter-symbol interference containing input signals, consisting of a delay element serving to receive the input signal, the output terminals of which are separated from each other by a delay of at least one data bit interval, furthermore one of the delayed input signals and a corrected system output signal receiving correction circuit, the output signals of the correction circuit receiving adder, a sample value of the amplitude of the summed output signal of the adder in bit intervals taking sample value extraction circuit, the determination of an overshoot or undershoot of the sample value compared to a certain amplitude value serving threshold value detector, which according to the determination of the Correction circuit returns a corrected system output signal, characterized in that the input signal is also fed to the correction circuit (30, 110) which, from the corrected output signal, generates a plurality of normalized i: deformed waveforms corresponding to the intersynbolkc components, one of these normalized waveforms from each of the delayed inputs; igssignale r {t-T) and the input signal r (t) is subtracted, whereby partially corrected delayed input signals r '(tT) and a partially corrected input signal / ·' (/) are generated, and that an amplifier (35, 70 , 71, 111 to 113) is provided, which amplifies the partially corrected signals with a preselected gain factor G , and that the summing circuit (40, 72, 73, 114) the output signals of the amplifier (35, 70, 71, 111 to 113) and of the partially corrected input signals. 2. Receiver according to claim 1, characterized by a subtracting circuit (60) between the sampling circuit (50) and the threshold value detector (61) is connected, and through which the Threshold value of the threshold value detector from the. » sampled output signal is subtracted and the Threshold of the detector is set to zero 3. Receiver according to claim 1 or 2, characterized in that the decision correction circuit (30) contains the following devices: a delay device (31) to receive a corrected system output signal, the delay device having a plurality of equally spaced output taps and an attenuator (R ₁ to R _e ) which is connected to each delay line to provide a signal at each tap which represents a component of the input signal distorted in its waveform, a summing circuit (32, 33, 34, 38) for summing the tap signals by a normalized signal and subtracting the normalized signals from the delayed input signals and from the received input signal to provide partially corrected delayed output signals and a partially corrected input signal, respectively. 4. Receiver according to one of claims 1, 2 and 3, characterized in that the amplifier has a first and a second amplifier (70, 71) for the predetermined gain (G ₁ , G ₂ ), to amplify each of the partially corrected signals includes that the summing circuit a first and second summing circuits (72, 73) for amplifying the output signals at the first and second. ' Amplifier that contains the sampling circuit first and second sampling circuits (74,75) for amplifying the amplitude of the summed signal at the summing circuits in the bit interval, and that the threshold detector includes first and second threshold detectors (76,77) to determine whether the sampled signal at the first and second sampling device is above or below the first and second predetermined angle values lies and whether an amplitude value and ao a logic circuit (78> includes the output signals from the first and second threshold detectors and an output signal having a first Value provides if the output at one or both detectors is below the predetermined value the value is, and whether there is an output signal with a supplies second value if the output on both threshold detectors is above the first and second predetermined value. 5. Receiver according to claim 2 and 4, characterized in that the subtraction circuit contains separate circuits (36,37) between each sampling circuit and each threshold detector are switched and the threshold value of the threshold value detector of the scanned Subtract the output signal and set the threshold value of the threshold value detector to zero. 6. Receiver according to one of claims 1 to 5, characterized by a low-pass filter (10) for Receipt of digital input data, the output signal of which is a filtered input signal of the delay circuit (20,100).