DE2052087A1 - Electric display device - Google Patents

Description

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"Electrical Display Device".

The invention relates to an electrical

Display device with a matrix of image-generating elements each containing at least one electrical display element, that between a leader of a first group with the name row leader and a leader of a second group with the Name column conductor lies, with at least a number of row conductors with outputs of a row selection circuit is connected, and wherein at least a number of the column conductors with outputs of at least two working in parallel Register is connected.

An electrical display device of the above type is described in U.S. Patent 3,021,387 . In this arrangement , the iconic

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lowing elements of a combination of a red, green and blue electrical display element, each via its column conductor with an output of another are connected by three registers working in parallel and fed by red, green and blue video signals. The ^ corresponding electrical display elements, for example the red elements, of the respective image-generating elements along a row conductor are connected to other outputs of the same register. A favorable relationship between the write-in and read-out times of the registers is obtained by the input and output signals of the register switched to a second set of registers.

The invention aims to provide a new method for maintaining such a favorable ratio create.

For this purpose, an electrical display device of the type mentioned above has the characteristic that the column conductors corresponding electrical elements at least two-P he imaging elements along a row conductor, each with an output of another of a corresponding number in parallel working registers are connected.

An electrical display device can, for example, have a number of 5x7 matrices of gas discharge cells contain as electrical display elements, which small matrices each for displaying only one alphanumeric Characters are suitable. Several similar small dies can be used around a die structure or a

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Form matrix of larger dimensions that are suitable for this is, at the same time, a relatively large number of alphanumeric To reproduce characters. A large board can have a 200 (row) χ 200 (column) two-dimensional Matrix of gas discharge cells included. Assuming that every drawing area of this great violent 6 χ 8 = 48 cells, of which 5 χ 7 = 35 are active cells for the formation of the characters and of which the rest Cell Spatien are used for spacing adjacent characters and lines of characters, so 25 lines can be added 33 alphanumeric characters (825 characters in total) can be displayed on the board at the same time.

The words "Row" and "Column" are just that uses the coordinate lines of the luminous elements, which form the two-dimensional matrix of an electrical display device of the type described, to indicate. Either of the two groups of coordinate lines of the elements can are referred to as "row" elements, in which case the elements of the other group are referred to as "column" elements will. The two groups of coordinate ladders which form the intersections become "row" ladders in a corresponding manner and called "column ladder".

A control circuit for an electrical Playback device of the type described is necessary to provide the device with control signals that are suitable for allowing the luminous elements in the arrangement to light up selectively in order to achieve a visible display

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to create alphanumeric characters. The selective control of the light elements for visible reproduction can there-. done by that each row of elements with the row conductors in a repetitive scanning cycle supplied control signals controlled, and thereby, that selected column conductors are supplied with drive signals during a row drive period, wherein the selected column ladder then those elements in

* are assigned to the series that represents a part of the Make characters. The columns are controlled by means of coded electrical signals corresponding to the characters to be displayed Signals determined. Only those elements light up which have row and column control signals at the same time are fed. Assuming that a number of lines, each with a number of characters, are reproduced must be, and that each line of characters extends over a few rows (e.g. 7) of light elements.

^ stretches, it should be evident that by the fact that the rows are controlled one after the other during the scanning cycle, the characters of each line are built up in rows and that consequently the different lines with characters can also be built up one after the other. With a sufficiently high scanning speed simultaneous display of a number of lines of characters will result.

For good playback using this repetitive defrost cycle (hereinafter referred to as "Row-Auegabeverfahren" is called), is an image

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repetition frequency of 50 Hz to avoid a flicker effect desirable, i.e. the matrix becomes 50 χ per second scanned in rows. For a matrix of 200 χ 200 elements, a row sampling frequency of 50 χ 200 = 10 kHz (8.75 kHz) required. That means the sampling time of this series is 100 µs (114 / US) during which 100 / us each element to be controlled in a row if possible must remain activated for a long time in order to achieve maximum luminance. When using gas discharge cells however, at least -10 / us of the sampling time of the series of one Self-delay claims which delay occurs before the discharge of a controlled cell is ignited, and from the remaining 90 / US during which the cell is driven can remain, some / US are to fill a column register with coded electrical signals for selective Control of the columns required. So that the column activation time is kept to a maximum, the time to fill the column register can be, for example, 10 / us (11.4 / US), so the actual column renewal time 90 / US, which means that due to the inherent delay, the "on" time of the cells is only 80 / tie. This means that if the column register was coded during the 10 / us intended for this purpose electrical signals for the column control filled a step or clock frequency of 10 χ 200 = 20 MHz is necessary. In practice, this clock frequency can do something be reduced because only 160 active columns and 175 active columns

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Rows of cells for character formation are available because the other rows and columns of cells form the above-mentioned spatial bands. The parenthesized alternative values in the above part of this scan refer to this smaller number of rows and columns with active cells. A reduction in the clock frequency can be obtained by using two column registers alternately so that each total sampling time turns to

ψ Filling of a column register with regard to the selective control of the cell columns is available during the subsequent scanning time of the row, while the other column register accomplishes the selective control of the cell columns during the current scanning time of the row, which columns are filled during the previous scanning time of the row . By using two column registers at a lower clock speed, the control circuit can be operated with cheaper logic circuits (e.g.

^ wise DTL's) instead of more expensive logic circuits (for example TTL ¹ s), which more expensive circuits would be required in the case of a column register operating only at a higher clock speed. The use of two column registers in this way means, however, that the number of required bit positions in the register is twice the number essentially used for column control.

According to the invention includes a control circuit for an electrical display device of the type described above, a column register circuit which is used for

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Reception of groups of coded electrical signals is set up, the signals in successive groups Respective groups of columns to be controlled belong to, the signals in each group in parallel to the column register circuit are fed, which column register circuit is stopped by clock pulses from a control circuit It can be said that the signals in each group are shifted in parallel through the column register circuit, namely to the column actuation points for the columns to which these signals belong. In this way, the column register circuit be filled with a clock speed that is only - - times the clock speed, the would be required to sequentially fill the column register circuit with coded electrical signals.

According to the invention, the column register circuit preferably consists of a number of discrete registers each with a number of bit positions for control only 1 / n times the number of columns (where η also represents the number of discrete registers) and where each discrete register receives only the coded electrical signals belonging to the columns to be controlled, which signals for each Registers are different and where the discrete registers are different from the. Clock pulses of the control circuit in parallel can be written step by step so that each of these registers are filled with coded electrical signals can.

The discrete registers can be set up in this way

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that only one register is available for every possible column required for a character area (e.g. 5 in a 7 ^ 5 character area) so that encoded electrical signals for only one row of a character area as mentioned above form a group and are brought into the discrete registers together, that is, only one signal by only one clock pulse in each register _T

An embodiment of the invention is shown in

h drawings and is described in more detail below. Show it:

1 shows a schematic front view of part of an electrical display device,

2 shows a block diagram of an inventive Control circuit for the electrical display device according to Fig. 1,

Fig. 3 is a block diagram of a circulating memory for supplying a character generator adapted to the circuit according to FIG. 2,

FIG. K shows the time relationship between pulses in the circuit arrangement according to FIG. 2,

Figure 5 is a block diagram of the column shift registers the circuit arrangement according to FIG. 2,

Figure 6 is a block diagram of part of the character generator in the circuit arrangement of FIG. 2.

The electrical display device shown in Fig. 1 shows a 200 χ 200 two-dimensional matrix with Luminous elements, such as gas discharge cells. If every character

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area of this matrix contains 6 χ 8 = 48 cells, of which 5 x 7 = 35 are active cells for the formation of the characters, and of which the remaining cells are spaces for spacing Adjacent characters and lines with characters lying one below the other, this matrix can contain 25 lines to 32 alphanumeric lines Play back characters (800 characters in total).

In Fig. 2, the letter M is a 200 χ Matrix with gas discharge cells indicated. Each cell (40,000 in total) has an anode and a cathode connected to a Row conductors RC and a column conductor CC are connected. Two hundred row conductors RC form one row of coordinates for the matrix and two hundred column conductors CC, the other. Each cell in the matrix can be controlled simultaneously of the relevant row and column conductors between which the cell is located are made to light up. So will For example, from the three specified cells c1, c2 and c3 of the matrix M, the cell c1 by Ansteuerungssxgnale, the a row conductor RC199 and a column conductor CC3 will light up. Some row and column conductors do not need to be controlled because, as already mentioned, the cells form bands of space in a drawing area. Thus there are only 175 effective row conductors, as shown in Figure 2, of which row conductor RC199 is the last is, and only 160 effective column conductors, of which the column conductor CC 199 is the last. This number of effective row and feeders is also related to the fact that in the present example it is assumed that with

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of rendering 32 characters per line are obtained and not 33 »which would be the maximum possible number in this example. Control signals for controlling the row conductors RC are supplied alternately in a repetitive sampling cycle from a row shift register RSR, which is operated cyclically step-by-step by row pulses of 8.75 kHz supplied to its input. The control signals are fed to the row conductors RC ™ via anode control amplifiers ADA. The cycle speed for each row conductor RC is thus 50 Hz, which is sufficient to avoid a flicker effect in the luminance of the cells and the row scanning time is then '[' 1h / us.

Control signals for controlling the column conductors CC are transmitted via the cathode control amplifier C.D.A. of a Column Shift Register C.S.R. delivered. The task of the Column Shift Register C.S.R. is, certain column ladder CC depending on the particular fc character to be formed for display. This is done using the column shift register C.S.R. alternately fed by data referring to jode Row of cells and this data is then transferred in parallel from the column shift register C.S.R. as control signals these column conductors, which belong to the relevant cells of the row to be controlled, supplied. This cell will be then activated when their row from the row shift register R.S.R. is controlled.

The column shift register C.S.R. is with data from a character generator CG. filled, which was

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running memory R.S. with coded characters to be reproduced electrical signals is fed. The coded electrical signals form from a keyboard K (or from a tape reader or computer) received input data in the form of a 7-bit word per character. This input data per character are stored by the memory R.S. received in parallel and from it via the outputs 1L to 7L from the character generator CG. read out in parallel. The R.S. is made by clock pulses at a frequency of 2.8 MHz, which are also used to control the column shift register C.S.R. operate gradually. The data output of the character generator CG. to the column shift register CS.R. is through a row scanning register S.R. regulated, which is gradually synchronized with the R.S.R. from the series pulses of 8.75 kHz. The row scan register S.R. supplies successive signals at the outputs SR 1 to SR7 Groups of coded electrical signals to control a number of cells that are consecutive Character one of the column shift register C.S.R, to be read out Line of characters, while the character generator for each of these characters from the circular memory R.S. Input data receives. In each group the coded electrical Signals to the column shift register CS.R, in parallel fed, and in it under the influence of the clock pulses of 2.8 MHz after the relevant column positions in parallel in steps postponed. Filling the column shift register CS.R. for only one line of 32 characters required 12, us,

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during this period of each row scanning time clock pulses are fed to the column shift register CSR via a gate amplifier GA which is permeable for 12 / US of the ~ \ ik / us. The column drive signals from the relevant column positions of the column shift register CSR are fed to the cathode control amplifiers CDA, which are transparent for 100 / US during each row scanning time, the clock pulses being suppressed in order to output drive signals to the relevant column conductors CC. This is 7 x per line repeatedly to see the characters and then the lines of characters are built up line by line rows. All this with a frequency of 50 Hz to enable a visible reproduction of the selected characters.

The circulating memory RS is shown in more detail in the block diagram of FIG. The circular memory contains 25 groups, which consist of seven shift registers 1S1 ... 7S1 to 1S25 ... 7S25, each of which is a 32-bit circular ψ memory register. Each of these 25 groups of shift registers is used to store input data against a different one of the 25 possible lines of display characters on the board: corresponding bit positions of the seven registers in each group are used to store input data in the form of a 7-bit word used against each of the 32 possible characters per line. These circular shift registers are all controlled in parallel by the 2.8 MHz clock pulses and the output voltages from their 32nd bit locations are fed to separate gates of 25 groups of gates 1G1

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7G1 to 1G25 ... 7G25 supplied. These 25 groups of gates are opened alternately in an always returning cycle by a line scan shift register LSSR, which register is controlled by line pulses with a frequency of 1.25 kHz, so that successive output voltages are supplied to the read command lines 1R to 25R. The output voltages of the corresponding gates of the 25 groups are jointly fed to the NOR gates NG1 to NG7, the outputs of which form 7-bit words on seven output lines IL to 7L which correspond to characters to be displayed and which are fed to the character generator for selecting the appropriate character, such as will be explained below. The points in time at which the successive 7-bit word signals appear on lines 1L to Jh in the operating cycle of the electrical display device determine the position on the table of the characters to be displayed to which these signals correspond. The shift register LSSR is controlled only at 1/7 the row scanning speed of the display on the panel because, as mentioned above, seven rows of cells are required to build one character. The shift register L »SSR is reset by reset pulses of 50 Hz during each raster period of 20 mS.

An alphanumeric keypad K is supplied for supplying input data consisting of 7-blt words for the characters to be displayed. A 7-t ⁾ ifc word for the circular memory is the same via the lines 1L ¹ to

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7L ¹ supplied from the key panel K, with corresponding circulating memories in each of the 25 groups being connected jointly to separate lines 1L ¹ to "JL * ^1. The key pulse K also supplies X pulses to determine which corresponding bit positions of the 32 possible Digits must occupy a 7-bit word input data. These X-pulses control a 32-bit X-position register RX, which supplies a Y-pulse once per control cycle. The Y-pulses control a Y-position register RY depending on the number of X pulses supplied by the key panel K, the X position register RX assumes an end position which identifies the bit position of a group of circular memories and indicates which position must be occupied by the input data from the key panel K and the Y position register RY takes an end position which identifies the relevant group of circulating stores. An output signal from the register RX in the end position is fed to a comparison arrangement CO. Output signals jed The bit position from a 32-bit position identification register RI are also alternately supplied to the comparison arrangement CO. If an output signal from the register RX and an output signal from the register RI coincide in the comparison arrangement CO, the comparison arrangement CO delivers an output signal which is fed jointly to a group of 25 ports GL 1 to GL25. One of these gates GLI to GL25 is already prepared in its end position by an output signal from register RY, so that this gate opens so that an output

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signal on one of the 25 write command lines 1W to 25W is delivered. The input data into the relevant group of circular memories at the corresponding bit positions, such as this from the register RX are identified, enrolled.

The register RI is controlled via a converter IV by the clock pulses of 2.8 MHz. The reacted and unreacted clock pulses are shown with the waveforms a and b in Fig. K. When new input data have to be written into the circular memory, the relevant bit is written into each circular register, one clock pulse after the previous data has been read out. The new data is read out 31 clock pulses later. The clock pulses fed to the identification register RI are identified so that read-out and write-in data appear separately. If, for example, old data is read out at clock pulse 1 and new data is written in at clock pulse 2, the new data is available at the next clock pulse 1 and can be read out half a clock pulse later. This is c by the Wellenforraen, d, e, and f shown in Fig. K. Waveform c "represents the second bit position of the register RI and waveform d the first bit position. Waveform e represents new data that is written into the first bit position from a write command line and waveform f the new one Data output on a read command line 31 clock pulses later, provided that all

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Registers work on the positive edges of the clock pulses. The register RI is every row period from the row pulse • sen of 8.75 kHz reset.

Fig. 6 shows a schematic representation of the character generator (CG. In Fig. 2) to which the 7-bit words, the identify the characters for playback over which Lines 1L to 7L are fed. With the 7-bit code 128 characters and symbols can be used and the

P coding preferably corresponds to the standardized U.S.A.S.C. II code. The character generator is a diode matrix in 16 χ 8 format. The supplied via lines 1L to 7L 7-bit words are divided into 4-bit and 3-bit words, which determine the Y and X coordinates of the 16 χ 8 format. This format always has the form of a 7 * 5 matrix, which consists of diodes, so that the complete diode matrix contains 16 χ 7 Y-lines and 8x5 X-lines with diodes. Lines 1L through 4L are connected to a 4-bit Y decoder

^ YD connected which decoder based on the 4-bit code these lines responds to the required group 7 Y Select lines from the 16 possible groups. A Row scan shift register R.S.S.R., which is derived from the row pulses of 8.75 kHz, selected from the appropriate series of seven via groups of gate amplifiers YGA. Lines 5L to 7L are to a 3-bit X decoder X.D. connected to the 3-bit code on these lines responds to the required group of 5X- * lines from the eight possible groups to select. Corresponding X-lines

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in the eight groups are common to output lines A. connected to E via groups of gate amplifiers XGA. Every crossing of X and Y lines in the matrix why one Connection is required is bridged by a diode d, which in this way forms a sign element. the Drawings are made by the selective arrangement of the bridging Diodes d are formed at the appropriate intersections as shown in FIG. Each X-line is to a different one connected to the gate amplifier XGA, which can each be actuated to deliver an output signal to the relevant Output lines A to E, which signal to an output signal supplied to them from the X decoder XD and a The output signal of the relevant X-line responds. The latter output signal is generated from one of the 16 outputs of the Y decoder YD via one of the seven gate amplifiers YGA belonging to this output (as indicated by the register R.S.S.R. determined) and fed through the relevant bypass diode d.

The column shift registers (C.S.R, in Fig. 2) are shown in more detail in Fig. 5. These column shift registers contain five discrete registers CSR1 to CSR5. which consist of 32 bits, whereby the lines E to A consist of the Character generator CG. connected to their inputs. The data for a range of characters only, (i.e. for the Cells that need to light up for a character in only one row) are assigned to registers CSR 1 to OSR 5 at a rate of 1 character per clock pulse applied in parallel

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leads. As mentioned above, this takes 12 / us for only a row of 32 characters and is repeated 7 χ per row of characters, with the cells of the display panel from [registers CSRI to CSR 5 via the cathode drive amplifiers CDA while 100 / US per row are driven during the suppression period of the clock pulses. The additional bit position Q in the register CSR 5 supplies a suppression clock signal when the registers are full to close the gate amplifier GA. A permeable pulse in the opening of the cathode control amplifier CDA is also supplied from this additional bit position at the same time. The waveform g in FIG. K shows the column activation period during which the clock pulses are suppressed and the waveform h shows the first bit positions of the column shifting regions .

By being discreet «; Column shift registers operating in parallel in this manner, a clock pulse W can be used speed, which is only one fifth of the clock pulse rate which would be required for a single column register which is filled from the character generator with data sequentially.

In connection with the `` row output method '' described above, it should be mentioned that the row writing can take place sequentially in that successive rows of the matrix are each controlled with row pulses, or that this can be done in a paeudo-functional way, the rows each following a predetermined one

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repeating patterns can be controlled.

Although in the above example every image-generating Elements contains only one display element, it should be evident that it is also possible in each image-generating element to use several display elements, for example with different color tones. the The number of shift registers must then be adjusted accordingly.

The electrical display elements from the example were gas discharge cells. The invention is limited but not on displays with such cells. All types of display elements, which are indicated by a row and a column signal can be selected are usable.

The registers from the above example are of the digital type. If desired, registers are from the analog Type usable.

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Claims (3)

PHB. 32009. - 20 PATENTAN Sl'P RÜCHE. 1.j Electrical display device with a matrix • Image-generating elements, each containing at least one electrical display element, which element between one A head of a first group, called a row conductor, and a head of a second group, called a column conductor, lies, wherein at least a number of the row conductors are connected to outputs of a row selection circuit, and wherein "at least a number of column conductors with outputs at least two registers operating in parallel is connected, characterized in that the column conductors are corresponding electrical elements of at least two image-forming elements along a row conductor, each with an output of one are connected to another of a corresponding number of registers operating in parallel. 2. Electrical display device for displaying characters according to claim 1, characterized in that fc the number of registers operating in parallel corresponds to the number of image-forming elements of a drawing area along a row conductor. 3. Electrical display device according to claim 1 or 2, characterized in that it contains a coding * circuit for coding successively occurring input signals into simultaneously occurring input signals for the registers operating in parallel. 109819/1269