DE2044792A1 - Field effect transistor - Google Patents

Description

Field effect transistor The invention relates to a field effect transistor, in which there is a conductive channel between a source and a sink area each with the same type of doping in an oppositely doped semiconductor region below an insulating layer depending on the potential of one on the opposite Side of the insulating layer arranged, the channel zone covering control electrode can train.

In the case of surface field effect transistors, the channel width is known to be determined by the formation of the insulating layer.

The insulating layer is very thin where the channel is to be created made while in the places where despite a metallization of the insulating layer no channel should occur, the insulating layer is many times thicker. the lateral delimitation of a canal is thus obtained through the fastest possible change in the thickness of the insulation layer. So that you get a clear, from the size of the control electrode receives independent channel limitation, the control electrode always made so large that it goes beyond the area of the thin insulating layer protrudes onto the thicker insulating layer.

If silicon is used as the semiconductor material, there is an insulating layer usually made of silicon dioxide. With the known field effect transistors the width of the thin oxide layer and thus also the channel width are not smaller make than 5. The resistance of a channel is proportional to the ratio of the channel length to channel width. In special applications it is desirable to use the Kanai resistance to make a field effect transistor as large as possible, so that its power loss is low. When the channel width is the smallest for manufacturing reasons Value, then an increase in resistance can only be achieved through a corresponding Increase the channel length. However, this brings an undesirable increase in size the area required by the field effect transistor.

The proposal was also made to use the semiconductor with a uniform to provide a thick insulating layer. This avoids various disadvantages, which result from the gradations in the insulating layer. So in the places where the thin insulating layer is supposed to be located, remove it completely first and then formed again to the desired thickness. At the transition points between the thin and the relatively thick insulating layer can cause fine cracks, which extend to the semiconductor surface and through the subsequently applied Metal of the control electrode are filled. This is how short circuits occur between the control electrode and the source or sink area. This will the yield of usable field effect transistors in production is considerable lowered. Furthermore, on dXl.

These transition points are located in the metal coating of the control electrode appear.

Requires the use of an equally thick insulating layer other measures to limit the width of the canal. This can, for example, by the third of the metal coating of the control electrode be determined. However, here too, the channel width cannot be reduced in the desired manner. Aluminum is usually used as the material for the control electrode. The vaporized Aluminum is a polycrystalline material with a relatively large grain size of about 0.8 g. The control electrode must therefore have a width of several μm.

The present invention is therefore based on the object Field effect transistor with an extremely small one, as is the case with conventional field effect transistors to create unreachable channel width. This task is done with the one mentioned at the beginning Field effect transistor achieved according to the invention in that to limit the width of the conductive channel is the doped one between the source and drain regions Semiconductor region with two areas arranged at a certain distance from one another contains similar, but much stronger doping than that of the channel zone, which extend below the control electrode and at least one each in the longitudinal direction of the channel have running edge.

The invention is illustrated below with reference to the figures Embodiments explained in more detail.

1A shows a plan view of a field effect transistor with a channel delimited by heavily doped regions, FIG. 1B shows a cross section through the field effect transistor according to FIG. 1A, and FIG. 2 shows a memory cell that contains six Contains field effect transistors.

1B is a cross section perpendicular to the longitudinal direction of the channel from the area between source 6 and sink 7 of a field effect transistor. For example, a P-doped semiconductor substrate 1 is uniformly thick Insulating layer 2 covered. A control electrode is located on the insulating layer 2 3. As a rule, the substrate 1 is made of silicon and the insulating layer 2 is made of silicon dioxide and the control electrode 3 made of aluminum. Below the insulating layer 2 are in Semiconductor substrate 1 has two similar, but much more heavily doped P + regions 4 and 5 included. These areas are on both sides of the control electrode 3 and reach below this. The edges arranged below the control electrode 3 areas 4 and 5 run in the longitudinal direction of the channel between source 6 and depression 7. These edges are arranged at a certain distance from each other, so that below the control electrode 3 extends in the longitudinal direction of the channel Strip from the more weakly doped P-substrate is located.

To create a conductive channel between the shown in Fig. 1A, heavily doped N + regions of the source 6 and the drain 7 is connected to the control electrode 3 put a corresponding potential, so that below this in a known manner an N-conductive channel is formed in the P-substrate by inversion.

Due to the heavy doping of the P + areas 4 and 5 occurs in However, this does not have any inversion, but only in the P-doped one limited by it Stripes. The lateral delimitation of the conductive channel is therefore already below of the control electrode 3 through the transition from the P- to one of the P + regions 4 or 5.

The channel-limiting P + doping can be achieved by an additional process step e.g. before the production of the N + regions of the source 6 and the sink 7 are formed. The P + -doped areas can enclose the entire field effect transistor, thus through the Effect of other metal deposits on the insulating layer 2 no conductive channels from the source or drain area to others in the substrate 1 Contained doped areas can arise and thus parasitic currents avoided will. According to FIG. 1A, the P regions delimiting the channel are 4 and 5 through an the sink 6 and the source 7 brought up. They thus extend over the entire Channel length. It is of course also possible that the channel is only part of it Longitude through the P + regions and the rest of the way in another way in its latitude is limited.

The field effect transistor shown can be similar to lateral bipolar transistors a diffusion distance between the two regions 4 and 5 can be achieved by about one in.

The channel zone of the transistor is correspondingly narrow. You get thus about a factor of 5 to compared to conventional field effect transistors 10 smaller values for the ratio of duct width to duct length with the same size Space requirement.

The power loss can also be reduced to the same extent, which is particularly evident when arranging a large number of such transistors a semiconductor die is important.

2 shows a memory cell known per se with six field effect transistors. Two cross-coupled transistors T1 and T2 are used to store the binary information. There are further transistors T3 and T4 for entering and reading out the information intended. If neither of these two operations is to take place, then the two will Transistors T3 and T4 held in the non-conductive state via a word line WL. As a result, the two memory transistors T1 and T2 are made up of two bit lines BO and B1 separated. During this time, the transistors T1 and T2 are through the positive potential V1 fed through field effect transistors T5 and T6. The control electrodes of these transistors T5 and T6 are connected to a terminal, which is also a has positive potential V2. To simplify matters, the two potentials V1 and V2 are chosen to be the same size. If the memory cell is used for an input or The read-out process is controlled, then by a signal on the word line WL the transistors T3 and T4 brought into the conductive state. When reading is brought the potential of points 8 and 9 to the associated bit lines and over fed to these sense amplifiers. When storing, the bit lines BO and B1 signals corresponding to the memory transistors T1 and T2 via the transistors T3 and T4 supplied.

The current let through by the transistors T5 and T6 only needs to be so large that it eliminates the leakage current of the associated blocked memory transistor T1 or T2 compensated. The memory cell is, for example, in the state in which the transistor Ta is blocked and the transistor T2 is conductive. The conductive state of transistor T2 is maintained by the potential of point 8. Therefor however, the condition must be met that the potential of this point does not decrease. For this it is necessary that the current supplied via the transistor T5 is the leakage current of the transistor T1 held in the blocking state is able to compensate. This stream is very low, it has a value of around 20 nA. The transistors T5 and T6 should therefore have a correspondingly high resistance, because a lower one Resistance of the respective conductive transistor, i.e. in the present example the Transistor T2, assigned transistor, i.e. of transistor T6, only the power loss but the stability properties of the memory cell cannot be improved. Such a high resistance is only possible with a very large value for the ratio Can be approximately achieved from duct length to duct width. With the conventional transistors this value can only be achieved by increasing the channel length accordingly and thus an increased space requirement can be achieved, since the channel width from manufacturing technology Reasons cannot be made small enough. In the field effect transistor described here can be compared to the channel width on the fifth through the tenth Reduce part, so that the area required by a corresponding increase in the resistance does not get bigger.

Claims (4)

P A T E N T A N S P R Ü C H E Field effect transistor in which there is a conductive channel between a Source and sink areas, each with the same type of doping, in one opposite direction doped semiconductor region below an insulating layer depending on the potential one arranged on the opposite side of the insulating layer, the channel zone Form covering control electrode can be characterized in that to limit the loading the width of the conductive channel is that between the source and sink area doped semiconductor region two regions arranged at a certain distance from one another with the same, but much stronger doping than that of the channel zone, which extend to under the control electrode and at least none in the longitudinal direction of the channel have running edge. 2. Field effect transistor according to claim 1, characterized in that the insulating layer has a uniform thickness. 31 field effect transistor according to one of claims 1 or 2, characterized characterized that he is of the two areas with similar, but essential stronger doping than that of the channel zone is enclosed. 4. Field effect transistor according to one of claims 1 to 3, characterized characterized in that the semiconductor is made of silicon and the insulating layer is made of silicon dioxide exist.