DE2044268A1 - Test circuit for operational programs in computer systems - Google Patents

Description

IBM Germany Internationale Büro-Maschinen Gesellschaft mbH

Boeblingen, September 4, 1970 ru-sk

Applicant: International Business Machines

Corporation, Armonk, N.Y. 10504

Office!. File number: New registration

File number of the applicant: Docket EN 968 013

Test circuit for operating programs in computing systems

The invention relates to a test circuit for operating programs in a computer system, which consists of at least one There is a program memory and a control unit in which both the occurrence in time and the type of error is saved and analyzed.

Test procedures and test circuits for program errors in Data processing systems are known per se. For example, it has been known for a long time when an error occurs to interrupt the program within a program and then to switch on an error correction program which, depending on the type of error, detects the faulty part of the Program repeated until this part of the program is without errors. However, it does so even after repeated runs the error is not eliminated, then the interrupts

Docket EN 968 013 109811/1866

Calculator after a certain number of repetitions the operation. However, this type of error correction has the disadvantage that only very specific errors affect this Kind and. Way can be recognized and that very extensive programs for error correction and error detection must be available, which also has a lot of storage space within the data processing system would be needed to run the actual program.

It is also known that the programmer can set markers at certain points in the program, this can be used to determine during the printout whether the program has worked properly up to this point has or not. If during the manual check it is then found that the program is at a certain point was faulty, then the programmer has to laboriously localize and eliminate the fault./The invention is therefore the task of creating a test circuit for Operati ons programs in a computer system that ^ the manual review, location and correction work of the programmer is significantly reduced.

The solution according to the invention is that between registers a central unit, a test or analysis counter is arranged, the one within a sequence of instructions Identifies a specific step in order to localize a specific error that said counter has modification circuits is connected to a known instruction counting and decoding register and that in addition, another counter for counting the operations carried out after the position indicated by the check counter is present, the reading of information into the instruction register or via AND circuits also controls in general registers from memory.

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The invention will now be made with reference to in the drawings illustrated embodiments described in more detail.

It means:

Fig.l is a block diagram of the invention Test circuit;

2 shows a further, more detailed block diagram the program check circuit;

3 shows the detailed structure of a register according to Figure 2;

4 shows a cycle control circuit for reading data into one of the selected registers, which are shown in Fig.3 and

Fig. 5 is a block diagram showing a program analysis operation code interlock circuit; as used in the present system.

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The information stored in the memory 11 is read out in the present exemplary embodiment in such a way that a half-word is always available, which consists of two bytes or sixteen data up to plus one parity bit. The registers 13, 15 and 17, which can be part of a known data processing system, also have one Sixteen bit capacity.

It should be assumed here that the instruction counter value is available in register 17, which is stored in the Memory address register 19 is transferred to address the memory in the data processing system. At this point It should also be pointed out that registers 13, 15 and 17 in the following description also have registers G, U and V, respectively. There is also a cycle control unit 20, which will also be described later , of which it should be mentioned at this point that it is used to control the reading out of a half-word from memory and then controls the decoding of the information to determine the opcode that makes the Instruction defined. The respective half-word read out is stored in register 13. However, if the Operation code has an analysis instruction, then recognizes and determines the control unit 20 that this is a full word and causes the next succeeding half word im Memory in the register 15 is read out. When this occurs, the value in memory address register 19 is through the address register modifier 23 is increased by two, so that the next half-word can be addressed.

At this time, if the above-described operation occurs, then the central processing unit is in that non-analytic fashion and the calculus instruction will

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treated as a no-operation instruction and the cycle-controlled one Circuit causes the next instruction to be read out. If the central unit of the Computer system is working in the analysis mode, then the analysis instruction is completed and the central unit enters the execution part of the analysis instruction. An address is given in the memory address register 19 been made to move to a specific location within the To address memory.

The data that is in register 13 at this time is stored. This causes a record of the actual state of the computer at this part-time. The memory starts during the first execution cycle at the memory location x, if the address χ in the memory address register 19 stands. At the same time, the address modifier 23 modifies the address data stored in the register 19 are stored. During the second execution cycle the data is saved in the U register. This occurs at storage location x + 2.

Additional execution cycles store data in the analysis counter 29 in memory location x + 4. Then the data in register 17 is in a memory location x + 6 and the other required information, e.g. the program status words, stored in other memory locations below.

During the following storage cycle in which the data from Register 17 are stored in the storage unit 11? the lowest digit of the twelve data bits from register 15 is set in the analysis counter 29, whereby the previously data in this unit are displaced.

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When all the necessary data has been saved and the associated modifications have been completed, that’s it Register 17 modified by circuitry to be described later. This register becomes the new address which reads out the next address to be executed from the memory and stores this address in the memory address register 19 enters. The cycle control unit 20 causes this new instruction to be read from memory as it was previously described.

During the first cycle of each instruction, the content of the analysis counter 29 is decreased by one, namely until the analysis counter 29 goes to zero, whereby the normal reading out and the execution of the instructions can be carried out continuously. If the instruction counter 29 goes to zero, then the current instruction is not carried out. The central processing unit will react here as it did when it carried out an analysis instruction. The cycle control unit 20 responds to a zero detector circuit causing an interrupt. The data in register 13 is stored in the same memory location as the data in register 15. The big difference will be that the data in register 17 will be modified by a factor of 2 and not by a factor of 4, as is done in an analysis instruction that ran correctly. In a similar way to the interruption just described, which is caused when the analysis counter 20 goes to the value Mull? other interrupts can be made to control the same sequence of incidents. This can be _f if errors occur in an interrupt operation or if there is a parity check or if there are other errors. To give atLm example, assume that if an analysis instruction

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is carried out in specific and selected places and storage information in memory related to the Analysis instruction are present, which by the lowest selected bits of the register 13 and by the highest Position of the selected bits from register 15 are shown. The content of the analysis counter is determined by the information determined in register 15. The content of the analysis counter 29 is to be regarded in the same way as the content of any one other register.

From the circuit diagram according to Fig.l it can be seen that information in the form of stored data on each of the Register 13 and 15 from the memory of the analysis counter or the storage unit 11 can be transferred.

In the following, more details are given in connection with 2-7 of the circuit previously shown in Fig.l described.

In Figure 2 there are a number of registers 13, 15, 17, 39, 40 and 41 shown. The output of the memory from the computer or the memory unit 11 is denoted by collecting line a. The data on this bus becomes given to all the registers whose outputs are on the line 43 ferry, which in turn via lines 45 and 46 with is connected to the memory address register 19 and via the line 47 to the memory unit 11. The outputs of the registers 13, 15 and 17 etc. are also connected via the LINE to registers 49 and 50, which in turn are connected to the arithmetic and logic unit 51 are connected. The arithmetic logic unit 51 is over the line connected to another input of registers 13-41. These registers are fed by the bus a, the registers in turn as the source for the arithmetic logical unit 51 are used, although to

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must be taken into account that there is still an additional source in the form of the b-collecting line 55, which is also available the arithmetic logic unit 51 feeds. The analysis counter 29 is fed in connection with the line 43.

In addition, the operation decoding circuit 59 is provided for the decoding, which will be described later in connection with FIG will be described in more detail.

It should also be mentioned here that each of the registers has several inputs and outputs, which are connected via control lines be in communication with the cycle control of the system.

In Figure 3, a control circuit is shown schematically, the is in communication with the storage unit 11 via the data bus line a and also via the data bus line a is connected to one of the registers, namely register 13, which carries data to the second bus b can deliver.

The storage system has a large number of word storage locations with a capacity of sixteen hits each. The incoming inspection 61 is connected to all of the AND circuits 62, 63 and so on. The other input of this and circuit becomes occupied by bits 0-15 from the memory.

In Figure 3, six of the sixteen locking circuits are which form the register 13 can be seen. These latches are all set when the cycle control is in control of the system the condition "read in G register" line is present, which causes sixteen ond circuits be turned on when the corresponding bit line of bus a is also ON. the Line 104 from the cycle control unit prepares the

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AND circuits 71, 72, etc. in front, thereby energizing the corresponding data lines and the corresponding locking lines are set if Data are present on a corresponding line. As a result, the pending information is loaded into register 13. The other inputs of these AND circuits are fed by the inputs of the AND circuits 62, 63 and so on.

In addition, there is a line 81 in the circuit according to FIG to the G register, which carries a corresponding cycle control signal. This signal is to delete the Register G exists and is therefore applied to every latch circuit 82, 83 etc. led. A latch circuit, e.g., 82, is made up of two feedback circuits AND circuits, e.g. 87 and 88, are formed.

The level for bit zero should serve as an explanation. If a signal is present on the line 81 and an output signal from the AND circuit 62 is also present at the AND circuit 71, an output signal is produced at the output of the AND circuit 71, which is given to the AND circuit 88 as an input signal. This AND circuit 88 has only a single input. The output of the AND circuit 88 is fed with a feedback path to the input of the AND circuit 87, which also receives a "Do not delete G register" signal from the line 81. As long as this signal continues, an output signal is available on the output line 91, which is connected to the AND circuit 93. The other input of this AND circuit is connected to a line which also leads to the inputs of the other AND circuits 93 'and so on. The output signal of the AND circuit 93, which is available when the cycle control signal "read register G" is present on the common input line just described and is equal to

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a signal on line 91 occurs in good time. This on Output of the AND circuit 93 occurring signal given to manifold B. Under similar conditions, there are also signals on the bit lines 1, 2, etc., which can also be passed on to collecting line B.

In Fig.4 is essentially the cycle control and the Instruction cycle control shown. The instruction cycle flip-flop 101 gives a pulse via the line 102 to an input of the AND circuit 103. The output of this AND circuit 103 is connected to a line 104 which carries the signal for writing into register 13 from Fig.3 provides. If the instruction cycle flip-flop is off, then there is none on line 102 Signal and on line 105 indicating the execution cycle controls, a signal is present. On the other hand, if the instruction cycle flip4 ELop 101 is on, a signal is present on line 102, and so that an input of the AND circuit 103 is energized.

In addition, the cycle counter 107 is provided, which supplies control pulses for each operating cycle, namely for the first through the N-th cycle. These pulses are given to lines 108 and 109, for example, which in turn are connected to inputs of the corresponding AND nodes, for example line 108 to AND circuit 103. The cycle counter thus supplies pulses on line 108 for the first cycle and pulses on line 109 for the second cycle. However, the entire operation is controlled by clock generator 110, whose time pulses a-7 occur on separate lines. In this example, only the line 111 is shown, which is connected to an input of the And-Schaltuii? 103 is in communication. The other geseigten in Fig.4 Ui * 3 circuits, the inputs of which are empty are the same with the ^T nstruktionszyklus flip-flop 101, cäeia Zyklusiähler

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107 and the clock generator 110 are connected via the corresponding lines, so that their detailed description is omitted. The operation decoder 115 is shown in FIG. 5, on the basis of which further details of the prograin manalysis operation are described. In the present example it should be assumed that bits 0, 2, 3, 5 and 7 in G register 13 are in the off state, but bits 1, 4 and 6 are in the on state. Under these conditions, bits 1, 4 and 6 indicate when an analysis instruction would be read from memory. In the program operation Analysis, bits 1,4 and 6, a Anaiysisinstruktion and all the corresponding lines to the AND circuit 117 are energized via the respective inverters 118 _f 119, 120, etc .. If, for example on one of the inputs, for example on the bit If a pulse is present on the zero line, it is inverted by the corresponding inverter circuit. It follows that the polarity of the pulse that would arise on bit line 1 would be inverted compared to others, so that not all inputs at the input of AND circuit 117 are the same and thus no output pulse at the output of the AND circuit 117 can arise. In addition to the described inputs of the AND circuit 117, namely the bit lines 0-7, one input is also connected to the line 131, which comes from the cycle counter and is thus controlled by the decoding operation controller. The mode of operation described so far shows the control of the operation decoding. If the AND circuit 117 is used to control the last output, all pulses are fed to the input and they must all have the same polarity.

It is now assumed that a signal from the output of the AND circuit 117 via line 133 for AND circuit 135 is given, at the other input of which is the line 137 with the "Do not delete" signal. Under these

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The AND circuit 135 supplies conditions at its output 139 an output signal which is sent via line 141 to the cycle control circuit, for example to the cycle control unit 20 in Fig.l, is performed. In addition, this signal is given to the single input of the and circuit 145, whereby this signal is locked until the "Do not delete" signal is switched off.

As can be seen from the above, the calculus counts 24 in Fig.2 and 29 in Fig.l the main object of the present invention and he serves primarily to localize an occurring error and to determine the same. A typical application of the The present invention would consist in performing the previously described error detection operations when entering a new program that may be buggy would be used. While generating the program would the programmer in this case insert analysis instructions at certain intervals. E.g. the program could contain a loop from which there is no longer any branching or exit to other instructions. In such a case the loop would run continuously * and endlessly. To avoid this, we would like before In other words, the programmer would insert an Analysis instruction into the loop at various points. This instruction would contain a number to be put in the calculus counter. That number would be the maximum of the number of instructions that should be executed normally before the next analysis instruction decrypts

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will. A computer enters the loop and continues this journey until a point comes in where the analysis counter reaches zero and generates an interrupt. The interrupt routine would then cause the Loop is exited and either a stop or a correction operation under the program interruption routine

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or a branch to a next point in the program would be carried out. When the program has been completely executed, the programmer can use an expression with exactly Using the printer on the computer, see the analysis instructions and the counter values for each instruction. If he in the evaluation finds that the content of the counter is too Has gone zero, then he knows that in this part of the Program something is wrong.

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Claims (1)

September 4, 1970 ru-sk Claims Test circuit for operation programs in a computing system, which consists of at least a program memory and a control unit in which errors occur during of the run are recorded according to the type and duration of occurrence, characterized in that between Registers (e.g. 13, 15 and 19) of a central unit a test or analysis counter (29) is arranged, the Identifies a specific step within a sequence of instructions in order to correct a specific error locate that said counter (29) via modifying circuits (e.g. 33) with a per se known Instruction counting and instruction decoding registers (35 or 115) is connected and that there is also another counter (e.g. 107) for counting the number after the the test counter (29) designated point carried out Operations is available, the reading of information into the instruction register via AND circuits (103) (13) or in general registers (e.g. 15) from memory (11). 2. Test circuit for operating programs in a computer system according to claim 1, characterized in that the test or analysis counter (24) registers (13-41) is connected downstream via a collecting line (43) and that the output of the test counter (24) via a collecting line (55) is also connected to the bus (43), which once becomes an arithmetic and logical unit (51) of the computer system and on the other hand via a collective filter (45) to the memory address register (19) 10981 1/1866 Docket EN 963 013 and leads to the memory (11) and also to the operation code controller (59) for operation control connected is. 3. Test circuit according to claims 1 and 2, characterized characterized in that the registers (e.g. 13) connected downstream of the memory (11) consist of interlocking circuits, those from feedback AND circuits (e.g. 87 and 88) are built, the bit input and outputs (Bit O to Bit 15) via gate circuits (62-65 or 93 and 93 ') for reading and writing with the cycle control via lines (81, 104, reading and writing). 4. Test circuit according to claims 1 to 3 _#, characterized in that the operation decoding su ^ß · AND circuits (eg 117) with a downstream locking circuit (135,145), at whose inputs (bit 0 to bit 15) are present and predetermined bit combinations the output (141) of which is the analysis operation code which is used for cycle control. 1098 1 1/1866
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