DE2040759A1 - Logical network - Google Patents

Description

Logical network The invention relates to a logical network to approximate a difference between two signals, each of which is several Binary digits and having the same binary code, the binary code being such that that all digits in each signal are assigned different equivalent decimal sizes are, as well as for generating a control signal corresponding to the approximation for digital servo devices, in particular for numerically controlled machine tools with differently graded control speeds.

Control systems of the kind used for automatic adjustment of machine tools are well known. In these systems one uses generally one or more setpoint generators for generating the setpoint tool position indicating command signal and a comparator for generating the instantaneous difference deviation signal indicating between the command signal and the position signal. The deviation signal is used to control the rotational speed or the speed a variable speed drive mechanism, for example a motor, which in turn controls the position of the machine tool. With the Approach of the machine tool to the command position (target position) the deviation signal inevitably decreases, so that the speed of the drive mechanism decreases until the tool reaches the desired position if necessary.

The advantages of digital controls, especially accuracy and stability, have long been recognized in particular in position control systems, so that they on have found widespread use in this field. As is well known, enable digital target / actual value comparisons provide stable position control for machine tools with an accuracy that is not easily achievable with analog techniques. However the digital control effort is considerable.

Suppose a machine tool is supposed to have an accuracy of one Thousands of an inch (0.0254 mm) over a twenty-four inch (609.6 mm) can be set, then when using a pure binary code for display all twenty-four thousand individual tool positions with a binary number fifteen bits required.

Thus, a fifteen-bit command signal must have a fifteen-bit position signal can be compared to generate a fifteen-bit deviation signal, which then converted into an analog signal in a fifteen-step digital-to-analog converter must be used to control the speed (or the speed) of a motor or a drive mechanism is suitable. In general, the comparison is made of the digital signals using a binary subtraction technique in which complex Subtraction and "lending" circuits are used, with the "Lelb" circuits to the Preventing signal reversal are necessary, if in any comparison stage the subtrahend exceeds the minuend. "Loan" circuits don't require just one large circuit complexity, they also cause time losses, since the "Loan" state in the lower digit levels must be resolved before the state of the difference signal (deviation signal) in the higher-digit levels finally can be determined. The digital circuit complexity is when using binary-coded Decimal signals (BCD signals) to facilitate the pure programming work still increased. A BCD code is obtained when each digit (decade) is a decimal number individually converted to binary form. Since there are ten possible for each decade Values, at least four binary levels are necessary to represent each decade. So there are more stages necessary than with pure binary code, so that additional logic circuit elements are required. In addition, the BCD words must be modified in order to be able to compare them appropriately.

The invention is based on the object of providing a digital network create, in which the target / actual comparison of binary-coded decimal signals to carry out certain approximations is significantly simplified in terms of circuitry without the accuracy of the digital control technology is reduced.

This task is solved by several comparison devices in order to simultaneously and individually the binary states of the respective pairs of digits of the same order of magnitude to compare and to individually display non-zero differences between pairs of digits of the same order of magnitude and To sue the polarity of the non-zero difference to produce logical bodies that connected to the comparison means to provide an indication of the polarity of the Difference between two digital signals according to the polarity of the difference between the compared pair of digits to produce the highest order of magnitude and having a non-zero difference, wherein the logical devices additionally an indication of the approximate magnitude corresponding to the difference between the digital signals the order of magnitude of the pair of digits being compared that has the highest order of magnitude and having a non-zero difference, generate correction means, which with the logic devices and the comparison devices are connected to the To suppress the approximation size display and a changed approximation size display corresponding to the order of magnitude of the pair of digits of the next lower order of magnitude to be generated only if the difference between the pair of digits of the highest order of magnitude, that has a non-zero difference that has a polarity and the difference between polarity opposite to the pair of digits of the next lower order of magnitude possesses, wherein the correction means additionally have means to another modified approximation size display instead of the aforementioned modified one Generate approximate size display only if additional, consecutive Pairs of compared digits that are orders of magnitude immediately lower are of the next lower order of magnitude than those of the pair, differences of the opposite Having polarity, and being the further changed Approximate size indicator according to the order of magnitude of the pair lowest order of magnitude of the additional successive pairs of digits with the opposite difference polarity generated becomes, and in that the binary code is a binary-coded decimal code, the Digit signals have at least eight digits to the equivalent of at least to reproduce two decades and with the logical network also additional Has correction devices to the further changed approximation size display to suppress and in their place. a corrected approximate size indicator only then generate if a pair of a group of digit pairs that make up the pair of next lower order of magnitude and the other successive pairs that Pair of the highest order of magnitude in any decade.

To explain the idea on which the invention is based referred to a special logic system with certain parameters. One such The system is intended here for illustration purposes only, without specifying the scope of the invention. It is assumed that for positioning a numerical controlled machine tool for the command signal (setpoint) A and for the position signal (Actual value) B BCD signals from five decades (5 x 4 or 20 levels) be used. Forner it is assumed that every signal has an absolute position indicates, i.e. a numerical position in relation to any reference zero point describes, and that drrs command signal remains constant until the machine tool is set according to the command signal. Due to these conditions, it is desirable cine quickly responsive position control with a minimum of switching effort to be specified, whereby the close positions are traversed.

An examination of the requirements for a signal to control the speed of the drive mechanism adjusting the tool showed that a rapid Positioning with override of the zero position when using a drive with multi-stage Can reach speed or speed range, the speed (or the speed) of the drive technology in stages for predetermined ranges decreases with the decreasing distance of the tools from its commanded target stub get smaller.

For example, assume that a maximum speed of 1200 inches (30,480 mm) per minute for large differences between target and actual words, a lower one Speed of 120 inches (3,048 mm) per minute for an adjacent area with a slightly smaller target / actual value difference and a speed of 12 inches (304.8 mm) per minute for the next range with an even smaller target / actual value difference etc. is prescribed. Such a schoma leads to large differences in target values to a quick response, while it has about the same zero position override properties because the system does not have a continuously variable speed. Also unnecessary In the system proposed according to the invention, there is a need for a conversion the digital difference between the command and the position signal in a constant analog deviation signal, so that only comparatively little logical Circuit elements and circuits for speed control are required. The logic circuits according to the invention lead to predetermined, the area delimiting stages of the digital difference signals and do not require any Conversion circuit assigned to the stage of the signal. It is even more important that that system according to the invention overcomes the disadvantages of direct binary subtraction a so-called pseudo-subtraction technique, which only leads to an approximation the actual deviation leads. This approximation to the deviation signal is permissible because only the respective range of difference between the command and the Positional signal is of importance in contrast to the comparable known devices, that require the actual instantaneous deviation. As from the description below As can be seen, the pseudo-subtraction technique according to the invention can be used with less perform logical circuit complexity than was previously the case with a direct subtraction technique or for those circuits that were already such an immediate Tried to avoid subtraction technique according to the previous state of the art.

First of all, the special feature of the BOD command and position signals is shown. In Table 1 below are the each of the twenty binary levels (A1 to A20) in the BCD command signal word assigned decimal values and the each assigned to the twenty binary levels (B1 to B20) in the BCD position signal word Values listed: Table 1 Decimal values of the non-zero A and D levels A1 = 00.001 = B1 A11 = 00.400 = B11 A2 = 00.002 = B2 A12 = 00.800 = B12 A3 = 00.004 = B3 A13 = 01.000 = B13 A4 = 00.008 = B4 A14 = 02.000 = B14 A5 = 00.010 = B5 A15 = 04.000 = B15 A6 = 00.020 = B6 A16 = 08.000 = B16 A7 = 00.040 = B7 A17 = 10,000 = B17 A8 = 00.080 = B8 A18 = 20.000 = B18 A9 = 00.100 = B9 A19 = 40,000 = B19 A10 = 00,200 = B10 A20 = 60,000 = B20 It should be noted that corresponding Levels in the command signal A and B are assigned the same values and that the 6 assigned notes Values increase with the number of steps.

Thus, for each of the signals A or B, provided that only the level 11 (A11 or B11) is in the binary on-state and all other stages are are in the binary zero state, the value of the respective signal is greater than when only level 10 (Alo or B10) is in the binary one state.

A and B are defined by:.

It is taken into account that the command signal A for each individual position cycle remains unchanged, when the comparison is carried out between him and the When the position signal B changes, the signal A can be used as a reference value. The aim is to investigate the possibility of obtaining a signal that is relevant to the respective Stages of signals A and B twenty independent stages defined as Ci = Ai - Bi includes. That means, it should be independent of the "flax" techniques and others Immediate binary subtraction related intermediate stages connections an immediate, step-by-step comparison can be made. From the following Table 2 (correctness table) shows that each Ci level is in a three level code with a positive value for Ai> Bi.

a negative value for Bi> Ai and a zero value for A1 = B1 can assume one of three states.

Table 2 A1 B1 C1 o o o 1 o + 1 1 o o 1 - Considering all twenty Ci levels means that the highest-digit, non-zero Oi level is always must have the same polarity as the polarity of the difference between the signals A and 3. This is because C1 defines it as the difference between A1 and Bi and is therefore the highest-digit, non-zero value O1 level corresponds to the highest point of A and B at which there is an inequality. The highest inequality between A and 3 determines the polarity of the Difference between these signals.

Correspondingly, the highest-digit, non-Hull O1 level delivers in addition to determining the polarity of the difference between A and B, an approximate Measure of the size of the difference between A and B. Wonn, for example, C19 positive (+) is (i.e. A19 = 1; B19 = 0) and at a special point in time it is the highest is a non-zero Ci level, is shown in the table. 1 that when using of C19 as a measure of the deviation size, the approximate deviation + 40,000 (A19 = 40,000).

However, how close this approximate deviation quantity is to the actual one The size of the deviation is close to the conditions in the C19 immediately preceding lower-digit Ci levels dependent. To illustrate this clearly, be the following example is considered @ Example 1 Assume that C20 = = 0 (A20 "O binary, 00,000 decimal; B20 = 0 binary, 00,000 decimal).

019 = + (A19 = 1 binary, 40,000 decimal; B19 = 0 binary, 00,000 decimal).

C18 = - (A18 = 0 binary, oo, 000 decimal; B18 = 1 binary, 20,000 decimal).

C17 = - (A17 = 0 binary, 00,000 decimal; B17 = 1 binary, 10,000 decimal).

C1 to O16 = 0, + or - (so that a maximum change of + 09,000 is brought about.

The actual deviation is therefore: + 40,000 - 20.00 - 10.00 + 09.999 + 10,000 + 09.999 However, the approximate deviation is based the highest non-zero 0i level as a measure of the deviation here + 40,000. A scheme in which + 40,000 to approximate a range between + 00.001 and + 19,999 is used because of the size of the area and because of the renation is out of range, obviously inadequate.

So it turns out that the correction factor in the deviation signal approximation must be included to account for the situations in which a or more of the highest-digit, non-zero Ci level immediately preceding lower-digit Ci level one of the polarity of the highest-digit, not zero have a different polarity at the respective level. Considering the foregoing For example, if C1 to C1 are zero or +, then C17, which is the non-permanent digit Level of the preceding uninterrupted tole is made up of Ci levels and one of the The polarity of the highest digit, non-zero level (C19) deviates i.e., has opposite polarity, a better approximation of size of the deviation signal (10,000). It then seems that where the highest non-zero Ci level immediately one or more oiner successive chain of lower-digit stages with reverse polarity before, better the lowest level of the chain as a measure of the size of the deviation signal could be used. This technique is illustrated in the following example. To simplify the explanation, Cm is the highest non-zero value C1 level defined at a given point in time: Example 2: Here it is assumed that that ; C20 = 0, C19 = +, C18 = -, C17 = 0 or + and C1 -> C16 zero (0), positive can be (+) or negative (+).

Thus Cm = C19 and hence the polarity of the deviation signal +. Since Cm is immediately preceded by a step (C18) of opposite polarity, this level is used to determine the size of the deviation.

Thus The resulting deviation is therefore + 20,000. When calculating the actual deviation using Table 1, it can be seen that C19 = + 40,000, C18 = - 20,000, C17 = 00,000 or + 10,0000 and C1 016 = + 09.999.

This results in an actual deviation range of + 10,000 to 39.999. The deviation from 20 obtained by using level B18 = 20 is in the middle of the range.

Example 3: Here it is assumed that: C20 = -, C19 = +, C18 = +, C17 = +, C16 = 0 or - and C1-> C15 = 0, + or -.

Thus, Cm = C20 and hence the polarity of the deviation signal - be. Since Cm (C20) immediately three stages (C17, C18, C19) of opposite gas Polarity, the lowest of these levels (C17) is used to determine the size of the deviation is used. Thus, C = A17 = 10,000 and is the approximate Deviation - 10,000.

When calculating the actual deviation using the table 1 shows that C20 = -80,000, C19 = + 40,000, C18 = + 20,000 and C17 = + 10,000 where C1 -> C16 must be between - 09.999 and + 07.999, so that results in an actual deviation range of - 02.001 to - 19.999, wohe the signal 10 is obtained, which is again somewhat in the middle of the range.

From the previous examples 2 and 3 it is clear that the correction factor the accuracy of the approximation is made by adding orstens the approximate deviation lay within the actual deviation range and the approximation is two times greater is kept in the order of magnitude of the actual deviation. For many purposes is it sufficiently precise and, as explained in more detail below, is practical Application of the correction factor is easier and does not require complex circuit construction.

However, there is another problem with the approximation because a BCD code is used. The on which the previous discussions are based The considerations and the resulting conclusion are all one pure binary code as well as a BUD code. However, a peculiarity leads of the BCD code and the deviation approximation create an additional problem, attention is to be given. Since four binary levels are used in the BCD code, each decade to determine an equivalent decimal number, each binary decade comprises sixteen bits, of which only 10 bits are used.

For example, only the numbers can be used in each four-stage BCD dakade 0000 (decimal digit 0) to 1001 (decimal digit 9) degenerate. Thus, the Zahlon where the following Lioto never occurs in any decade: 1010 (decimal digit 10) 1011 (decimal digit 11) 1100 (decimal digit 12) 1101 (decimal digit 12) 1101 (Decimal digit 13) 1110 (decimal digit 14) 1111 (decimal digit 15) Instead of this these decimal digits come in connection with the next higher four-level binary decade before, so 0001 0000 the decimal digit 10, 0001 0001 the decimal digit 11, 0001 0010 the decimal number 12, 0001 0011 the decimal number 13.

0001 0100 the decimal number 14 and 0001 0101 the decimal number 15 represents.

This six-bit excess capacity in each decade leaves 9 door The techniques described so far create additional problems. These problems are best illustrated by a specific example.

Example 4: Here it is assumed that: Om = C5 = +, C4 = -, C3 = 0, C2 = 0, and C, = t - or 0.

(Note that C5 - the lowest grade in the second Decade - the highest digit, non-zero Ci level, and that C4 - the the next lowest level and the highest level in the first Dakado - an opposite one Has a sign). According to the approximations developed above, the approximated Deviation is determined as follows: The polarity of the deviation is the polarity of Cm, (C5) thus +.

The size of the deviation is determined by C4, since C4 (Cm-1) the only C5 (Cm) immediately preceding Ci stage with opposite signs is.

So C4 = B4 = 00.008 and the approximate deviation is + 00.008.

When calculating the actual deviation, it can be seen that 5 = + 01,000, 4 = - 08,000, C, = 00,000 or + 00,001 and the actual deviation range + 00.001 to + 00.003.

The approximate deviation is outside the actual deviation range. When examining the relationship between the assigned values of adjacent levels within a decade and comparing it with the relationship between the assigned values of the highest-digit level in a decade and the lowest-digit level of the next higher decade, the reason for this problem becomes somewhat clearer. It is generally true that in any decade there is the following relationship between level values: (within a decade) Berner agrees that the following ratio of the level values exists at decade boundaries: The reason for this inequality in this relationship is the restriction against the use of the six counts in every four-thirty decade, which, as I said, represent the counts 10 to 15 discussed. Since the highest digit in each dskade is valued with the dazimal number 8, it is clear that the lowest digit of the next higher decade must be valued with the desimal digit 16 in order to achieve the 2: 1 ratios that are the same between mutually adjacent levels within a dckade. However, since the egg type of the BCD code precludes such a bowing, the inequality of reserve is inevitable.

In order to correct this factor, it is necessary to make the protruding ones Described technique of size determination in which the level Cm has a polarity and one or more of the stages Cm-1, Cm-2, ....... Cm-n the opposite polarity aufweison and oine or mchrere of the steps with opposite polarity the highest digit The level of a decade is or are to be changed. In isolation it has been shown that under such conditions a shift from the lower level to one decade to the second lowest level of the next lower decade in generally leads to satisfactory results. This results from the BCD code, where counts representing the decimal number n 10 to 15 for the four binary levels are forbidden in a dakade, namely when the highest level in a commendable Decade is part of the chain of Cm-1, Cm-2, etc. that is a move of the size determine the level from Cm to the lower Ci level required, there is a certain limitation on the states of the second and third Stage of this decade. if O4 is negative (-), indicating that A4 = O and B3 = 1 @@@ so it is not possible that C3 and C2 can be ueg @ tiv (-), since this would require that either U3 or B2 be binary 1, so that the decimal value the Da @ ade B1 to B4 would be greater than 9. Since the BCD code rules out this situation, It becomes clear that stunts 2 and 3 of the decade are not an extension of the uninterrupted @@ Chain from the Stufon Cm-1 'Cm-2 uew. include hénuon @@ that therefore your effect on the Annüberu @ ug is not so big wi @ diej @ nige through level 4 of the Dokade.

The effect of this change in the sewing technique can be seen best illustrated with a specific example: Example 5: Here Assume that C1 to C20 have the following states: C20 = 0 C19 = 0 Dckade 5 C18 = 0 C17 = + (decimal + 10,000) C16 = - (decimal - 08,000) C15 = 0 decade 4 C @@ ~ 0 C13 = - (decimal - 01,000) C12 = - (decimal - 01,800) C11 = 0 Dckade 3 C10 = 0 C9 = - (decimal = 00,100) C8 = - (decimal - 00.080) C7 = 0 Dckade 2 C6 = 0 C5 = - (decimal - 00.010) C4 = - (decimal - 00.008 C3 = 0 C2 = 0 C1 = - (desimal - 00.001) According to the techniques discussed above the polarity of Cm = C17 is first determined and determined as +.

It should be noted that Cm (C17) and Cm-1 (D16) are of opposite polarity and that C16 also eats the highest level of decade four. So one shifts to the second level of decade 4 (C14) and assigns the value for #A 14 # or # B14 # from table 1 to it. However, since the immediately next lower level C13 contains a polarity which is the opposite of Cm (C17), the shift to it takes place by a conditional amount of the approximate deviation. It should be noted, however, that C13 is followed by stage C12 with opposite polarity, so that one must therefore go up to this stage in order to cause a conditional deviation quantity. The step C12 is however the highest step of the decade 3, so that it must be shifted further towards the second step of the decade 3 (C10). It should be noted again that two stages (O9, O8) follow C10 with a polarity opposite to the parity of Cm, so that even more is shifted when searching for the size-determining bit. Since "is the highest level in decade 2, it must be shifted to level C6, which in turn is preceded by levels C5 and D4 with an opposing polarity Cm. C4 is the highest level of decade 1, so that further up to level C2 must be shifted, and since this stage is preceded by stage C1 with the polarity of Cm opposite polarity, one must go down to C1, which determines the size of the deviation. and the approximate deviation of + 00.001 is obtained.

It is noted that the actual discrepancy can be found when checking turns out to be + 00.001.

Although the approximate deviation according to Example 5 with the actual Deviation coincides, this is not necessarily the case in every case. For example the change in increments due to the opposite polarity at the highest level of a decade the polarity of the second and third level in each Disregarding the decade, Example 5 would have been the same approximated even then Size result if C15, C14, all, C10, C7, C6, C3 and C2 are all positive instead of zero (+) would, however, under these conditions, the actual deviation would be + 06.667 be. Obviously, 0.001 is an insufficient approximation of 06.667, which is why a further change is necessary. Such a further change must be the Take into account the impact that levels 2 and 3 of each decade may have, if jumping to these steps according to the technique described above. in the individual it is to be noted that if the levels 2 and / or 3 are one of the level 4 contain opposite polarity and stage 4 a part of the Kotte from Cm-1 ' Cm-2 etc. is of opposite polarity to Cm, level 2 or 3 not moved together (jumped). It turned out that satisfactory results are obtained for these conditions if the appropriate jump to the third level instead of the second level. This leaves Illustrate yourself at the boston by looking at the need for the last Described change visualized: Example 6: Assume that C1 to C20 which have the following tone states: C20 = 0 decade 5 C19 = 0 C18 = 0 C17 = + (decimal + 10,000) C16 = - (de imal - 08,000) Decade 4 C15 = + (desimal + 04,000) C14 = + (decimal + 02,000) C13 = - (decimal - 01,000) C12 = - (decimal - 00.800) Decade 3 C11 = + (decimal + 00.400) C10 = + (decimal + 00.200) C9 = - (decimal - 00.100) Decade 2 C8 = - (decimal - 00.080) C7 = + (decimal + 00.040) C6 = + (demimal + 00.020) C5 = - (desinal - 60.010) C4 = - (decimal - 00.008) decade 1 C3 = + (decimal + 00.004) C2 = + (decimal @ 00.002) C1 = - (decimal - 00.001) Entnprochond According to the previous invention, zundchat is networked with polarities and that forner C16 is the highest level of decade 4. En is then moved to level C14 the second stage of Do @ ade 4 advanced, but it is to be blessed that mindesicus oine (in dicoem Pall both) of levels C14 and C15 (levels 2 and 3 of Dakade 4) There are polar lines opposed to C16 and that is therefore on the level C15 (level 3 of decade 4) is shifted. Since the next lower level C14 does not has the same polarity as the polarity of Cm-1 'Cm-2 etc. (in diosem Talle only C16) is not shifted further and C15 is the level that the @@ size the approximated deviation beatiumt. (Due to the limitations discussed above for the DCD code, stage C14 cannot have the same polarity as the stage C16. Thus, the shift is when the stage 3 or stage 2 of each decade is one shows Po @@ ritüt set off by level 4 of this decade, always at level 3 be end.) From Table 1 it can be seen that the deviation quantity determined by means of C15 04,000. The approximate deviation is therefore + 04,000.

As discussed above with the aid of Example 5, the actual value here is o Deviation + 6.667, so that the approximation is satisfactorily close.

In summary, the following rules according to the invention are used as an approximation one of the differences between DCD setpoint and actual value signals A uod B derutel anden Deviation signal set up: 1.) The polarity of the deviation signal is the polarity of Cm, the highest, non-zero level Ci.

2.) When Dm-1 is zero or has the same polarity as Cm, the size of the approximate deviation signal is where # C # is the absolute value of the approximate deviation signal and # Am # is the absolute value given in Table 1 for 1 # m # 20.

3.) If Cm is immediately one or more uninterrupted @@ chains of n steps Cm-1 'Cm-2' ... Cm-n precede the lower digits compared to Cm and are of opposite polarity, and none of these n lower-digit levels are the highest levels of a decade, is the size of the approximate deviation rating : C = Am-n.

4.) If according to rule 3 there is an uninterrupted chain with n lower digits Steps immediately preceded by an opposite sign Am and if one of these lower-digit levels is the highest (fourth) level in a decade is and if a) neither the second nor the third stage of this decade is one of the fourth stage has opposite polarity, then the size of the displayed th deviation due to the second stage of this decade of the same polarity as the fourth level, where under this condition the size is determined by the rule 3 and considering this erateness as part of the original uninterrupted Chain from Cm-1 'Cm-2 etc. is determined.

and if b) one of the second and third stages in that decade or both have or has a polarity opposite to that of the fourth stage the third stage the size of the approximate deviation signal.

It should be noted here that the rules (1), (2) and (3) apply the pure binary code as well as the BCD codes can be used and that the elu 4 (a) and 4 (b0 only aof the BCD code can be used. In addition, they are in the definition The Grandgeda used according to the invention does not apply to the one here in particular the code discussed, but also apply accordingly to other code. One There is a limitation insofar as the special procedure for approximating the signal deviation can only be applied to code in which the levels have values of increasing Size for anste @@ ende level members are assigned.

As from the following description of an embodiment As can be seen from the invention, the digital technology described above provides one sufficiently accurate digital comparison for many types of applications and eliminated the need for expensive and complex circuit elements as they are known for Digital techniques that perform direct digital subtraction are required.

From the above it follows that the invention on which the invention is based Task was to create a logic circuit to compare two digital ones To propose signals with which an approximation to the difference of the digital signals, which is sufficiently accurate for many applications, with less complex and complex circuits than before is made possible.

To solve this task belongs the creation of a control device, in which the difference between a fixed and a changeable digital one Signal approximated and the approximate difference for effecting an appropriate control function is used.

The purpose of the circuit according to the invention is to determine deviation signals be suitable in digital servo devices in which an approximate difference signal between digital setpoint / actual value signals as control or Controlled variable used will.

This can mainly be a numerically controlled factory use manchinem act, meaning the difference between the tool position and a command signal approximate for generating a calibration signal for several separate areas is approximated to the machine tool at different speeds in To star depending on the distance of the factory screw from the target position.

The invention is described in more detail for an exemplary embodiment, which is illustrated in drawings.

1 shows a block circuit diagram of a logic Circuit system according to the invention, Fig. 2a a logical comparison circuit according to the invention in block diagram representation, Fig. 2b a schematic representation of the logic comparison circuit according to Fig. 2a, Fig. 3 a Schematic representation of a complete logical comparison circuit for a Pre-comparison stage, FIGS. 4a and 4b are schematic representations of a complete logical one Pre-equalization circuit for eight pre-equalization stages, Fig. 5 is a schematic representation the switching process of the output signals obtained in FIG. 4 according to the invention.

It is clear that it is the same as in the embodiment of the invention around fluidic (flow amplifier elements with moving parts) clectronic, photoelectric, magnetic or other similar circuits can act, and that the following description, although it is based solely on Fluidies-Scha @ ungen is for illustrative purposes only.

In Fig. 1, a special logic system is illustrated in which the logic technique according to the invention is used. The logical techniques According to the invention, as said, can be adapted to any system, including a Comparison of digital signals takes place. In the present example case, the invention a numerically controlled machine tool using a setting device described in more detail. By a Bandstee tion, the dandle reader 13 is a predetermined Tape length with command information (setpoint on) supplied for a one-time cycle. The tape read control can have a group of known logic circles and a known tape feed mechanism included. By the belt control 11 is also checks whether the command positions (target positions) of the previous setting cycle have been achieved and whether the various operations of the machine tool are correct have been executed.

The tape reader 13 reads the command information from the about the Band control received band section.

In addition to having the tape set command information during each set cycle supplies, the tape also contains information on the control of auxiliary functions, such as the changeover dou machine tool shop, with the tape reader 13 issues a corresponding command. A command information is in parallel form as a 20-bit binary coded decimal word (BCD word) into the comparison device 15 transferred. It is clear that a three-dimensional adjustment of the Wenkseuges when using three separate digitalon Words can, each of which represents a position command on a different axis. For the sake of simplicity, this is only the one-dimensional one in the example Operation so that only one digital command word is supplied. The ones below in detail to be described comparison device 15 receives parallol from a known analog-digital converter 17 with feedback oin another 20-bit BCD signal, The wall-1er 17 generates a fluidic (or electronic, photoelectronic or the like.) Actual signal as a function of the position of a device to be controlled or a tool. One such transducer is shown in U.S. Patent 3,239,142 described. After this, the device to be controlled or the tool may not run, (Angular position signals then being fed to the comparison device) or adjust in a straight line.

In any case, the comparison device 15 is from the converter 17 provided information in BCD form. The comparison device 15 compares the two from the reader 13 and the converter 17 receive signals to a the Generate deviation signal representing the difference between the two signals. For certain difforences, different separate signals are used between these signals Deviation signal levels generated to a drive mechanism 19 each with different To put speeds into operation. The drive mechanism 19 can be a motor be for adjusting the machine tool 21. : According to the idea of the machine tool 21 in the direction of a target cleat with the aid of the motor 10 is approaching the position signal received from the transducer 17 at the comparison device 15 the value of the value obtained from the reading device 13 at the comparison device 15 Command signal. In doing so, the output signals emitted by the comparison device become corresponding predetermined signal difference sizes between the command and the position signals gradually smaller. If bo, for example, a drive with four speeds is required, the tool can be used when the first signal difference is exceeded Deviation signals see B. at certain speeds of 1200 inches (30,480 mm) per minute. For signals that are below this first signal difference, However, the tool can be above a certain second signal difference can be sampled at a speed of 120 zo11 (3.048 mm) per minute. In the range between the second predetermined value and a third signal difference the speed can be reduced to 12 inches (304.8 mm) per minute, at The motor can generate deviation signals that are smaller than the third signal difference driven at 1.2 inches (30.48 mm) per minute. Once the difference between the command signal and the position signal according to the adjustable accuracy the machine tool is zero or close to zero, the motor stops because the The tool is then in the target position. In the example case, there is no beach restriction an adjustment accuracy of one thousandth (1/1000) of an inch (0.0254 mm) is assumed The mode of operation of the comparison device 15 is shown in FIGS. 2a and 2b Fig. 1 illustrates. like from wig.

2a, it receives any single comparison level descriptive comparison element C1 from the corresponding bit of command word A. at the reader 13 and the position word B at the converter 17 SO an input signal A1 and B1. The predicate C1 from which 20 pieces required if the signals A and 3 are each 20 bits long, generates four output signals, namely a + signal if A1> B1, a signal if B1> A1, an O signal, where A1 = B1 and a 0 signal when A1 = B1.

Fig. 2b shows in a schematic way the single bastand parts of a Comparative element or block Ci and the preliminary links for the corresponding Input and output signals. As shown here, signals B1 and B1 become the two Inputs 25 and 27 of a fluidic AND element 23 are closed. The AND element 23 may be of the type described in the nearby Society published in February 1963 of Instrument Technology 'essay "Fluid Logic Devise and Circuite" by A.E. @itchell i.a.

(Fig. 4a) is described in which the inputs A and B and the Outputs #. #, A. B and A. 2 to inputs 25 and 27 or outputs 31, 33 and 29 of the AND element 23 ontopping.

It is assumed here, for example, that the binary 1 is due to the presence a flow and the binary 0 are represented by the absence of the flow. If A1 = 1 and B1 = 0, then there is a + (flow available). If Bi = 1 and A1 = 0, then cie - (flow not available) If A1 and B1 are both binary 0, there is no input 25, 27 the gate 23 and at none of the exits 29, 31 a flow. When Ai and Bi boide are binary 1 (there is a flow at both inputs 25, 27), then A flow appears at the output 33, while at the + and - outputs 29 and 31 there is no current.

The inputs Ai and Bi are also the inputs 37 and 39 one EXOLUSIVE = OR gate 35 supplied. The OR gate 35 can be of the aforementioned in dr Mitchell publication, Fig. 4b, be a beach drive type in which the entrances A and B and outputs A. B and A. B + A 1 B to inputs 37 and 39 or des Outputs 47 and 45 of the OR gate 35 according to FIG. 2b ent speak. If Al = 1 and Bi = t 0, a current is fed to the passage 37, which via the passage 47 to the output 45 of the OR gate 35 flows. When Bi = 1 and A, = 0, the Flow fed to the input 39 of the OR gate, so that it passes through the deu 45 to output 45 can flow. If Ai and Bi are both = O, then exist at the inputs 37 and 39 no currents. Therefore, there is no flow at the output 45 of the OR gate Before. If Ai and Bi are both 1, 37 and 39 of the occur at both inputs OR gate 35 fluid flow, whereupon a flow appears at the output 47. Thus there is no flow at the outlet 45 if only Ai or only Bi = 1. Of the Output current at the output 45 of the OR gate 35 is the input of an amplifier 49 supplied, the vou in the magazine "Flnidics", 1965, page 243, Fig. 2, can be described design, in which the control nozzle A and the outputs Ä and A to the input or the outputs F53 and 51 of the amplifier 49 according to Fig. 2b. A signal at the signal at output 45 leads to an amplified Ö signal at the output 51 of the amplifier. At 51 there is always a sign) if Ai or Bi = 1 aind. At the If there is no signal at output 45, an amplified 0 signal appears at output 53, indicating that Ai and Bi are either both = O aind or both are # 1. It shows So that when using the three legal Fluidic members 23, 35, 49 four various output signals from block 01 Fig. 2az obtained can be.

Fig. 3 is a schematic representation of a complete comparative and coding device 15 according to FIG. 1, the comparison element Ci with double input signals A1 and Bi emits the output signals - 1, Öi, +1, O1 explained in FIGS. 2a and 2b. The -1 output signal is fed to the input 571 of the fluidic NOR element 551. The NOR gate may be that shown in FIG. 1 of US Pat. No. 3,240,219 Be of construction.

In addition, the -1 output signal of the a + 1 pin becomes% efürt as a display for Bi> Ai. The + i output signal Ci + 1 of the comparison element Ci is fed to the input 47i of the NOR gate 66i. The NOR gate 66th is preferred of the same duration as the NOR gate 55i. Also, the + 1 output becomes of the comparison element Ci supplied to the Ci + 1 stage.

The Oi output signal aue the Ci element is the inputs 59, and 69i of the NOR elements 551 and 661, respectively. The Ö1 output is the input 61i of the OR gate 60i supplied. The OR gate 60i can be of the type shown in fig. 1 of the aforementioned U.S. Patent 3,240,219. (It is clear that according to the Description in column 9, cells 30 to 34, of the patent specification of the OR clusters additional control nozzles can be added to this design). An Öi + 1 signal the stage Ci + 1 becomes the inputs 58i and 68i of the NOR gate 55i and 66i and also fed to the input 63i of the OR gate 60i. This signal indicates that fpr is a non-zero state for any level higher than Ci consists and is at stage C. directly from an outlet passage (not shown) 62i + 1 of the stage Ci + 1 added to the output passage 62i + l of the stage C des OR gate 60L corresponds to the stage.

An output signal at the output 56i of the NORD member 55i becomes an input 71i of the OR gate 70i is supplied.

In addition, an output signal at the output 65i of the NOR element 66, led to the entrance 75i of the GDER link 77i.

The OR gate 70 and the OR gate 77i are preferably of the same design as the OR gate 60 @ ° An additional input signal for the OR gate 70i is fed from the Ci + 1 stage to input 78i and is present, when Ci + 1 is positive (+ i + 1) and Ci is negative (-i). An output signal from the OR gate 70i appears at exit 73i. The OR gate 77i holds an additional correspondence Input signal nm input 76i, which is also fed from the c @@@ stage Represents the state that Ci + 1 is negative (-i + 1) and Ci is positive (+1). The 'output signal from the OR gate 77i appears at the output 74 ,. The output signals at the outputs 73i and 74i are the respective inputs 81i and 88i of the OR gates 80i and 85i supplied.

The conditional gates 80i and 85i may be different from that shown in FIG. 1 of the United States patent 3 240 219 described type. The steering nozzle is not used and can be open or closed as required. The output 84i of the element 80i is arranged so that it draws a current at input 81i. An additional input signal -i-1 from the Ci-1 stage is fed to the input 82i of the conditional gate 80i. This signal is available when Bi-1 is Ai-1. The input 82i is arranged in such a way that that the input current fed to it is connected to an input 81i of the conditional gate 80i deflects occurring input current in order to receive an output current at output 83i.

The output current at output 83i is fed to input 78i-1 of Ci-1-st @ fe which corresponds to the input 78i of the OR gate 70i in the Gi stage. In the same way, an additional input signal is applied to the conditional gate 85i on Input 86i supplied. This input signal @ originates from the stage Ci-1 and is present when Ai-1> Bi-1.

The input signal 86i is normally directed to have a at input 88i leaked current to output 89i of conditional gate 85i. The output signal at output 89i is fed to the Oi-1 stage at a (not shown) Input 76i-1 of an OR element 77i-1 (not shown) corresponding to the input 76, of the OR gate 77i in the Gi stage.

It should be noted that the exit signal + Ai at Aungang 84i and the output signal - Bi at the output passage 87i allow the output signals of the Ci stage. That means that one of these signals is present when the next one is still approaching prescribing logical bad conditions that the Ci level is the size of the approximate deviation signals generated by the precalculation and coding apparatus of FIG certainly.

Hg. 4 shows a schematic representation of eight stages of the comparative and coding unit 15. To simplify the description of the device are only two decades (eight steps), it being clear that the remaining three Decades (twelve s @ ns) or more, if necessary for special applications, in in the same way are mutually related, and in agreement Work wisely. It can be easily seen that each of the stages shown in the what is essentially the same as the stage G illustrated in FIG the following description is appropriate, the reference characters used in Fig. 3 are used corresponding elements according to FIG. 4 assigned, but with the addition of a the subscript indicating the particular level to which the element belongs, instead of the i used in FIG.

The operating mode that must be described relates to the one presented above Regein 1 and 2 and takes care of the determination of the polarity and the approximate size of the difference between the command signal A and the position signal B when the highest-digit, non-zero Ci level not immediately lower-digit Steps of opposite polarity precede. at the beginning generates the highest digit, Non-zero Ci level (Cm) a signal that all the lower-digit Blocks logic circuits assigned to Ci levels.

For example, if the signals A8 and B8 at the comparison stage C8 are not the same, the output signal Ö8 is excited. This signal appears on Input 618 of the OR gate 608. The OR gate 608 generates an output, if any of its inputs are excited, eo d @ in the present example at the output 628 an output signal occurs. The signal vaa the outlet 628 becomes the stage 7 where it is fed to inputs 587, 687 and 637 of NOR gates 557, 667 and 607 is created. The NOR gate operates so that there is only an output signal can generate when none of its inputs are energized.

In this way, the signal at the output 62 is used to block the two NOR gates 557 and 667. In addition, the signal at the output gate makes 628 the OR gate 607 is effective via the output 637 in order to generate a signal at the output 627. The output signal at Augang 627 is in turn fed to stage 6, where it is the Inputs 586 and 686 of NOR gates 556 and 666, respectively, are supplied so that these NOR members are saved. In addition, the signal from port 627 becomes the input port 636 of the NOR element 606 is supplied to generate an output signal at the output 626 of the OR gate 606.

The signal appearing on passage 626 can over all lower digit Stages are continued, where it blocks the NOR gates 55 and 66 and the OR gates 60 of this level is effective in the manner described with reference to levels 6 and 7 power. It should be noted that the OR gate 607 is activated by an input signal at the input 617 can be made effective as soon as A7 = B7, nm give an @ signal sb, and sb the OR gate 606 can be made effective by an input signal at the input, once A6 = B6 to generate a signal # 6 au, because the same ratio at all Stage exists, it is clear that an inequality of the input signals Ai and Bi an any stage Ci generates an output signal Öi that all stages with a lower digit than the NOR elements 55i-1, 55i-2, etc. ... 55i-i + l assigned to Ci and 66i-1; tti-2 etc. ... 66i-i + 1 blocks. Thus, an inequality of the level blocks 8 the NOIS elements in levels 7 to 1, an inequality in level 7 the StOR elements in levels 6 to 1, etc. Accordingly, only the highest digit, non-zero Ci stage an unlocked NOR element (55i or 66i). Looking at it will therefore, assuming in the present example that A8 = 1, B, = 0 0 eats the signal generated. The NOR element 558 is the only one of the NOR elements 55i and 661 (all stages) for generating an output signal.

This is so because all NOR elements in stages 7 to 1 are protruding described are blocked, since the NOR gate 668 by the +8 (A8> B8) signal, that is present at input 678 is blocked and, because neither - 8 (B8> A8) nor 08 (As =) at input 58 or to lock the NOR gate 558 is present, consequently an output signal is present at output 568 of NOR gate 558, which is used as an input signal at input 718 of OR gate 708 is logged on. This will the OR gate 708 acts to generate an output signal at output 738 which selnereits is fed to the input 818 of the conditional gate 808. Missing in the case of an example at input 828 of gate 808 a signal appears at output 848, which in turn supplies the +, 080 output signal.

The absence of a signal at input 828 of conditional gate 808 is due on the assumed condition that stage C7 is not opposed to one of stage C8 Is polarity and therefore the signal - 7 is not generated by stage C7. The operation of the system for conditions when this signal is present is as follows described in the following. For the purposes of this example, however, that is +, 080 signal is the only output signal of the system for the logic circuit. This can be better understood by considering the following existing conditions. Each of the NOR gates 661 to 668 is blocked as described above, so that Input signals to the OR gates @ 771 to 778 connected via the NOR gate are. In addition, the OR gate generates 778 because it has only one input and because this one Passage is not excited by a signal, no output signal and consequently delivers at the input 858 of the bedington OR gate 808 no input signal. In the absence of one Input signals at input 858 can never be sent to one of outputs 878 and 898 of the conditional logical gate 888 an output signal must be present. The lack of one The output signal at the output 878 closes the existence of the .080 output signal of the syatems. It also prevents an output signal from appearing at output 898 of energizing the input 767 of the ODEN gate 777. D the input 757 of the OR gate 777 is unexcited in the corresponding catfish, is at the output 747 of the OR gate 777 No signal is present, so no input signal can be received at input 857 of the conditional gates 887 will be present, and consequently there will be fewer of the exits 877, 897 of the gate 887 excited. The absence of a signal at output 877 closes the output gas signal in 0.040 system, where the picking of a signal @@ Au @@@@ 897 causes an the stages 1 to 6 outgoing asigwales were excluded in a similar way, correspondingly how if a signal is received at output 898 in front of a viewing light, in order to - to exclude the 040 signal. Eats @@ chand the output signals +, 001 to +, 040 excluded as long as the -7- (Bu> A7) signal at stage 7 is not generated (Om-1 asked a not from Cm opposed @@@@ polarity). Thus, the OR gates get 701 to 707 no input signals from the sug @ ondneteä blocked for them NOR-Glioderu 551 to 557 or from d @@ Au @ -gaug 831 of the next Höhorstolligen states.

The example described above for A8 $ gt; B8 the output signal of the errogated system is +, 080, the -e obtained in Table 1 from A8 is approximated Deviation +00.080 regardless of the conditions of levels C1 to C6, and below the assumption that C7 is not in the state (D8> A8).

The next to complain @ iboude @atriobsart concerns the above festgo @@ tzte @agel 3 and ensures the correction of the deviation signal as soon as the highest view Zero C1 level (C @) of lower polarity is more than clae odar the immediately preceding niodri @@@ stolligen Ci levels, for the Zwc @ k @ these Deschr @@@ se assumed that, w @@ before @ stah @@@, A0 = 1, B0 = 0, Bci consideration the NOR element @@@ in the @@@@ @ shows that the signals to d @@ Aus @@@ en 578 and 598, -8 or O8, not available sin pnd d @@@@ da @ BOR-Clind 558 a, Auagang 568 a @@ @@@ @@@@. @@@@ is takes only output signal from the C8 stage the signal +8, which shows that A8 is greater than B8. The signal at the exit port 568 makes the OR gate 708 effective, on in the previously described Woise at the input 818 of the conditional gate 808 to generate a signal. If it is now assumed that the level Om- @ l (C7) has an opposite polarity from the level Om (O8), then B7> A7 and the -7 signal is passed through stage C7 to input 828 of the Gate 808 supplied. Such a signal directs the signal at input 818 in the direction of on the A @@ ang 398. whereby the output signal at output 848 disappears. Consequently the polarity change of the level Cm (C80 to Cm-1 (C7) is expressed in a signal, which blocks the +, 080 signal, although A8> B8. Now the logical Set conditions for outputs 848 and 838 of conditional gate 808 as follows : a) Provided that A8 is not larger than B8, ao none of the outlets 84 or 83 is a Exit available.

b) If A8 is greater than B8 and B7 is not greater than A7, it is on Outlet 848 has a +, 080 output indicating the magnitude of signal O (according to rule 2) is the unconditional size of A8.

c) If A8> B8 and B7> BA7, there is none at output 848 Signal present so Å8 does not control the magnitude of signal C. Instead controls A7 determines the size of signal C, which is indicated by the presence of the signal at 838 (according to rule 3) is displayed.

The output signal at input 838 becomes level 7 at input 787 of the OR gate 707 is supplied in order to generate an output signal at the output 737, to the input @@ the T @@@ 807 for the delivery of a +, 040 output signal @@@ @@@@@@@@ is being prepared as long as the Anp @ ang 827 koin -6 ring input is received from C6. As above for doa input 828 of conditional gate 808 is explained, there is only a signal at output 827 if the D6 input signal for the next lowest tunnel level 06 is greater than the A6 input signal for the new stage. When the - 6 - signal is present, there is no output signal on the Passage 847, however, instead of an output 837 there is an output signal, which is fed to the OR gate 706, in turn from the input 816 of the conditional Gate 806 an input signal to lioforn. Thus a polarity week lies between Cm (the highest tone, non-zero signal Oi-Bitotufe) and Cm-1 the control for Determine the size of Cm on Cm-1 or irgondcine low-digit level, if the polarity of Cm-1 continues in these lower digit levels. This circuit behavior is best illustrated with a specific example.

Example 7: Let A8> B8; B7> A7: B6> A6; A5 = B5.

According to rule 3 of the general flail listed above is Clearly, the magnitude of the C deviation signal will be controlled by stage 6 must, while the polarity must be determined by step 8 and in direction A (or +) lies. When checking the circuit for the feature, whether this is actually is performed, mon determines that the + appearing on input passage 678 8 signal the NOR gate 668 blocks. The O8 output signal of stage 0a is not present and the - output signal from C8 is also not present, so that NOR element is not blocked and there is a signal at output 568. This Signal energizes OR gate 708 which in turn is a signal for the input terminal 818 of the conditional gate 808 delivers. in addition, the exit of the stage C8 is applied to the OR gate 608 to produce an output signal at the gate 628 As noted above, this signal acts in conjunction with the various OR gates 60 in stages 2 to 8 to form the NOR gates 55 and 66 in each of the levels 1 to 7 au sporran. According to the hypothesis made the states of inputs A7 and B7 of stage 7 are such that B7> A7. Thus the -7 output signal occurs at stage C7, while the output signals of the stage C7 are prevented as a result of the locked NOR gates 557 and 667 Entrance 828 of the conditional gate 808 in the c8. The signal at input 818 is thereby deflected mun output 838 and occurs at output 787 of the OR gates 707 in dex level 7.

The output signal of the OR gate 707 occurs at the input 817 of the conditional Gate 807 as an entrance signal.

The B6 is larger than A6 and is also from the level U6 cin - 6 signal erzengt, which occurs at input 827 of the conditional gate 807 of the Stufo 7. The signal causes a signal to appear on output 837. The output signal at the output 837 is applied to input 786 of OR gate 706 in stage 6. Consequently the OR gate 706 is energized to a signal at the input 816 of the conditional gate 806 to generate. According to the aforementioned hypothesis A5 = B5, the - initial signal of stage U5 is not energized and no occurs at input 026 of conditional gate 806 Input signal. in this way the flow signal occurring at input 816 Unhindered to get to the output 846, so that a +, 020 output signal d @@ Eystems originates which is the size and polarity of the approximate deviation signal certainly.

In order to demonstrate how the system according to FIG. 4 with the requirements If Reyel 4 matches, one of the levels Cm-1, Cm-2, etc. is the highest @@@ @laer decade is. Example B below is used as an aid.

Belopiel 8: Assume that: A8> B8; B7> A7; B6 > A6; B5> A5 and B4> A4 Int.

These conditions lead to an example described @@ @@ before @@@ corresponding addition, including a signal at input 816 of the bediogton gate 806 occurs. However, in the protruding balapiol, since D5> A5, the signal -5 at stage C5, whereupon @@ occurs at input 826 of stage 6 to generate the om Exit 816 flows from exit 846 towards exit 836 deflect so that the +. 020 output of the system from output 846 is removed will. The signal at the output 836 is the OR-Gliod 705 of the substance 5 at the input 785 supplied. The OR gate 705 thus generates a signal at the output 735, which is sent to the Entrance 815 of the conditional gate 805 is created. Since according to d @@ given conditions B4> A4. A -4 sign is generated by the Stufo O4 and sent to 825 dos bodington Gate 805 applied to the signal present at the input passage 815 in the direction obsolete on don @ nsgung 835. Let it be b @@@@ that the level C4 is in the through dio levels C1 to C4 determined decade is the highest level and that level C5 is the size of the deviation signal (+, 010 output signal of the system) bootimmune level ge @@@ on if no - 4 signal was generated at level C4. Thus it contains the Chain of those preceding the highest, non-zero level Cm (C8), and Opposite degrees Om-1, Cm-2, etc., the highest degree (C4) one decade (decade 1). According to rule 4 set forth above, a Such a condition for a shift to the second (C2) or third (C3) highest Stage of this decade depending on the state of these stages. First it is assumed that both stages C2 and C3 are in the zero state (0) (A2 = B2: A3 = B3). Under these conditions, the Sigman at the exit port 835 becomes the entrance 101 of an OR-NOR element 100.

The OR-HOR element 100 may be of the type shown in FIG. 1 of US Pat. No. 3 240 219 described type. This link works so that a signal is input 101 occurs at the output if there is no signal at any of the inputs 102 and 103 is. If a signal is applied to one of the inputs 102 or 103, it will be Signal at input 101 deflected towards exit 105, input 102 is connected so that it picks up a 42 signal from the O2 stage, during the Input 103 is connected so that it picks up a +3 signal from stage C3. Since it was assumed that A2 = B2 and A3 = B3, none of the signals is +2 or +3 are present, and the input signal can at input 101 undeflected to the Output 104 of the OR-NOR element 100 arrive. According to rule 4a, the output signal at output 104 to stage 02, specifically to input 72 of 01ER element 702 applied to excite this gloied and to generate an output signal at output 732. this signal is in turn fed to the input 812 of the conditional gate 802. The operation then continues, as described above, as if stage C2 entered Part of the unun @@ rbrch @@@ chain from the levels Cm-1 'Om-g etc. with Cm opposite polarity would be. So if at level C1 (B1> A1) a -1 Signal is generated, the signal at passage 812 is toward the output 832 deflected, which in turn excites the OR gate 701 to a +, 001 output signal of the system so that stage C1 is made the sizing stage will.

On the other hand, if there is no -1 signal, the signal will be at the passage 812 is not deflected and a + .002 output of the system results from of level C2.

If in the previous example instead of C2 = 0, C3 = 0 on one or a + signal would have been generated at these two stages, hide from it give slightly different results. This is indicated by the assumption that stage C3 a + 3 signal (A3> B3) is generated. At the beginning it must be emphasized that, provided that a signal is generated by stage C4 (B4> A4), neither C3 nor c2 is im (-) state, since there is no requirement for the first decade of the B signal (Levels B1 to B4) would cause a value greater than the decimal digit 9 to have. Hence, if C4 is negative (-), O3 and C2 'can only be in state (+) or 0 are located. Returning to the example occurs when O3 gives a +3 signal (A3> B3) generates a signal at the input passage 103 of the OR-NOR gate 100 which deflects the signal at the input port 101 to the signal at the output 104 and to generate an output signal at output 105. (The same The result would have been if C2 were in the (+) state and the deflection signal +2 would occur at port 102; and accordingly the same result would result, if C3 and C2 were both in the state and then let the signals (+2 and +3 on you) 102 or 103 would occur0. The output signal on Passage 105 is according to the requirements of leeches 4b at the input passage 79 of the OR gate 703 in level C3. This is used to effectively collect the OR gate 703, the at the output 733 an output signal is generated at the input 815 of the conditional toro 803 is created, Wio explained above, can under the for this example assumed conditions in which the stage C4 is negative (-), the -2 signal can never be generated at stage C2 and consequently can never be generated at passage 823 a signal must be present in order to deflect the signal appearing at output 813. Consequently is according to rule 4b of the output signal of the system +, 004, The in the preceding Working method described in the examples, in which the polarity is the highest, not Zero Ci level is not negative, runs in the same way, when the highest non-zero Ci level is negative.

This is so because the circuit shown on the left of Fig. 4 on the right-hand side of FIG. 4 has corresponding elements and the circuit these members control the operation of the system for a negative deviation signal takes over. As a result, the working method of the systems for a negative difference between A and ß is not described.

The operating mode to be described next concerns the condition at which the command signal A and the position signal D are the same. From Fig. 3 is it can be seen that the O1 output signal of stage Ci leads to the NOR gates 55i and 66i to be locked. Thus, if all of the dits in the D-signals are equal to the corresponding bits in the A-signal, O-output signals, which are the lock respective associated NOR gates 55 and 66, so that the suction of any the output signals +, 001 to +, 080 and -, 001 to -, 080 of the system is prevented. Another Ergobnie for it.

that all B-bits become equal to all of the A-bits consists in that in none of the stages one of the # signals is generated. thus none of the OR gate 602 to 608 probed, and the NOR gate 110 assigned to stage C1 does not receive an input signal. The NOR gate 110 preferably coincides with the NOR gate mandrel 551 and 661 match if there are no input signals for blocking the NOR gate 110 are applied, a STOP output signal occurs at outlet 111 to stop the drive mechanism or stop motor 19 of FIG.

It is evident that although Fig. 4 and its detailed description of operation refer to a two-decade eight-step system, the operation of a Drci, Four, five or more decades system is essentially the same. The interconnections in each decade for larger systems are essentially the same as sis in fig. 4 are shown, it being clear that the OR-NOR element assigned to the first decade 100 is required for all decades except for the highest-digit decade.

5 illustrates a possible one in a schematic representation Prior application of the output signals generated in the system according to FIG. 4 for a speed range control for the drive mechanism 19 according to Fig. 1. The comparison block 120 atells the system according to Fig. 4 with the different output signals (+, 001, to +, 080 and -, 001 to -, 080) as input signals for various OR gates 121 to 126. It is lar that the special signal grouping nuch Fig. 5 nar serves as an example and that any other grouping can be used as soon as it is determined Define deviation signal Borelche. For example, one would use the +, 002 signal not group with the +, 040 and the +, 080 signal etc. How vividly the signals +, 080 and +, 040 are the input signals for the OR gate 121, the signals +, 020, +, 010 and +, 008 are the input signals for daz OR gate 122, the Signals +, 004, +, 002 and +, 001 the input signals for the OR gate 123, dis signals -, 080 and -, 040 the input signals for the OR gate 124, the signals -, 020, -, 0l0 and -, 008 the input signals for the OR gate 125 and the signals -, 004, -, 002 and -, 001 the input signals for the OR gate 126. The OR gates 121 to 126 are preferably of the same type as the OR gate 60, according to FIG. 3. The Output signals to the OR gates 121-126 are to the respective speed control devices 127 to 132 connected, which in turn supply the drive mechanism 19 signals. In addition, the STOP signal generated by the NOR gate 110 of FIG Control device 133 connected for switching on, which in turn is the drive mechanism 19 supplies a signal. The types of the control devices 127 to 132 are of the type independent of the drive mechanism. For example, if the drive mechanism 19 a at different speeds as a function of the size and polarity of the If the motor is running in both directions, the control devices can Convert 127 to 132 flow signals into electrical signals. Or if the antricbomechausimus 19 is fluid, the control devices can be fluid amplifiers. In each In this case, the control devices 127 to 152 must generate different signals can be used on the drive mechanism as commands for different speeds and act in different directions. So if the comparison block is an approximate one Deviation signal delivers 4.080 or @.040, becomes the OR element 121 orrogt, the coin side the control device 127 for the fast adjustment gear turns on. The control device 127 then orzougt a signal which the Overdrive of the Autrichomechnaismus in (+) direction triggers. In a corresponding way the various other output signals excite the OR gates assigned to them and speed control devices in the manner that the drive mechanism depending on the respective control signal from the comparison block 120 in the SCHNELI, MEDIUM, or LANCSAM gait either in positive (+) or negative (-) direction is working.

As soon as the STOP output signal appears, the control device will 133 is effective to generate a signal that turns the drive mechanism 10 off or interrupts.

As with the star devices 3.27 to 132, the type of the control device 133 depending on the type of the drive mechanism 19. The only one what is required of the controller 133 is the generation of a signal which is recognizable on the drive mechanism as an interrupt command.

What has been described above represents only one of the many possible embodiments of the invention. Further, the invention not limited to logical circuits from fluid moments (pluidics), although such circuits are preferred according to the invention.

- P a t e n t a n s p r ü c h e -

Claims (11)

Claims 1. Logical network for approximating a difference between two signals, each of which is multiple binary digits and the same binary code wherein the binary code is such that all digits in each signal are different equivalent decimal sizes are assigned, as well as to generate one of the approximation corresponding control signal for digital servos, especially numerical controlled Werkzoug machines with differently graded control speeds, characterized by several comparison devices. around simultaneously and individually the binary states of the respective pairs of digits of the same order of magnitude compare and order to view non-zero differences between pairs of individually Digits of the same order of magnitude and indicating the polarity of the non-zero difference to generate logic devices associated with the comparison devices are to match the polarity of the difference between two digital signals according to the polarity of the difference between the pair of digits being compared to generate which have the highest order of magnitude and a non-zero difference, wherein the logic devices additionally display the approximate size of the Difference between the digital signals according to the magnitude of the compared Pairs of digits that have the highest order of size and a non-zero difference have, erzengen, correction devices that correspond to the logiachen fin directions and de @ Verg @ e @ chsein @ ichtung are connected to the approximate size display suppress and a changed approximate size display according to the order of magnitude of the number pair of the next lower order of magnitude only if the difference between the pair of digits of the highest order of magnitude, which is a non-zero difference which has a polarity and the difference between the pair of digits of the next lower order of magnitude has opposite polarity, where the correction means in addition to have a further modified approximate size display instead of generating the aforementioned modified approximation size display only, if additional, consecutive pairs of compared digits, the orders of magnitude exhibit. which are immediately lower than that of the pair of the next lower Order of magnitude, having differences of opposite polarity, and where the further changed approximation size display according to the size of the Pair of lowest order of magnitude of the additional consecutive Ziffon @ pairs is generated with the opposite polarity difference, and in that the binary code is a binary-coded decimal code, the digit signals at least have eight digits to represent the equivalent of wentg at least two decades and where the logical network also has additional hearing correction devices, about the further changed proximity @@@ @@@@ unterdriiclcen and instead to generate a corrected approximate size display only if a pair of a group of pairs of digits that are the pair of the next lower order of magnitude and the further successive pairs the pair of the highest order of magnitude have in any decade. 2. Network according to claim 1, characterized in that the additional Correction means have: means for the corrected approximate size indication corresponding to the size of the pair of digits of the third highest order of magnitude in the to generate any decade only if the differences between the pair of digits of the third highest order of magnitude or between the pair of digits of the second highest Order of magnitude in any decade the same polarity as the difference between the pair of digits of B has the highest polarity with a non-zero difference, further facilities to display the corrected approximate size according to the Size of the pair of digits of the second highest order of magnitude in any given decade only to be generated when the difference is neither the third highest nor the second highest Order of magnitude in any decade the same polarity as that of the difference has a non-zero difference between the pair of digits of the highest order of magnitude, and means to suppress the corrected approximation size display which is generated by the further devices, and corrected by a different one Approximate size indicator only to be generated if the pair of digits is of the lowest order of magnitude in the any decade has the opposite polarity difference. 3. Logical network according to claim 1 or claim 2 for comparing two digital, binary-coded signals A and B, of which A represents a desired position with respect to an arbitrary zero position of a device whose position is to be controlled and through is defined and B represents the actual position of the device, which by where Ai and and Bi represent any of n binary levels in signals A and B, and where the order of magnitude assigned to each level in the signals increases for increasing values of i, and where equal orders of magnitude are assigned to corresponding Ai and Bi levels, denoted by n Comparison means (Ci) to make n individual comparisons between the binary states of A. and Bi and to generate several signals Ci to represent C. = Ai - Bi for each stage, the orders of magnitude assigned to Ai and Bi by Ci and the corresponding comparison means are determined, logic switching devices connected to the n comparison devices to generate a signal Cm representing the highest order signal of the non-zero-magnitude Ci signals at any point in time, conditional logic devices associated with the logic switching devices and the comparators are connected to: 1) an output of the l ogischen network that represents the polarity and the magnitude of the signal Cm when the signal Cm-1 'the Ci signal with the next lower magnitude than Cm, is either zero or has the same polarity as Cm, and by 2) suppress the network output signal representing the polarity and magnitude of signal C when signal Cm is 1 m m- 1 of opposite polarity to signal Cm, and a network output signal with the polarity of signal Cm and the magnitude of signal Cm- x, where Cm-x represents the Ci signal of the lowest order of magnitude of a sequence of x successive signals of lower order of magnitude of am with the opposite polarity, and wherein the Ci signals generated in each comparison device comprise: a) a signal + i, which indicates that Ai>Bi> b) a signal -i 'indicates that Bi>Ai' c) a signal Oi 'indicates that A. = Bi, and d) a signal # i indicating that Ai # Bi, and wherein the logic switching devices have: n-1 OR gates (60), which are assigned to all comparison devices (15; Ci)) with the exception of those of the lowest order of magnitude, 2n pairs of OR-not gates (55, 66), of which each pair is assigned to a corresponding one of the n comparison devices (Ci), means for supplying an output signal of each or-not gate to a conditional logic device, means for the # signal which is obtained from all comparison devices (Ci) with the exception of the one of the lowest order of magnitude is to be supplied as an input signal to the respective OR gate (60) assigned to this comparison device, devices to match the OR gates (60), which are assigned to all comparison devices with the exception of the one of the highest order of magnitude, from the OR gate, which is assigned to the comparison device of the next higher order of magnitude, to supply an additional input signal, and an input signal to feed the output signals of each OR gate (60) as an input signal to the OR-not gates (55,66) of the pair that is assigned to the respective comparison device of the next lower order of magnitude in order to determine each pair of or-not gates To block gates associated with a comparator that is of a lower magnitude than the comparator of the highest magnitude that generates a # L signal. 4. Network according to claim 3, characterized in that the logical Switching devices furthermore have: devices to the Oi signal from each comparator (Ci) is generated as an input to the pair of Or-not gates (55,66) connected to this comparison device is, and means to the -i signal generated by each comparison means is, as an input to a first gate (55) of the pair of or-not gates (55,66) connected to this comparison device, and the + i signal generated by each comparator as an input signal to a second gate (66) of the pair of or-not gates (55,66), which is connected to this comparison device, with no more than one gate of all or-not gates provide an input to the conditional logic device can conduct at any point in time, and this being a gate of all or-not gates is assigned to the comparison device of the highest order of magnitude, which is a # i-Siganl generated. 5. Network according to claim 4, characterized in that the conditional logical devices comprise: 2n pairs of OR gates (70,77), each OR gate is assigned to one of the n comparison devices, 2 (n-1) pairs of conditional logic gates (80,85), each pair being one of the comparison means (n-1) -most order of magnitude and each conditional logic gate one has first and second inputs and first and second outputs, the first output emits a first output signal only when there is an input signal the first input and no signal is fed to the second input, and the second output emits a second output signal only when input signals the first and the second input are fed, means for an output signal the first gate (55) of each pair of or-not gates (55,66) as an input signal to the first gate (70) of the pair of OR gates (70,77) to the the same comparison device are assigned, devices to an output signal from the second gate (66) of each pair of or-not gates (55,66) to to the second gate (77) of the pair of OR gates (70,77) which is the same Comparison device is assigned to means to an output narrow signal from the first gate (70) of the pairs of OR gates (70,77) (n-1) -the highest order of magnitude as an input to the first input of the first gate (80) of the pair of conditional to route logic gates (80,85) assigned to the same comparison device are, Means to receive an output from the second gate (77) of the pairs of OR gates (70,77) (n-1) -the highest order of magnitude as input signal to the first input of the second gate (85) of the pair of conditional logic To conduct gates (80,85) which are connected to the same comparison device, Means to the -i signal, which from the comparison device (n-l) -lowest Order of magnitude is generated as an input signal to the second input of the first Gate (80) of the pair of conditional logic gates (80, 85) that the Comparison facilities are assigned to the next higher order of magnitude, Means to the + i signal, which from the comparison means (n-l) -lowest Order of magnitude is generated as an input to the second input of the second Gate (85) of the pair of conditional logic gates (80,85) that are assigned to the comparison device of the next higher order of magnitude, and means to do every other output of all conditional logic gates so switch so that they emit network output signals. 6. Network according to claim 5, characterized in that the conditional logic devices further comprise: devices to provide an output signal from the second output of the first gate (80) of the pairs of conditional logic gates (80,85) as an input signal to the first gate (70) of the pairs of OR gates (70.77) to conduct, that of the comparison device of the next lower Order of magnitude are assigned to devices wn an output signal from the second Output of the second gate (85) of the pairs of conditional logic gates (80,85) as an input signal to the second gate (77) of the pair of OR gates (70,77) to conduct which is assigned to the comparison device of the next lower order of magnitude are. 7. Network according to claim 5, characterized in that the conditional logic devices further comprise: a pair of or-or-not gates (e.g. 100), which are assigned to all decades with the exception of those of the highest order of magnitude, wherein each of the or-or-not gates has a first, a second, and a third Having an input and a first output in order to generate an output signal only when there is an input signal at the first input and no input signals at the second and a third input are present, as well as a second output for an output signal only to be generated when an input signal is at the first input and at least the second or third input occurs, means to provide an output signal from the second output of the first gate of the pairs of conditional logic gates, that of the comparison device is the second, third and highest order of magnitude of a assigned to each decade as input to the first gate of each To conduct pairs of OR gates, the comparison device next lower Magnitude are assigned, facilities to provide an output signal from the second output of the second gate of the pairs of conditional logic gates, those of the comparator second, third and fourth highest orders of magnitude each Decade are assigned as input to the second of each gate of the Pairs of OR gates to be fed to the comparison device of the next lower Order of magnitude is assigned to means to obtain an output signal from the second Output of the first gate of each pair of conditional logic gates that the comparator of the lowest order of magnitude in all but one decade the lowest order of magnitude of the decade as input to the route the first input of the first gate of the pair of or-or-not gates, which are assigned to the decade of the next lower order of magnitude, institutions, an output from the second output of the second gate of each pair of conditional logic gates, those of the comparator of the lowest order of magnitude are assigned in all decades with the exception of the lowest order of magnitude, as the input signal to the first input of the second gate of the pair of or-or-not gates which are assigned to the decade of the next lower order of magnitude, Facilities, by the + i signal obtained from the comparator of the third highest magnitude every respective decade with the exception of the decade of the highest order of magnitude is, as an input signal to the second input of the first gate of the pair of Or-or-not gates assigned to the same respective decade are, devices to the -i-signal obtained by the comparison device of the third highest Magnitude of each respective decade with the exception of the decade of the highest Order of magnitude is generated as an input to the second input of the second Gate of the pair of or-or-not gates that are of the same respective one Decade are assigned, devices to the + i signal, which is from the comparison device second highest order of magnitude of each respective decade with the exception of the decade of the highest order of magnitude is generated as the input signal to the third input of the first gate of each pair of or-or-not gates to direct the are assigned to the same respective decade, facilities for the -i signal, that from the comparator of the second largest order of magnitude of each respective one Decade, with the exception of the decade of the highest order of magnitude, is generated as an input signal to the third input of the second gate of the pair of or-or-not gates to lead, which is assigned to the same respective decade, Facilities, a signal that is present at the first output of the first gate of each pair of Or-or-not gates is generated as input to the first gate of the Pairs of OR gates to guide the comparison device of the second lowest Order of magnitude in the decade to be assigned to the respective or-or-not gate is assigned, means to generate a signal at the first output of the second Gate of each pair of or-or-not gates is generated as an input signal to the second gate of the pair of OR gates to be passed to the comparison device are assigned to the second lowest order of magnitude in the decade of the respective Or-or-not gate is assigned to facilities to send a signal to the second output of the first gate of each pair of or-or-not gates is generated as an input to the first of the pair of OR gates to direct the comparison facility of the second largest order of magnitude in the Decade are assigned to which the respective or-or-not gate is assigned, and means for a signal appearing at the second output of the second gate of each pair of or-or-not gates is generated as an input signal the second gate of the pair of OR gates to pass that of the comparison device The second highest order of magnitude in the decade is assigned to the respective or-or-not gate assigned. 8. Network according to claim 5 or 7, characterized in that each comprising n comparison means: a logic gate (23) with a first one and a second input and a first and second output to provide a first output signal Generate at the correct output only if an input signal is at the local input and there is no signal at the second input and a second output signal at the second output only when there is an input signal at the second Input and no signal is present at the first input, an exclusive-or gate (35) with a first and e # second input and an output to provide an output signal to generate when the first or the second input receives an input signal, devices, to send a signal representing the binary state of Ai to the first input of the logical gate (23) and the exclusive-or-gate (39) to manage facilities, a signal representing the binary state of Bi to the second input of the logic gate (23) and the exclusive-OR gate (39) to conduct an amplifier-inverter device (49) with an input, a first output for generating a first output signal only if there is a signal at the input, and with a second output, to generate a second output signal only when there is no signal at the input is, and bodies to the output of the Exclusive-Or-Gatt with to the input of the amplifier-inverter device, the first output of the logic gate generates the signal, the second output of the logic gate the -i signal, the first output of the amplifier-inverter device the # @ signal and the second output of the amplifier-inverter device the Oi signal. 9. Network according to claim 8, characterized by: a drive mechanism (19) with variable speed to control the position of the to be controlled Device, a signal converter that is connected to the first output of all conditional logical Gate and the drive mechanism is connected to the drive mechanism at several different speeds according to the appearance of a signal at predetermined outputs of the first outputs of the conditional logic gates operate, the device automatically according to the command position in Position is brought. 10. Network according to claim 9, characterized in that the two digital signals are fluidic signals, and that the comparison devices, the logical switching devices, the conditional logical devices and the Or-or-not gates have fluidic elements. 11. Network according to claim 9, characterized in that the signal converter has: several output-OR-gates with a different number of first outputs of the conditional logic gates are connected, several control devices, which receive an output signal to one of the output OR gates and from which each is responsive to an output gate signal to produce a signal of a different level to generate, and means to supply the level signal from each control means to direct the drive mechanism and the drive mechanism in one direction and propel it at a speed determined by the signals which appear at the first output of the conditional logic gates.