DE2040150C3

DE2040150C3 - Method and circuit for demodulating phase-shifted signals

Info

Publication number: DE2040150C3
Application number: DE19702040150
Authority: DE
Inventors: Arnulf Dipl.-lng. 8000 München Streit
Original assignee: Siemens AG
Current assignee: Siemens AG
Filing date: 1970-08-12
Publication date: 1977-09-22

Description

phasengetastete Signale keine Synchronisationszeit auf. Außerdem wird eine definierte Bezugslage ohne Referenzübertragung erreicht.phase-shifted signals have no synchronization time. In addition, a defined reference position is used without Reference transmission reached.

Einzelheiten des Verfahrens nach der Erfindung und zu dessen Durchführung werden an Hand von zwei in Zeichnungen dargestellten Demodulationsschaltungcn und Impiilsdiagrammen näher erläutert. Es zeigtDetails of the method according to the invention and its implementation are based on two in Drawings shown demodulation circuits and pulse diagrams explained in more detail. It shows

Fig. 1 ein Blockschaltbild eines ersten Demodulators nach der Erfindung,Fig. 1 is a block diagram of a first demodulator according to the invention,

Fig.2 Einzelheiten des Zählers innerhalb des Demodulators nach F i g. I,FIG. 2 details of the counter within the demodulator according to FIG. I,

Fig.3 ein Impulsdiagramm zur Schallung nach Fig. 1,3 shows a pulse diagram for sounding according to Fig. 1,

Fig.4 das Blockschaltbild eines anderen Ausführungsbeispiels einer Demodulatorschaltung nach der Erfindung und4 shows the block diagram of another exemplary embodiment a demodulator circuit according to the invention and

Fig.5 ein Impulsdiagramm zur Schaltung nach Fig. 4.5 shows a pulse diagram for the circuit according to FIG.

F i g. 1 zeigt eine Deinodulationsschaltung für phasengetastete Signale zur Durchführung des Verfahrens nach der Erfindung. Alle Bauelemente dieses Ausführungsbeispiels sind Elemente aus der ECL-Logikfamilie. Das phasengetastetc Signal U_c mit einer Trägerschwingung von der Frequenz f_o wird einem Tiefpaß t zugeführt, der ausgangsseitig mit einem Eingang eines ODER-Gatters 2 verbunden ist. An Stelle des ODER-Gatters 2 kann auch eine Schwellwertschaltung verwendet werden, die je nachdem, ob an ihrem Eingang positive oder negative Spannung vorliegt, eine Ausgangsspannung abgibt, die dem 0-Pegel oder L-Pegel der in den nachfolgenden Teilen der in der Schaltung verwendeten Logik-Familie entspricht. Der zweite Eingang des ODER-Gatters 2 liegt dauernd auf einer logischen 0. Das ODER-Gatter 2 weist zwei Ausgänge auf, wobei an einem das Ausgangssignal in invertierter Form vorliegt (NOR). Die Ausgänge des Gatters 2 sind mit dem Scnsibilisierungseingang jeweils eines von zwei Zählern 3 und 4 verbunden, die beide von einer schnellen Taktfolge mit der FrequenzF i g. 1 shows a de-modulation circuit for phase-shifted signals for carrying out the method according to the invention. All components of this exemplary embodiment are elements from the ECL logic family. The phase-shifted signal U _c with a carrier oscillation at the frequency f _o is fed to a low-pass filter t, which is connected on the output side to an input of an OR gate 2. Instead of the OR gate 2, a threshold value circuit can also be used which, depending on whether there is positive or negative voltage at its input, emits an output voltage that corresponds to the 0 level or L level in the following parts of the circuit logic family used. The second input of the OR gate 2 is permanently at a logical 0. The OR gate 2 has two outputs, one of which has the output signal in inverted form (NOR). The outputs of the gate 2 are connected to the sensitization input of one of two counters 3 and 4, both of which have a fast clock sequence with the frequency

f_c ■■= m · f_o f _c ■■ = m · f _o

angesteuert werden. Die eine Hälfte des Gatters 2 wirkt als ODER-Gatter und die andere Hälfte als NOR-Gatter. Die Ausgänge der beiden Zähler 3 und 4 sind mit jeweils einem Kippeingang einer bistabilen Kippstufe 5 verbunden, an deren Ausgang das demodulierte Signal ansteht.can be controlled. One half of gate 2 is effective as an OR gate and the other half as a NOR gate. The outputs of the two counters 3 and 4 are with each connected to a flip-flop input of a bistable flip-flop 5, at whose output the demodulated signal pending.

Fig. 2 zeigt im einzelnen den Aufbau der Zähler 3 und 4 mit den Anstcucrungsleitungen vom ODER-Gaitcr bzw. NOR-Gatter zu den Sensibilisierungseingängen 8 und der Taktzufühmng an die Takteingänge 9 der einzelnen ausgewählten Kippstiifcn6und 7.Fig. 2 shows in detail the structure of the counters 3 and 4 with the Ancucrungslinien from the OR gate or NOR gate to the sensitization inputs 8 and the clock feed to the clock inputs 9 of the individual selected tilting pins 6 and 7.

Die Funktionsweise der Schaltung nach den I·' i g. I und 2 wird an Hand des Impulsdiagramnis nach Fig..'} im einzelnen erläutert. Die einzelnen, in F i g. 3 untereinander dargestellten Funktionsverläufe sind an der linken Seite mit denjenigen Bezugszeichen versehen, die in F i g. 1 die entsprechenden Stellen der Schaltung bezeichnen. In F i g. 3a ist die vom Sender zu übermittelnde Nachricht dargestellt, die aus einer binären Zeichenfolge bis etwa 5 Mcgabit/sec bestehen kann. Diese Zeichenfolge wird sendcscitig auf eine Trägcrschwingung ungefähr bekannter Frequenz /j, phasenniäßig aufgetastel. Dabei stellt eine Phasenlage ein digitales Zeichen (!.) dar und die um IHO" verschobene Schwingung das andere digitale Zeichen (0). Beispielsweise kann die Regellagc das logische L iind die Kchrlage die logische 0 bilden, wobei jedoch die Regellagc frei definiert werden kann. Die Umtastung der Trägerschwingung erfolgt stets im Nulldurchgang. Dieses phasengetastete Signal wird als Eingangssignal Uf dem Tiefpaß in Form des in Fig. 3b dargestellten Funktionsverlaufes zugeführt. F i g. 3c zeigt das Signal im Anschluß an den Tiefpaß I, wobei zu berücksichtigen ist, daß die Darstellung in F i g. 3b stark schematisiert ist, da sie in Wirklichkeit wegen des Tiefpaßcharakters der Übertragungswege dem in Fig.3c dargestellten SignalThe mode of operation of the circuit according to the I · 'i g. I. and 2 is based on the pulse diagram according to Fig .. '} explained in detail. The individual, in F i g. 3 function curves shown one below the other are on the left-hand side is provided with the reference numerals which are shown in FIG. 1 the corresponding places of the Designate circuit. In Fig. 3a shows the message to be transmitted by the sender, which consists of a binary string up to about 5 mcgabit / sec. This string is sendcscitig to a Carrier oscillation of approximately known frequency / j, shown in phase. It represents a phase position represents a digital symbol (!.) and the oscillation shifted by IHO "represents the other digital symbol (0). For example, the rule set can form the logical line and the code can form the logical 0, but the Regellagc can be freely defined. The keying of the carrier oscillation always takes place in the zero crossing. This phase-shifted signal is used as the input signal Uf of the low-pass filter in the form of that shown in FIG. 3b Functional course fed. F i g. 3c shows the signal following the low-pass filter I, which must be taken into account is that the illustration in FIG. 3b is highly schematic, since in reality, because of the low-pass character of the Transmission paths the signal shown in Fig.3c

ίο bereits sehr ähnelt. Fig.3d und 3d' zeigen den Funktionsverlauf am ODER- und NOR-Ausgang des Gatters 2. Die Nulldurchgänge 10 des Signals schalten das Gatter 2, während die Einbuchtungen 11 an den Umtastpunkten den Schaltpegel nicht überschreiten.ίο already looks very similar. Fig.3d and 3d 'show the Functional progression at the OR and NOR output of gate 2. The zero crossings 10 of the signal switch the gate 2, while the indentations 11 at the keying points do not exceed the switching level.

Somit entstehen an diesen Stellen an den Ausgängen des Gatters 2 längere Impulse bzw. Impulspausen. Die sich an das Gatter 2 anschließenden beiden Zähler 3 und 4 werden mit Hilfe einer schnellen TaklfolgeThus, longer pulses or pulse pauses occur at these points at the outputs of gate 2. the the two counters 3 and 4 connected to gate 2 are set with the aid of a fast cycle sequence

f_c — /77 · /"„ f _c - / 77 · / ""

betrieben und zählen die Breiten der Impulse aus. m sollte dabei möglichst groß sein. Die untere Grenze liegt zwcckniäßigcrweise bei /7) = Ib, wobei m keine ganze Zahl sein muß. Dieser in Fig. 3c dargestellte Takt liegt an den Takteingängen 9 der Zähler 3 und 4, wobei die Ausgänge des Galters 2 diese über die Sensibilisierungseingänge 8 für den Takt aufnahmefähig machen. Bei tiefem Potential an den Sensibilisierungseingängcn 8 werden die Taktimpulse gezählt, bei hohem Potential sind die Zähler 3 und 4 gesperrt und werden zurückgestellt. Genauso gut läßt sich ein Zähler realisieren, der mit anderen Potentialvcrhältnissen arbeitet. Somit ist die Stellung der Zähler 3 und 4 vor dem Rückstcllkommando ein Maß für die Breite der Impulspause. Beträgt die Zählerstellung m/2, so liegt eine'kurze Pause vor, beträgt sie /77, eine lange. Eine lange Pause zeigt aber ein Umtastcn des Eingangssignals Uc an, wobei eine solche im oberen Zählkanal »Schalten auf logische 0», im unteren Zählkanal »Schalten auf logisches L« bedeutet. Diese Zuordnung ist fest, wenn der Sender jeweils nach ganzen Perioden umtastet. Um Störungen auszugleichen, wird vorteilhaft ein mittlerer Wert für die Auszählung von etwa ³At · m festgelegt, der die Feststellungen »Impuls lang« oderoperated and count the widths of the impulses. m should be as large as possible. The lower limit is usually at / 7) = Ib, where m need not be an integer. This clock shown in Fig. 3c is at the clock inputs 9 of the counters 3 and 4, the outputs of the gate 2 make them receptive to the clock via the sensitization inputs 8. If the potential at the sensitization inputs 8 is low, the clock pulses are counted; if the potential is high, the counters 3 and 4 are blocked and reset. A counter that works with other potential ratios can just as well be implemented. Thus, the position of the counters 3 and 4 before the reset command is a measure of the width of the pulse pause. If the counter position is m / 2, there is a short pause, if it is / 77, a long one. A long pause, however, indicates a keying of the input signal Uc , which means "switching to logical 0" in the upper counting channel and "switching to logical L" in the lower counting channel. This assignment is fixed if the sender keyed after whole periods. In order to compensate for disturbances, a mean value for the count of about ³ At · m is advantageously established, which makes the determinations "pulse long" or

»Impuls kurz« trennt. Die Zähler 3 und 4 sind so aufgebaut, daß sie bei Erreichen dieses Wertes einen Impuls, vergleiche dazu die Fig. 3f und 3f\ an die bistabile Ausgangskippstufc5 abgeben und diese auf den richtigen Wert setzen. In den F i g. 3f und 3f' sind die"Impulse short" separates. The counters 3 and 4 are designed so that they one when this value is reached Impulse, compare FIGS. 3f and 3f \ to the Issue bistable output tilting stage 5 and set it to the correct value. In the F i g. 3f and 3f 'are the

Ausgangssignale 3 und 4 und in F i g. 3g ist das demodulicrtc Ausgangssignal U₁, dargestellt. Dieses deinodulierle Ausgangssignal U₁₁ ist gegenüber dem binären Signal der ursprünglich zu übermittelnden Nachricht nach F i g. 3a etwas phasenverschoben.Output signals 3 and 4 and in FIG. 3g shows the demodulicrtc output signal U ₁ . This deinodulating output signal U ₁₁ is opposite to the binary signal of the message originally to be transmitted according to FIG. 3a somewhat out of phase.

Der in F i g. 2 dargestellte Zähler 3 bzw. 4 zählt dann wenn die Leitung vom ODER-Gatter 2 zu der Sensibilisiemngseingängcn 8 auf niedrigem Potential ist Ist die Leitung vom Gatter 2 zu den Scnsibilisierungs eingängen 8 auf hohem Potential, so sind die Taklein günge 9 gesperrt, und über einen Rückslelleingang 15 werden die bistabilen Kippstufen 6 und 7 auf ei tu logische ((gesetzt.The in F i g. Counter 3 or 4 shown in FIG. 2 then counts when the line from OR gate 2 to Sensibilisiemngseingängcn 8 is low Is the line from Gate 2 to the Awareness Raisers inputs 8 at high potential, the Taklein günge 9 are blocked, and via a reset input 15 the bistable flip-flops 6 and 7 are set to a logical ((.

Diese Demodulationsart ist sehr störsicher. Da eim enge Bandhegicn/iing vorliegt, ist das Rauschen dei Impulsbreiten stark eingeschränkt, so daß die Zählum eine sichere Unterscheidung von schmalen und breitet Impulspausen ermöglicht. Störimpulse fälschen lcdiglicl ein einziges Zeichen, das nächste wird wieder richtifThis type of demodulation is very immune to interference. There one There is tight band control, the noise is dei Pulse widths are severely restricted, so that the count can reliably distinguish between narrow and wide Impulse breaks enabled. Interference pulses falsify a single character, the next one is correct again

empfangen, da das Schalten auf logisches L und auf die logische 0 durch getrennte Zählerkanäle bewirkt wird.received, since the switching to logical L and to the logical 0 is caused by separate counter channels.

Fig. 4 zeigt eine zweite Schallungsmöglichkeit zur Durchführung des Demodulationsverfahrens nach der Erfindung. Auch bei diesem Ausführungsbeispiel werden Hausteine der ECI.-Eogikfaniilie verwendet. Dieser Demodulator besteht aus einem Tiefpaß 13, dem das phasengelastete Eingangssignal //,. mit einer Trager· schwingung von der Frequenz f» zugeführt wird, einem Übertrager 14, weieher primärseitig mit dem Tiefpaß 13 verbunden und sckunclärscitig an einer Mittclanzapfung 15 mit einer Gleichspannungsqucllc 16 versehen ist, einem ausgangsscitig invertierenden ODER-Gatter 17, welches mit seinen beiden Eingängen an den Außenanschlüssen der Sekundärseite des Übertragers 14 liegt, einem von einer Taktfrequenz /; = '» · ΛΊ gesteuerten Zähler 18, der mit seinem Sensibilisierungscingang am Ausgang des Gatters 17 liegt und einer bistabilen Kippstufe 19, die vom Ausgang des Zählers 18 her angesteuert wird und an deren Ausgang das demodulierte Signal l>„ abgenommen werden kann. Für m gehen die gleichen bedingungen wie bei der Schaltung nach Fig. I und 2. Außerdem wird der in F i g. 2 dargestellte Zähler in gleicher Weise angesteuert wie beim ersten Ausführiingsbeispiel.Fig. 4 shows a second sounding option for performing the demodulation method according to the invention. House stones from the ECI.-Eogikfaniilie are also used in this exemplary embodiment. This demodulator consists of a low-pass filter 13 to which the phase-loaded input signal // ,. with a carrier oscillation of the frequency f »is fed to a transformer 14, which is connected on the primary side to the low-pass filter 13 and is unclearly provided with a DC voltage source 16 at a central tap 15, an output-side inverting OR gate 17, which has both inputs is on the external connections of the secondary side of the transformer 14, one of a clock frequency /; = '»· ΛΊ controlled counter 18, which is with its sensitization input at the output of gate 17 and a bistable flip-flop 19, which is controlled from the output of counter 18 and at the output of which the demodulated signal l>" can be picked up. The same conditions apply to m as in the circuit according to FIGS. I and 2. In addition, the circuit shown in FIG. The counter shown in FIG. 2 is controlled in the same way as in the first exemplary embodiment.

Die Funktionsweise der Schallung nach Fig. 4 wird an Hand des in Fig. 5 dargestellten Impulsdiagramms beschrieben, wobei die links eingezeichneten Bezeichnungen der einzelnen, untereinander dargestellten Funktionsverläufe mit den Bezeichnungen der Sehalüingspiinkte in F i g. 3 übereinstimmen. Das Eingangssignal (/,. wird nach dem Tiefpaß 13 kominuticrt. was dadurch erzielt wird, daß es dem ODER-Gatter 17 einmal direkt und einmal iir. -erlieft zugeführt wird. Zur Invertierung wird der Übertrager 14 verwendet, wobei die an der Miitelaii/.apl'ung 15 liegende Gleichspannung Ib dafür sorgt, daß beide Eingänge um die Symnietrielinie der Schaltpegel schwingen. Mit dieser Gleichspannung Ifi läßt sich auch die Breite der Ausgangsimpulse des GiUteis 17 in bestimmten Grenzen variieren. Die I'ig. 5a und ^r>b /eigen die Funktionsverläufe an den beiden Eingängen des Gatters 17. wobei der zuThe mode of operation of the sound system according to FIG. 4 is described with the aid of the pulse diagram shown in FIG. 5, the designations on the left of the individual function curves shown one below the other with the designations of the visualization points in FIG. 3 match. The input signal (/,. Is cominuticrt. After the low-pass filter 13, which is achieved in that it is fed once directly and once directly to the OR gate 17. .apl'ung 15 DC voltage lying Ib for ensures that both inputs oscillate about the Symnietrielinie the switching level. this DC voltage Ifi also the width of the output pulses of the GiUteis 17 can vary within certain limits. the I'ig. 5a and ^r> b / own the function courses at the two inputs of the gate 17. where the to

ίο übermittelnde Binärzeichenzug von Fig. 3a zugrunde liegt, während der Funktionsverlauf nach F i g. 5e den Zustand am Ausgang des Gatters 17 darstellt. Liegt dort eine lange Impulsspanne vor, so gibt der anschließende Zähler 18 bei Erreichen des Zählercndwertes von etwa V4 m einen Impuls ab. was im einzelnen im Verlauf nach F i g. 5 dargestellt ist. Dieser Impuls steuert die bistabile Ausgangskippstufc 19 an, wobei die Vorderflankc jedes aultretenden Impulses ein Kippen dieser Kippstufe 19 bewirkt. Am Ausgang der Kippstufe 19 ist die demodulierie Nachricht, welche in Fig. 5c dargestellt ist, verfügbar.ίο is based on the binary character train of FIG. 3a transmitted, while the function sequence according to FIG. 5e shows the state at the output of gate 17. If there is a long pulse span, the subsequent counter 18 emits a pulse when the counter value of approximately V4 m is reached. what in detail in the course of FIG. 5 is shown. This pulse controls the bistable output flip-flop 19, the leading edge of each emerging pulse causing this flip-flop 19 to flip. The demodulating message, which is shown in FIG. 5c, is available at the output of the flip-flop 19.

Die Schaltung nach F i g. 4 ist insbesondere dann von Vorteil, wenn das Signal nach beliebigen, ganzzahligen Vielfachen von i„/2 der Trägerschwingung getastet scir kann, da dann empfängerseitig sowieso keine feste Zuordnung zwischen Phasenlage und Binärzeichcr vorliegt (/„ = Schwingungsdauer).The circuit according to FIG. 4 is particularly advantageous when the signal is according to any integer Multiples of 1/2 of the carrier oscillation can be scanned, since then there is no fixed frequency anyway on the receiver side There is an assignment between phase position and binary character (/ "= period of oscillation).

Das bei der Demodulation phascngctasleter Signall beschriebene Verfahren nach der Erfindung läßt siel auch für Phasendiflerenzumtastung verwenden und is bei der Übermittlung von Daten und Nachrichtci einsetzbar.The phascngctasleter signal during demodulation The described method according to the invention can also be used for phase difference keying and is Can be used for the transmission of data and messages.

Hierzu 3 Blatt ZeichnungenFor this purpose 3 sheets of drawings

700 G38/700 G38 /

Claims

Patent claims:

1. A method for demodulating phase-keyed signals, which consist of a digital character sequence to be transmitted to a carrier wave, with one phase position representing one digital character (L) and the other phase position representing the other digital character (0), and keying of the carrier wave 180 degrees has always taken place in a zero crossing, and the phase-clocked signal is reshaped by means of a low-pass filter in such a way that it does not reach the zero line at those points at which the carrier oscillation was keyed and the distance between the two, the Umtastungsstel len neighboring Zero line runs is greater than that between two usual successive zero line runs of the carrier oscillation, characterized in that the respective distance between two successive zero line runs by means of a counting device (3, 4) with a significantly higher count rate (frequency / 7; f ₀ ) than the frequency ( f _o ) of the carrier oscillation is determined in that a counter output signal is only emitted when the counter (3, 4) has reached a fixed end counter value, that the cycle time of the counter to the end value is longer than the line between two usual successive zero line runs of the carrier oscillation and is shorter than the time between two zero line passes adjacent to the keying points and that the counter output signals form the edges of the digital character sequence to be transmitted.

2. The method according to claim 1, characterized in that the receiving side is fixed on the transmitter side Assignment between the phase position and the respective binary character (0 or L) recognized is that switched to zero only after a zero crossing in the negative range and only after a zero crossing in the positive range is switched to one.

3. A circuit for performing the method according to one of claims 1 or 2, characterized in that the phase-shifted signal (U ₁ -) via the low-pass filter (1) to one input of an OR which is constantly fed with a logic zero at its second input Gate (2) is performed that the OR gate (2) has two outputs, one of which (NOR) emits the inverted signal from the other (OR) that a counter (3, 4) with each of these two outputs its sensitization input (8) is connected and a clock is fed to the counter inputs (9), the repetition frequency (f _c ) of which exceeds the frequency (f _o ) of the carrier oscillation by far, so that each counter (3, 4) the clock at least up to counts to such a count that it is ensured that not a short output pulse of the OR gate or NOR gate (2) derived from 6 "of a half carrier wave, but a long output pulse of the OR gate that occurs when the phase position is keyed Gate or NOR gate (2) is present, and & 5 that the counter outputs are each connected to one of the two inputs of a bistable multivibrator (5), at whose output the demodulating

th signal (L / Jan stands.

4. Circuit according to claim 3, characterized in that that instead of the ODF.R gate (2) a threshold value circuit is provided which, depending on whether there is positive or negative voltage at its input, emits an output voltage, those of the 0 level or the L level used in the subsequent parts of the circuit Logic family.

5. A circuit according to claim 3 or 4, characterized in that at low potential (0) of the OR or NOR gate output signal the clock pulses using the appropriate counter (3, 4) are counted and the counters (3, 4) are blocked at high potential (L) and reset will.

6. Circuit according to one of claims 3 to 5, characterized in that at a clock frequency ic = ■■ trt ■ f _a (fo = frequency of the carrier oscillation) m is at least 16.

7. A circuit according to claim 6, characterized in that the count value at which the counting operation of the counters (3, 4) is completed, about ^_3/4 is ■ m.

8. A circuit for carrying out the method according to claim 1 or 2, characterized in that the phase-shifted signal (U _e ) via the low-pass filter (13) to the primary side of a transformer (14) is passed, the one at a center tap (15) at a DC voltage source (16) placed secondary side is connected to one of the two inputs of an output-side negating OR gate (17) that the output of the negating OR gate (17) is connected to the sensitization input (8) of a counter (18) is, the counting inputs (9) of which a clock is fed whose repetition frequency (f _e ) exceeds the frequency (Q of the carrier oscillation by far, so that the counter (18) counts the clock at least up to such a count value that ensures that not a short output pulse derived from half a carrier wave from the negating OR gate (17), but a long output pulse that occurs when the phase position is keyed OR gate (17) is present, and that the counter output is connected to the input of a bistable multivibrator (19), at the output of which the demodulated signal (U _a ) is present.

9. A circuit according to claim 8, characterized in that instead of the OR gate (17) one Threshold value circuit with two inputs is provided, which then always sends a signal to raise awareness of the following counter (18) outputs when one of the two inputs is above zero potential.

10. A circuit according to claim 8 or 9, characterized in that clock pulse pulses at low potential (0) of the negating OR gate output signal can be counted by means of the counter (18), which is at high potential (L) is blocked and reset.

11. Circuit according to one of claims 8 to 10, characterized in that at a clock frequency f ₀ - tn ■ fo (fo = frequency of the carrier oscillation) m is at least 16.

12. Circuit according to claim 11, characterized in that that the count value at which the counting process of the counter (18) is ended, for example

j / ₄ . nt amounts to.

13. Circuit according to one of claims 8 to 12, characterized in that the DC voltage of the DC voltage source (16) is adjustable i it.

The invention relates to a method and a circuit for demodulating phase-shifted signals, which consist of a digital character string to be transmitted, gated on by a carrier wave, one phase position being the one digital character (L) and the other phase position being the other digital Character (0) represents, and a keying of the carrier oscillation by 180 degrees always in a zero crossing has taken place, and the phase-loaded signal is reshaped by means of a low-pass filter in such a way that it follows those points at which the carrier oscillation was keyed, the zero line did not reach and the Distance between the two zero line runs adjacent to the keying points is greater than that between two usually consecutive zero line runs of the carrier oscillation.

The: assignment of the digital characters at the receiving end 0 or L for a specific phase position is clear if after a full period or a multiple of it is keyed.

Two-phase transmission of binary coded information is disclosed in U.S. Patent 1,559,642 known, according to which one phase the one binary value and the opposite phase the other binary value represents. In such a system, however, it is necessary that a synchronizing signal be on a separate ways. In the case of a transmission system over lines, this can be passed through Carry out transmission of the carrier sine wave via a separate wire. Because of the coding it has to modulated signal can be compared with the actual carrier signal in such a system, the respective binary value is defined in that the modulated signal is either in phase or in Antiphase to the carrier signal is.

A system which avoids the separate transmission of the synchronizing signal is disclosed in US Pat 30 32 745 treated. Then a coding technique is used in which the binary value not by comparing the modulated signal with the carrier signal, but by comparing each Zv cycle of the modulated signal is determined with the previous cycle. The one value becomes thereby by reversing the phase with respect to the previous cycle and the other binary value by holding in the same phase. Such a system, however, has a relatively low transmission speed on.

Another known demodulator is a phase modulated by binary coded information ^ The carrier signal is from the German interpretation 13 00 139 known. With this arrangement, due to the low-pass characteristics of the transmission line, all Harmonics of the carrier frequency are removed and the circuitry brings the filtered signal into one Rectangular shape, with an i_ .._ ,! Γ.-.,; »Η <· Rjpär / iffer of the first value

impuls uiiu lUi JV.S-- --11.->-■-·-impulse uiiu lUi JV.S-- --11 .-> - ■ - · -

Impulse as well as for each binary number of the second far two pulses are generated. In this known preservation circuits are provided that only aut Address signals which cause an amplitude change between the zero level and the level at the Have phase reversal points of the filtered signal around a given threshold value. Furthermore is a Time circuit necessary to determine the period between the pulses in order to generate a first signal, if the time between pulses is greater than half a period of the carrier frequency, the first Signal is generated for each binary digit of the first value. A device whose impulse input corresponds to the The output of the circuit and whose control input is coupled to an output of the timing circuit is used for Generation of a second signal indicating the second binary value. There is also a pulse gate circuit to select one pulse per period and to generate a clock pulse train with a Pulse per binary digit as well as an extensive register for storing the values are required.

From the magazine "Electro-Technology", 1962, November, pp 122 to 124, in particular Fig. 2, is In addition, a method for demodulating phase-shift keyed signals is known in which the The phase-shift keyed signal is reshaped in such a way that it is at those points where the carrier is around 180 degrees was keyed, the zero line was not reached and the distance between the two, the keying points adjacent zero line runs is greater than that between two ordinary consecutive ones Base line passes of the carrier. In this known method, the to be demodulated Signal amplified and then limited to maintain zero crossings. In a parallel branch there is a Signal delayed by a 1-bit pulse width is also amplified and then limited accordingly. In one Synchronous detector, the two limited signals are then evaluated in such a way that when there is In-phase of these two signals a logical "one" and, if they are in phase opposition, one logical "zero" is emitted. This known method requires a relatively long synchronization time and is because of the complex required before the actual demodulation Analog signal processing (amplification, limitation) relatively imprecise.

The invention is based on the object of a method that is greatly simplified compared to the known method and the demodulation method for phase-shifted signals is very reduced in terms of circuit complexity to create that works precisely, is suitable for high transmission speeds and is highly immune to interference having. According to the invention, which relates to a method of the type mentioned, is this object is achieved by the fact that the respective distance between two successive fillet line runs by means of a counter with a significantly higher count rate than the frequency of the Carrier oscillation is determined in that a counter output signal is only emitted is when the counter has reached a specified Er / lzählwert that the processing time of the Counting device to the final count longer than the time between two ordinary consecutive ones Zero line runs of the carrier oscillation and shorter than the time between two keying points adjacent zero line runs and that the counter output signalc is the edges of the to to be transmitted digital character string.

It occurs in this demodulation method for