DE2036847A1 - Junction field effect transistor - Google Patents

Description

Junction Field Effect Transistor The invention relates to a semiconductor device and in particular a junction field effect transistor, hereinafter abbreviated is also referred to as "FEX".

Big. 1 of the accompanying drawings shows in a schematic representation Fig. 3 is a longitudinal section of a known Schottky barrier gate FET. At the marked Part of the main surface 12 of the semiconductor substrate 11 is by diffusion or by Growth from the vapor phase formed a slightly contaminated area 13, the n-conductivity is opposite to that of the substrate 11, which has a high specific Has resistance, so as to have a pn transition at the boundary between the n-area 13 and the substrate 11 to form. On the parts of the main surface 12 of the substrate 11, which are directed against both sides of the n region 13, is a source and a drain region 15 and 16, respectively, are formed, both of which have high impurity concentrations have and are n + -conductive, so that pn + transitions 17 and 18 respectively that formed by the source region 15 and the drain region 16 with the substrate 11 There are limits. On the n-conductive region 13 is, for example, due to precipitation Applied gate electrode 19 placed, so that a Schottky barrier layer is formed is. On the surfaces of the source and the rain area, 5 and 16, source and drain electrodes 20 and 21 made of metal are attached (ohmic contact). Reference number 22 in Figure 1 identifies an insulating layer, for example made of silicon dioxide (SiO2) exists.

In the following, the functioning of a after # the preceding constructed FET described. About the source and drain electrodes 20 and 21 is a DC voltage of a predetermined size is supplied so that the source electrode is negative and the drain electrode is given positive polarity. Will be on this condition Input signals are supplied via the gate and source electrodes 19 and 20, respectively, see above these signals control the expansion of the depletion layer in the area of the Schottky gate 19 occurs so that the drain current is modulated which forms a circuit from the source region 15 passes through n-region 13 to drain region 16, so that the source and Drain electrodes 20 or 21 amplified signals. To with such field effect transistors To achieve the highest levels of amplification and cut-off frequencies, these are manufactured in such a way that that their steepness is increased as much as possible. To do this, it is desires that the resistance opposing the drain current as much as possible is decreased. (In this case, it is also preferably the length L of the gate electrode to shorten as much as possible.

Here are of course with regard to the manufacturing technique Limits).

In a barrier layer field effect transistor described above with reference to FIG however, it asks for #i: # current state of the art possible Mask alignment accuracy that the gate electrode 19 from the source electrode 20 or drain electrode 21 is separated by at least more than about 3 # µm because otherwise short circuits via gate electrode 19 and source electrode 20 or drain electrode 21 occur or are to be feared.

In the known Schottky gate FET shown in FIG Drain-current passage area made of a material which, for reasons of construction Structure necessarily have a relatively high resistivity, what has the consequence that the steepness is relatively greatly reduced and as a consequence thereof the gain and the cutoff frequency are also lower than desirable were.

Semiconductor devices have been made that do not have the aforementioned highly contaminated areas under the source and drain electrodes are equipped. In comparison to these types of FETs, the one shown in FIG Semiconductor device has a much smaller specific resistance.

The object of the invention is to overcome the disadvantages shown in the case of junction field effect transistors to eliminate.

A semiconductor device formed in accordance with the invention has on certain parts of a semi-insulator or with a high degree of specificity Resistance-equipped semiconductor substrate at least two source and drain regions high impurity concentration at a given distance and also a low impurity or doped area is provided so that the two Ends of the latter area overlap the aforementioned areas through which the slope and thus the gain and the cutoff frequency are increased.

The invention is explained in more detail below with reference to the drawings for example explained. It shows: FIG. 1 - as already mentioned - in schematic form Representation of a longitudinal section of a Schottky gate FET according to the prior art; 2A-2I show a schematic representation of longitudinal sections through a Schottky gate FET according to one embodiment of the invention in various stages of production; FIGS. 3-6 also show schematically longitudinal sections through a junction field effect transistor according to other embodiments of the invention; and shows a 0 A # i '# s- # according to Fig. 6 equivalent circuit diagram.

Referring first to the drawings, the preferred embodiments are discussed a semiconductor device according to the invention explained. Within the scope of the invention the term "junction field effect transistor" (junction FET) refers to those Types of field effect transistors that have a pn junction gate or a Schottky gate exhibit. Figures 2A to 21 show schematic longitudinal sectional views of a Schottky gate FET according to one embodiment of the invention in individual production stages. First, an insulating layer 33 made of SiO2 about 5000 Å thick by thermal Decomposition of monosilane SiH4 for about 20 minutes at a temperature of deposited about 4780C on the entire cleaned major surface 32 of the substrate 31 or dejected, which has a relatively high specific resistance having. This substrate can be made of silicon Si, germanium Ge, gallium arsenide GaAs, Gallium phosphide GaP or indium arsenide InAs or, for example, a p-type or i-type semi-insulator substrate 31 are made up of gallium arsenide GaAs (Fig. 2A). By known photo etching, for example, in a predetermined Distance parts of the insulating layer 33 removed to form two windows 34 and 35 (Fig. 2B). In these two windows 34 and 35 formed by etching to a depth of approximately 2-4% n + -conducting source and drain regions 36 and 37 with a high concentration of impurities, for example a carrier concentration of about 2 × 1018 cm -3 diffused, which differed from the substrate 33 Have employability type. The diffusion takes place for 4 hours at one temperature of about 9500 c according to the closed-tube method, with, for example, niche powder made of GaS, Ga2S3 and GaAs can be used. Over the entire major surface 32 of the substrate 31 another insulating layer 33 is then deposited from the same material described above (Fig. 2D). The parts-this insulating layer 33, which against part of the surfaces of the source and drain regions 36 and 37, respectively and a part of the surface of the substrate 31 are directed between the source and drain region is etched to form a window 40 (Fig. 2E).

In this window 40 is an n-type epitaxial layer 41 or a channel area up to a thickness of about 0.5Jwm forms, which for example has a carrier concentration of about 1 to 2 x 1016cm 5. This epitaxial layer is made by an epitaxial growth process for about 4-5 minutes on a Temperature of about 750 ° C generated for example with a mixed solution of Ga and AsCl.

On the surface of the n-type region 41 as well as on the others Areas of the main surface 32 of the substrate, except where the n-type region 41 is formed, the same kind of insulating layer 33 is deposited, as in the previous case (Fig. 2G). The areas of the insulating layer 33, the part of the surface of the n-area 41 as well as the source and drain-3 area 36 and 37 are photoetched to create windows 43 # 44 and 45 (Fig. 2H).

In the area of the etched out windows 43, 44 and 45, Schottky barrier layers are formed as gate, source and drain electrodes 46, 47 and 48 to a thickness of about 3000 to 5000 Å, which are made of prescribed conductive metals, are deposited (Fig. 21). So that the manufacture of a Schottky gate FET according to the invention is completed # Ti # this case consists of the one forming the source and drain electrodes 47 and 48 Metal, for example, made of Sn-Ag or In-Ag [steel], which are able to produce a to form ohmic contact with the n-type region 41. This ohmic contact is thereby causes the aforesaid metal to be about 5000 Å thick, for example deposited by vapor deposition or dusting, for example by means of cathode sputtering # 'ird' followed by a heat treatment of the deposited metal for about 10 Minutes in a non-oxidizing atmosphere at a temperature of about 5000C. The metal layer forming the Schottky barrier gate electrode 46 is made, for example made of Mo, Ti, Ni or Au or a layer thereof which forms a Schottky barrier layer contact or rectifier contact with the n-area 41 is able. That Schottky gate is produced by heat treatment at a temperature of less than 35,0000 Furthermore the aforementioned insulating layer 33 can be made not only of SiO but also of Si3 # 4 or SiON or a layering of it The following will the mode of operation of an FET according to the invention described so far will now be explained in more detail. As in the known FET according to FIG. 1, the source and drain electrodes are used 47 and 48 a DC voltage of a predetermined size applied so that the source electrode negative polarity and the drain electrode assumes positive polarity. Be under this Condition the gate and source electrodes 46 and 47 signals of suitable amplitude supplied, these signals control the expansion of the depletion layer that is im n region 41 is formed so that the drain current flowing from the source region 36 flows via n-region 41 to drain region 37, is controlled so that amplified Signals at the drain electrode 48 can be tapped.

The Schottky gate FET according to the invention has, in particular, a small amount contaminated n-area 41 with a relatively high specific resistance, the so is designed that at least the two ends of this region 41 is part of the Surfaces of the source and drain regions 36 and 37 are superimposed on the high concentrations of impurities and thus have a relatively low specific resistance exhibit.

This has the following advantages: Between the gate electrode 46 on the one hand and the source and drain regions 36 and 37 on the other hand always lies the n-area 41. As a result, there is no possibility of a short circuit across or in the space, as easily done with known devices of this type the case is. The distance T between the source and drain regions can thus be independent choose freely from the gate electrode, insofar as there is no short circuit between occurs in the areas mentioned.

According to the current state of production technology, this Minimally reduce the distance to about 53lm. As shown in FIG. 3, however, can this distance can be made smaller than the length L of the gate electrode 461 (L / T> 1). This can be at least a part of the n-region 41 which comprises the section forms with the highest resistance for the passage of the drain current through one Short-circuit the source and drain regions 38 and 39, which are much less specific Have resistance (generally less than 1/1000) than that of the n-range 41. This makes it possible to find the actual effective resistance for the drain current lower significantly more than was previously possible. The result shows that an FET constructed approximately in accordance with FIG. 21 offers a significantly higher slope than known FET types, from which it follows that the gain and the cutoff frequency are significantly increased.

To enable specific comparisons, some numerical values are given. For known FET types, a resistance ron about 100 to 20001t over the through the gate electrode with the source or drain electrodes specified distance. In the case of an FET according to the invention, values of 20 were obtained for this resistance to 5off. For conventional devices, values of up to about -10 mS indicated, while steepnesses of about Resulted in 20 to 40 mS.

The reverse voltage properties of such FETs are, as is known, in essentially by the size of the static capacitance across the gate electrode and determines the drain area or the gate capacitance. The lower the gate capacitance the higher the reverse voltage. The gate capacitance decreases inversely proportional to the distance between the gate electrode and the drain region.

4 illustrates a staggered gate Schottky gate FET according to another embodiment of the invention, in particular for use at high reverse voltages suitable is. In this embodiment the gate electrode 462 is separated from the drain region 37 as far as possible, i. H.

drawn closer to the side of the source region 36, so the distance to widen as much as possible between the gate electrode 462 and the drain region 37, d. H. by the offset distance Os.

Fig. 5 shows a junction field effect transistor according to a further embodiment of the invention. In this embodiment it is in the n range 411 another p-region 421 is formed. This p-region 421 is by diffusion, generated by zinc (Zn) in the p-region 411, for example.

In this p-region 421 there is an ohmic contact with an all-metal electrode 463, made for example of molybdenum (Mo), titanium (ei), chromium (Cr) or In-Ag alloy.

6 shows a Schottky gate FET with a dual gate structure according to a further embodiment of the invention. In the embodiments according to the figures 21, 3, 4 and 5, only one gate was provided, while in the embodiment 6, a gate region 412 between a source region 361 and a drain region 371 is formed and a further combined drain and source region 50 with n + conductivity, similar to the source and drain regions 361 and 371 on the bottom is arranged essentially in the middle of the n-area 412. The areas of Surface of the n-region 412 that lie against the intermediate distances that are by the combined drain and source region 50 with the source or. Drain area 361 and 371 are first and second Schottky barrier gate electrodes 4641 and 4642 provided.

7 shows an equivalent circuit diagram of a junction REX for the Dual-gate structure according to FIG. 6. D. h. the circuit structure of FIG. 7 is similar to that of FIG FET arrangement equivalent in which two junction FET5 Q1 and Q2 are used, where the drain of one of the two connects to the source of the other connected is.

A junction FET arrangement of this construction has the advantage that This not only achieves the same effect as in the case of an FET according to FIG. 21 lets, rather it is also achieved that the equivalence series resistance Rs, the occurs between the connected drain and source terminals, much less than is the case with known FETs in dual-gate construction. So is that too increases the slope in a very effective way.

It should also be mentioned that in FIGS. 3 - 6 with FIG Corresponding parts are provided with the same reference numerals, so that on their separate description was omitted.

Claims (6)

Claims 1. Junction field effect transistor with a semiconductor substrate with a relatively high specific resistance, with at least two heavily contaminated Areas that enclose a source and a drain area, their conductivity from that of the substrate at certain points on the substrate surface in a predetermined Distance is different, with one between the two heavily contaminated areas arranged slightly contaminated area of the same conductivity type as the low contaminated area and with common electrodes that are most low contaminated Area and are attached to the heavily contaminated areas, d u r c h it is not noted that the slightly contaminated area (41, 411, 412) the heavily contaminated areas (36, 361, 50, 37, 371) # bridged so that both Ends of the slightly contaminated area are part of the source (36, 361) and the Overlay the drain area (37, 371). 2. The transistor of claim 1, d a d u r c h g e k e n n z e i c Note that at least one of the heavily contaminated areas (36 361, 50, 37 371) delimited spaces is narrower than the length of the gate electrode (46, 461, 462, 463, 46414642). 3. The transistor of claim 1, d a d u r c h g e k e n n z e i c Note that the gate electrode (46, 461, 462, 463-, 4641-4642) is closer to the source region (36, 361) is arranged as the drain area lying in the heavily contaminated area (37, 371), 4. The transistor of claim 1 d a d u r c h g e k e It is noted that the slightly contaminated area (411) is a partial area (421) which is in ohmic contact with the gate # electrode (463) and a Has conductivity that is opposite to that of the slightly contaminated area (4113 is. 5. The transistor of claim 1, d a d u r c h g e k e n n z e 1 c h n e t that the heavily contaminated area has three sub-areas, d. H. the Source area (361), the drain area (371) and a combined source and Drain area (50), which is also about halfway between the source and Drain area is arranged and that gate electrodes t4641 or 4642) on such Parts of the surface of the slightly contaminated area (412) are attached, which with separate source and drain areas against the combined source and and drain area are directed towards delimited spaces. 6. The transistor of claim 1 d a d u r c h g e k e n n z e i c h n e t that the gate electrode (46, 461, 462, 4641, 4642) is a Schottky barrier layer forms between the electrode and the slightly contaminated area (41, 412). Blank page