DE2033701A1 - Device for examining the statistical distribution of measurement results - Google Patents

Description

Patent attorney Dlpl, -lng. R. BEETZ Mn.

Dlpl-lng. K. LAMPRECHT

Dr.-lng. R.BEE TZ Jr. 8 Munich 22, Steiiwdorfetr. 10

410-15.882P 7.7.1970

SOCIETE D'ELECTRONIQUE INDUSTRIELLE ET NUCLÄAIRE (S.E.I.N.)

Paris (France)

Device for studying the statistical distribution

of measurement results

The invention relates to a device for examination the statistical distribution of measurement results, in particular to obtain the course of the simple (histogram) or! integral statistical distribution of successive measurement results.

Amplitude analyzers are already known which _{supply the t} profile of histograms. However, they are pretty | expensive if only used for such a purpose. Electromechanical devices have also been developed to meet the requirements. They basically consist of groups of counters that are connected to simple logic circuits. However, as soon as a pain analysis is to be carried out with these devices, they become very expensive because their price is linear with the number of channels t for classifying the measurement results. B33l8) -HdP (7)

INSPECTED

They are also difficult to operate because the operator does not see the histogram, but see the ones displayed by hand Must record values. Finally, devices of this type work relatively slowly (maximum J50-50 measurement results / sec).

According to the known state of the art, a statistical analysis of digital or numerical data is carried out Measurement results mostly either in addition, time-consuming manually to transmit a number of printed values, or for processing with a computer, whereby however a A suitable program must be available and the measurement results must be brought into a form that can be entered into the computer (Magnetic tape, punched tape, punched cards, etc.).

It is therefore the object of the invention to provide a device create that

is specially developed for statistical analysis, allows a pain analysis at a lower price compared to the known devices,

works quickly and thus allows the classification of more than 1000 measurement results / sec, and

During the analysis, a constant visual display of the course of the simple or integral statistical Distribution of the measurement results.

This task is performed in a device for studying the statistical distribution of successive Measurement results in numerical or digital form with a Umsebzstufe, which converts each received measurement result into a number which is stored in a register which specifies the associated class, where the ZaJh (I N possible values can accept; ' a memory with at least N channels, the control of which is determined by this number, and one

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arithmetic register that stores the content of that channel of the Receives the memory whose address corresponds to this number and stores it back in the same address incremented by one; and a device for analyzing the content of the channels of the memory achieved in that the conversion stage comprises: one - first counting stage, which is the value of the lower limit of the examined Area of the measuring results, an oscillator which is connected to the serial input of the first counting unit connected,

a comparator for comparing the received measurement result with the number stored in the first counting stage, and a second counting stage, whose serial input is also on the oscillator is connected and which forms the register in which the number can be stored which indicates the class of the result, the conversion stage being constructed in such a way that, if the received measurement result is less than the number stored in the first counting stage, the comparator sends a signal outputs, which sets the second counter stage to the address of the first channel of the memory;

if the result received is greater than that in the first Number stored in the counting stage 1st, the lack of the signal specified by the comparator means the delivery of pulses of the The oscillator triggers the two counting stages and the comparator by 'a signal that interrupts the delivery of the impulses, indicates the equality of the received result with the number stored in the first counting stage, where the second counting stage is at an address which, depending on the value of this measurement result, is between that of the second and the (N-I) th channel of the memory may lie; and, if the second counter stage reaches the address of the Nth channel of the memory before the output of the signal, the second Counting level emits a signal that your counting up at this

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BATH ORIGINAL

Address as well as that of the first cooling stage.

The invention is explained in more detail with reference to the drawing, in the single figure of which an exemplary embodiment of the device according to the invention is shown.

The measurement results whose statistical analysis is to be carried out (hereinafter referred to as information), occurs in digital form at an output register 1 of a measuring device 2, which operates digitally or an analog-digital - has converter stage. The output register 1 controls parallel several AND gates 2, the opening command is formed by a signal A, the outside by a programmer 4 is generated when information contained in the output register 1 can be stored. This command triggers the parallel transport of the contents of the output register 1 to an intermediate (interface) register 5, that the information in a known way logically stores (integrated DTL logic) so that the device can be adapted to the various existing types is guaranteed by converters.

The information stored in register 5 is converted into a Level 6 is fed in, which converts the information and its value into an integer between 0 and 99, which is the associated Class designated.

Level 6 basically has the following assemblies:

A first counting stage 7, which is connected in parallel via AND gates 8 to a unit 9 of digital commutators or switches is connected, in which at the beginning of the analysis the Saves the beginning of the region of interest of the measurement results, -d. H. the value below which a received information

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should not contribute to the formation of the histogram. That Signal A, which is output to all AND gates 8, controls at the time of storing the information, the setting of the counter level 7 to the value, the dlee unit stores;

a high-frequency oscillator 10, which is connected to the series (numbers) input of stage 7 connected 3äb and by a command B is triggered, which is issued by the programmer 4 immediately after the store command A;

a second counting stage 11, whose serial (numbers) input " is connected to the oscillator 10 via a k-fold reducer 12 and therefore the k-th part of the number of counts pulses delivered by the oscillator to stage 7;

and a comparator IJ for comparing the Register 5 and the level 7 stored numbers.

Under these conditions the following operation occurs:,

If 'The total in the register 5 ^J-stored number is smaller than the vomit more -Number te in the counting stage 7 prior to the delivery of the command B, that is, if the information has a value ι

below the area of interest is classified

class "0". For this purpose, the Ver. ■, *

same Ij5 from a signal s that clears the counting levels!

or sets it to zero and compensates for the effect of signal B siert, so that not a single pulse generated by the oscillator 10

If the comparator IJ outputs the signal s Äicht, i. H. if the information has a value above the initial value, command B increments the counter step by step at the rate of the oscillator 10 and the counting stage 11 at the rate of the oscillator 10, divided by k, until the comparator IJ

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by means of a signal u, which ends the counting up of these two counting stages, indicating the equality between the numbers stored in register 5 and in counting stage 7. The number stored in the counting stage 11 therefore represents the class of information received, which is determined by the difference between its actual. Value (stored in register 5) and the output value (stored in stage 7), divided by k, because the counter 1 \ only counts by one every k pulses emitted by oscillator 10. The width of each class in The area of interest is thus determined by the value of k.

If the counting stage 11 reaches the value "99" before the comparator 1J> has delivered its signal u, which corresponds to a value of the information which exceeds the upper limit of the area of interest, it is assigned the class "99": the counting stage 11 itself now interrupts the counting up by means of a signal ν and therefore remains at the value "99".

So if the information received has a value:

below the initial value, it belongs to class "0",

within the range of interest, to a class between "1" and "99", according to their value and that of k,

and above the ■ area of interest, for Class "99".

After these operations are finished, the count level increases 11, which stores the class of information received, via a logic 14 (the purpose of which will be explained in more detail below will be) the control of a core memory 15 with 100 channels. This triggers a Speieher cycle that the Transmission of the content of the channel whose address is given by the

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ZUhlstufe 11 is stored in an arithmetic register of the memory causes. A signal G emitted by the programmer 4 then counts up the register 16 by one, its Content is again transferred to the memory 15 at the specified address.

In this way, each received information, which has previously been converted by stage 6 according to its value into a number between "0 ^h and" 99 ", increments by one the content of that channel of the memory 15 which is designated by this number In this way, the histogram of the process examined is developed in memory 15 as a function of the arrival of the information.

Each time the signal A is output from the sequencer 4, it counts a counter stage 12 which is provided with a Vorsähleinrichtung, by one high. When the number of information received reaches the value stored in the latter device, a signal fed into the memory I5 triggers an interruption of the storage.

The constant visualization of the contents of the memory during "the summation phase" is carried out on the screen of a television set 18 which has a generator 1 * 9 for picture and synchronization signals. For this purpose, stage 19 controls continuously and cyclically the incremental counting stage 20, which has a storage capacity of 100 and, like stage 11, controls memory 15 via logic Ik . Logic 14 is formed by OR gates and allows control depending on their state via counting stage 11 or stage 20. In this second In this case, each interrogation of the memory allows the content of a channel to appear in arithmetic register 16 and its status

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a logic 21 is transmitted in series or series-parallel operation to an intermediate register 22, the additional register is called because it is on before each transfer May or may not be set to zero. (It can be seen, however, that a systematic reset to zero takes place at the end of an interrogation cycle of all channels of the memory). The information contained in register 22 is first in a digital-to-analog converter 25 and then fed into the generator 19 which generates the image signal (video signal). Thanks to this cyclical query all channels of the memory 15 thus shows the screen constantly either the course of the histogram if the additional register 22 is constantly reset to zero, or the integral distribution curve if it does not zero after visualizing the content of each channel is reset.

After the end of the totalization, the analysis of the content of the memory can be made as before by the television set 18, but also by means of a potentiometer control t he s 24 that goes to the output of the digital-to-analog converter angeeohloeeen 1st, as well as by means of a printer 26, the is connected directly to the output of the additional memory 22. The printer 25 can also be controlled by the register 5 in this way be that in the same line the content of the ■ one channel and the value of the classified in this channel Information prints

Finally, there are two switches on the counting stage 11 (not shown) through which the two limits of an acceptance range of the measured values can be defined. A logic connected to the two switches provides impulses:

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At a first output, if the stored number is below the limit value A,

at a second output, if the number is between A and B, at a third output if the number is greater than B.

The signals emitted by this logic can then be used to trigger an external process by the the number of measured values is reduced. .

The device according to the invention can in particular be as follows Operational parameters have:

Maximum feeding frequency: 1000 Maximum number of significant digits in the measurement: 4, Extension to 6 possible

Memory capacity: 9999 events / channel.

The device according to the invention has two major areas of application, namely in scientific research and in industry.

The measured values obtained in scientific research are very often from the limit of the possibilities of measurement, influences directions, be it that the physicist is sohwaohe Tries to clarify interaction, be it that a restriction takes place through background noise. In these In both cases, a statistical analysis of the measurements is recommended to determine the mean value and the typical To determine deviation.

In the industry, the uses are numerous, particularly for the control of tablecloth. The course of the histogram enables the actual accuracy to be determined -

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INSPECTED I / '; ■ · ■;

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of production (statistical deviation) and its shift (deviation between the mean and the target value). The exact knowledge of these values enables a effective countermeasures for the assembly line and thus an improvement in the finished product, a reduction in the number the reject pieces and in this way an increase in Profitability. Application examples of the device according to the invention are

Comparison of the frequencies of two atomic clocks Stabilization of an oscillator; Highlighting a mode of multiple vibrations;

Checking the correct conformity of accelerations in the "white noise" during vibration tests;

precise numerical determination of surface conditions;

Control of dispersions in the manufacture of high-precision components (e.g. resistors «capacitors);

Examination of the reliability by means of successive statistical controls during the aging phases of Products;

Checking the dimensions of workpieces after machining}

Control of bulk goods (food industry);

statistical control of a continuously fluctuating quantity by means of successive random samples.

The example shown can be used in different Way to be modified · So the device is not on the 'Use of 100 classes is limited, but they can be used with

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any number N of classes. In addition, it is not necessary that the classes of interest Area have the same width, e.g. B · the widths can be chosen to be exponentially different.

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Claims (4)

-12 claims Device for examining the statistical distribution of successive measurement results in digital form with a conversion stage which converts each received measurement result into a number that is stored in a register that indicates the associated class, where the number N can assume possible values; a memory with at least N channels, whose modulation is determined by this number, and an arithmetic register that stores a Number receives the content of the channel of the memory whose address corresponds to this number through this stage, and stores it back in the same address increased by one and a device for analyzing the content of the channels of the memory, characterized in that that the conversion stage includes: a first counting stage (7), which the value of the lower limit saves the examined area of the measurement results, an oscillator (10) connected to the series input of the first Counting stage (7) connected 1st, a comparator (13) to compare the received measurement result with the number stored in the first counting stage (7), ' and a second counting stage (11) whose series input is also connected to the oscillator (10) and which the Forms register in which the number can be stored which specifies the class of the measurement result, the conversion stage so is constructed that if the received measurement result is smaller than the number stored in the first counting stage (7), the comparator (15), emits a signal (s), 009837/1393 which sets the second counting stage (11) to the address of the first channel of the memory (15); if the received measurement result is greater than that in the first counting stage (7) stored number, the lack of the from the comparator (13) output signal (s) the output of pulses from the oscillator (10) to the two counting stages triggers and the comparator (13) by a signal (u), that interrupts the delivery of the pulses, the equality of the received result with that in the first counting stage (7), the second counting stage (11) is at an address that is in Depending on the value of this measurement result, it can be between that of the second and the (N-I) th channel of the memory; and, if the second counting stage (11) has the address of the Nth channel of the memory (15) before the output of the signal (u) reached, the second counting stage emits a signal (v) that its counting up at this address as well as the the first counting stage (7) stops. 2. Apparatus according to claim 1, characterized by a coaster (12) between the oscillator (10) and the second counting stage (11), - 3. Apparatus according to claim 1, characterized in that the facility for creating the content of the channels of the Memory (15) has: ' a register (20) for controlling the memory (15) * a television set (18) whose generator (19) for the synchronizing and image signals controls the incremental increment of this register (20) by one, so that the transmission at each step the content of a channel of the memory (15) in the arithmetic register (ΐβ) ^! is effected, and 009887/1393 eintη digital-to-analog converter (23) * of the content of the arithmetic register (16) receives to feed it as an analog variable in the Oeneraor (19). 4. Apparatus according to claim 3, characterized by an additional arithmetic register (22) «which is connected in parallel to the arithmetic register (16) of the memory (15) 1st and may or may not be reset to zero while reading the contents of two consecutive ones Channels, whereby the digital-to-analog converter is connected to the additional register (22). 009887/1333