DE202019006044U1 - Display substrate and display device - Google Patents

Abstract

A display substrate (100) comprising:
a base substrate (1000, 2000) comprising a display region (1100) and a bonding region (1200, 2200) located on at least one side of the display region (1100);
a plurality of subpixels (110, 210) located in the display area (1100);
a plurality of data lines (1101) located in the display area (1100) and configured to provide data signals to the plurality of subpixels (110, 210);
a plurality of data leads (1220, 2220) located in the bonding region (1200, 2200) and electrically connected to the plurality of data leads (1101);
at least one group of contact pads located in the bonding region (1200, 2200), the at least one group of contact pads comprising a plurality of contact pads (1210, 2210), at least one of the plurality of contact pads (1210, 2210) comprising a first contact pad metal layer (1215, 2215) and a second contact pad metal layer (1217, 2217), the first contact pad metal layer (1215, 2215) being located on a side of the plurality of data leads (1220, 2220) remote from the base substrate (1000, (1217, 2217) and being electrically connected to one of the plurality of data leads (1220, 2220), the second contact pad metal layer (1217, 2217) being located on a side remote from the base substrate (1000, 2000) remote side of the first contact pad metal layer (1215, 2215) and electrically connected to the first contact pad metal layer (1215, 2215), and wherein the second contact pad metal layer (1217, 2217) covers an edge of the first contact pad metal layer (1215, 2215);
a first insulation layer (1230, 2230) located in the bonding region (1200, 2200), the first insulation layer (1230, 2230) being located in gaps between the plurality of contact pads (1210, 2210) and covering edges of the plurality of contact pads (1210, 2210) and exposing the surfaces of the plurality of contact pads (1210, 2210) facing away from the base substrate (1000, 2000); and
a bonding area insulation layer (1243, 1244, 2243, 2244) located in the Bond region (1200, 2200), and wherein a portion of the bond region insulation layer (1243, 1244, 2243, 2244) is located between the first contact pad metal layer (1215, 2215) and the plurality of data leads (1220, 2220), wherein the bond region insulation layer (1243, 1244, 2243, 2244) extends continuously from a position between the first contact pad metal layer (1215, 2215) and the plurality of data leads (1220, 2220) to a position between the first insulation layer (1230, 2230) and the base substrate (1000, 2000).

Description

TECHNICAL AREA

Embodiments of the present disclosure relate to a display substrate and a display device.

BACKGROUND

With the increasing demand of users for organic light-emitting diode (OLED) display devices and higher requirements for product quality, the rapid development of the display device has been promoted. In recent years, the resolution of the display device is getting higher and higher, and the frame of the display device is getting narrower and narrower, so the pixel size of the backplane circuit of the display device is gradually reduced.

SUMMARY

At least one embodiment of the present disclosure provides a display substrate comprising a base substrate, a plurality of subpixels, a plurality of data lines, a plurality of leads, at least one group of contact pads, and a first insulation layer. The base substrate comprises a display region and a bonding region located on at least one side of the display region; the plurality of subpixels are located in the display region; the plurality of data lines are located in the display region and are configured to provide data signals to the plurality of subpixels; the plurality of data leads are located in the bonding region and are electrically connected to the plurality of data lines; the at least one group of contact pads is located in the bonding area, the at least one group of contact pads comprising a plurality of contact pads, at least one of the plurality of contact pads comprising a first contact pad metal layer and a second contact pad metal layer, the first contact pad metal layer is disposed on a side of the plurality of data leads remote from the base substrate and is electrically connected to one of the plurality of data leads, the second contact pad metal layer is disposed on a side of the first contact pad metal layer remote from the base substrate and is electrically connected to the first contact pad metal layer, and the second contact pad metal layer covers an edge of the first contact pad metal layer; the first insulation layer is located in the bonding area, the first insulation layer is disposed in gaps between the plurality of contact pads and covers edges of the plurality of contact pads and is configured to expose the surfaces of the plurality of contact pads remote from the base substrate.

For example, in the display substrate provided by at least one embodiment of the present disclosure, a vertical distance between a surface of a side of the first insulation layer remote from the base substrate and the base substrate is not greater than a vertical distance between a surface of a side of the plurality of contact pads remote from the base substrate and the base substrate.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the edges of the second contact pad metal layer are covered by the first insulation layer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the at least one group of contact pads includes a first group of contact pads and a second group of contact pads, the first group of contact pads and the second group of contact pads each include a plurality of contact pads, the second group of contact pads is arranged on a side of the first group of contact pads near the display area, and the plurality of data leads are electrically connected to the first group of contact pads and the second group of contact pads in a one-to-one correspondence.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at least a portion of the first insulation layer is located in gaps between adjacent contact pads of the first group of contact pads.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at least a portion of the first insulation layer is located in gaps between adjacent contact pads of the second group of contact pads.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at least a portion of the first insulation layer is located in gaps between adjacent contact pads of the first group of contact pads and is further located in gaps between adjacent contact pads of the second group of contact pads.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of contact pads of the first group of contact pads are arranged in at least a first row, and the plurality of contact pads of the second group of contact pads are arranged in at least a second row; a row direction of the first row and a row direction of the second row are parallel to an extending direction of a side edge of the display region facing the bonding region, and at least a part of the first insulation layer is located in gaps between the first row and the second row.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at least one of the plurality of subpixels includes a pixel driving circuit, a first planarization layer, a first transfer electrode, a second planarization layer, and a light-emitting element, wherein the first planarization layer is located on a side of the pixel driving circuit remote from the base substrate to provide a first planarization surface, and includes a first through-hole, the first transfer electrode is located on the first planarization surface and is electrically connected to the pixel driving circuit through the first through-hole, the second planarization layer is located on a side of the first transfer electrode remote from the base substrate to provide a second planarization surface, and includes a second through-hole, the light-emitting element is located on the second planarization surface and is electrically connected to the first transfer electrode through the second through-hole, wherein the first insulation layer and the second planarization layer are provided on the same layer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel driving circuit includes a first display area metal layer, the first display area metal layer and the first contact pad metal layer are provided on the same layer, and the first transfer electrode and the second contact pad metal layer are provided on the same layer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel driving circuit includes a thin film transistor, the thin film transistor includes a source electrode and a drain electrode, and the source electrode and the drain electrode are located in the first display area metal layer and are located on the same layer as the first display area metal layer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at least one of the plurality of subpixels further comprises a passivation layer, and the passivation layer is located between the pixel driver circuit and the first planarization layer and includes a passivation layer through-hole, wherein the pixel driver circuit and the first transfer electrode are further electrically connected through the passivation layer through-hole; the display substrate further comprises a second insulation layer located in the bonding region, wherein the second insulation layer is located between the first contact pad metal layer and the second contact pad metal layer and covers edges of the first contact pad metal layer, the second insulation layer includes first contact pad through-holes, and the second contact pad metal layer is electrically connected to the first contact pad metal layer through the first contact pad through-holes; wherein the second insulation layer and the passivation layer are provided on the same layer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at least one of the plurality of subpixels further comprises a storage capacitor, the storage capacitor comprises two capacitor electrodes, the thin film transistor further comprises a gate electrode, at least one of the plurality of data lines and one of the two capacitor electrodes of the storage capacitor are provided on the same layer as the gate electrode.

For example, the display substrate provided by at least one embodiment of the present disclosure further comprises: a bonding region interlayer insulation layer located in the bonding region, disposed between the plurality of contact pads and the plurality of data leads, and disposed between the first insulation layer and the base substrate; a first bonding region gate insulation layer located in the bonding region and disposed on a side of the bonding region interlayer insulation layer close to the base substrate; and a second bonding region gate insulation layer located in the bonding region, disposed between the first bonding region gate insulation layer and the bonding region interlayer insulation layer, and laminated with the bonding region interlayer insulation layer; wherein the second bonding region gate insulation layer comprises first contact pad through-holes, the bonding area interlayer insulation layer comprises second contact pad through-holes, and at least one of the plurality of data leads is electrically connected to at least one of the plurality of contact pads through the first contact pad through-holes and the second contact pad through-holes.

For example, in the display substrate provided by at least one embodiment of the present disclosure, at least one of the plurality of subpixels further comprises a display region interlayer insulating layer, a first display region gate insulating layer, and a second display region gate insulating layer, wherein the display region interlayer insulating layer, the first display region gate insulating layer, and the second display region gate insulating layer are each provided on the same layer as the bond region interlayer insulating layer, the first bond region gate insulating layer, and the second bond region gate insulating layer; the display region interlayer insulating layer is disposed between the gate electrode and the source electrode and the drain electrode, the first display region gate insulating layer is disposed on a side of the display region interlayer insulating layer close to the base substrate, and the second display region gate insulating layer is disposed between the display region interlayer insulating layer and the first display region gate insulating layer; and the two capacitor electrodes include a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being provided on the same layer as the gate electrode and the second capacitor electrode being provided between the display region interlayer insulating layer and the second display region gate insulating layer.

For example, the display substrate provided by at least one embodiment of the present disclosure further comprises a third bonding region insulation layer, wherein the third bonding region insulation layer is disposed in the bonding region and provided on a side of the first insulation layer and the plurality of contact pads remote from the base substrate to cover the first insulation layer and the plurality of contact pads, and the third bonding region insulation layer comprises third contact pad vias to expose surfaces of the plurality of contact pads.

For example, the display substrate provided by at least one embodiment of the present disclosure further comprises an encapsulation layer and a third display region insulation layer located in the display region, wherein the encapsulation layer is disposed on a side of the light-emitting element remote from the base substrate, the third display region insulation layer is disposed on a side of the encapsulation layer remote from the base substrate, and wherein the third bond region insulation layer and the third display region insulation layer are disposed on the same layer.

For example, the display substrate provided by at least one embodiment of the present disclosure further comprises an auxiliary conductive layer, wherein the auxiliary conductive layer is located in the bonding region and is provided on a side of the third bonding region insulation layer remote from the base substrate, wherein the auxiliary conductive layer comprises a second transfer electrode pattern located in the bonding region, and wherein the second transfer electrode pattern is electrically connected to the plurality of contact pads through the third contact pad vias.

For example, the display substrate provided by at least one embodiment of the present disclosure further comprises an auxiliary electrode layer provided on the third display region insulating layer, wherein the auxiliary electrode layer and the second transfer electrode pattern are provided on the same layer.

For example, in the display substrate provided by at least one embodiment of the present disclosure, in the bonding region, a height of the second transfer electrode pattern relative to a surface of the base substrate is not greater than a height of the surface of the third bonding region insulating layer relative to the surface of the base substrate.

At least one embodiment of the present disclosure further provides a display device comprising the display substrate provided by any of the embodiments of the present disclosure.

There is further described a manufacturing method for a display substrate, comprising: providing a base substrate, the base substrate comprising a display region and a bonding region located on at least one side of the display region; forming a plurality of subpixels in the display region; forming a plurality of data lines in the display region, the plurality of data lines gen is configured to provide data signals to the plurality of subpixels; forming a plurality of data leads in the bonding region, the plurality of data leads electrically connected to the plurality of data lines; forming at least one group of contact pads in the bonding region, the at least one group of contact pads comprising a plurality of contact pads, at least one of the plurality of contact pads comprising a first contact pad metal layer and a second contact pad metal layer, the first contact pad metal layer configured to be located on a side of the plurality of data leads remote from the base substrate and electrically connected to one of the plurality of data leads, the second contact pad metal layer configured to be located on a side of the first contact pad metal layer remote from the base substrate and electrically connected to the first contact pad metal layer, and the second contact pad metal layer covering an edge of the first contact pad metal layer; and forming a first insulation layer in the bonding region, the first insulation layer being disposed in gaps between the plurality of contact pads and covering edges of the plurality of contact pads and being configured to expose the surfaces of the plurality of contact pads facing away from the base substrate.

For example, in the manufacturing method, forming the first insulation layer comprises: causing a height of the surface of the first insulation layer relative to a surface of the base substrate to be not greater than a height of the surface of the plurality of contact pads relative to the surface of the base substrate.

For example, in the manufacturing method, forming the plurality of subpixels in the display region comprises: forming the plurality of subpixels in the display region, wherein at least one of the plurality of subpixels comprises a pixel driver circuit, a first planarization layer, and a light-emitting element, forming the plurality of subpixels in the display region comprises: forming the pixel driver circuit on the base substrate, forming the first planarization layer on a side of the pixel driver circuit remote from the base substrate to provide a first planarization surface, and forming a first through-hole in the first planarization layer, forming a first transfer electrode on the first planarization surface, wherein the first transfer electrode is electrically connected to the pixel driver circuit through the first through-hole, forming a second planarization layer on a side of the first transfer electrode remote from the base substrate to provide a second planarization surface, and forming a second through-hole in the second planarization layer, wherein the first insulation layer and the second planarization layer is formed by the same second insulating material layer; forming the light emitting element on the second planarization surface, wherein the light emitting element is electrically connected to the first transfer electrode through the second through hole.

For example, in the manufacturing method, forming the first insulating layer and the second planarization layer by the same first insulating material layer includes: depositing a first insulating material layer on the base substrate after the plurality of contact pads and the pixel driving circuit are formed; performing a patterning process on the first insulating material layer so that a part of the first insulating material layer located in the display region is formed as the second planarization layer and the second via hole is formed in the second planarization layer, removing a part of the first insulating material layer overlapping with the plurality of contact pads, and thinning a part of the first insulating material layer located in the bonding region and at edges of the plurality of contact pads to form the first insulating layer.

For example, in the manufacturing method, forming the first insulating layer and the second planarization layer by the same first insulating material layer includes: depositing a first insulating material layer on the base substrate after the plurality of contact pads and the pixel driving circuit are formed, the first insulating material layer comprising a photosensitive resin; exposing the first insulating material layer using a gray tone mask plate or a halftone mask plate, developing a photoresist that is exposed so that a part of the first insulating material layer located in the display region is formed as the second planarization layer and the second through hole is formed in the second planarization layer, removing a part of the first insulating material layer overlapping with the plurality of contact pads, and thinning a part of the first insulating material layer located in the bonding region and at edges of the plurality of contact pads to form the first insulating layer.

For example, in the manufacturing method, performing a patterning process on the first insulating material layer comprises: Patterning the first insulating material layer using a gray tone mask plate patterning process or a halftone mask plate patterning process.

BRIEF DESCRIPTION OF THE DRAWINGS

• 1A ist eine schematische Darstellung einer dreischichtigen laminierten Metallschicht (Ti/Al/Ti), die von einer Elektrodenschicht getragen wird;
• 1 B ist ein schematisches Diagramm des Abfalls einer Kante einer dreischichtigen laminierten Metallschicht (Ti/Al/Ti);
• 2A ist eine schematische Draufsicht auf ein Anzeigesubstrat gemäß mindestens einer Ausführungsform der vorliegenden Offenbarung;
• 2B ist eine schematische Draufsicht auf einen Bondbereich eines Anzeigesubstrats gemäß einer Ausführungsform der vorliegenden Offenbarung;
• 3A ist eine schematische Querschnittsansicht entlang der Linie M1-N1 des in 2B gezeigten Anzeigesubstrats;
• 3B ist eine schematische Querschnittsansicht entlang der Linie M2-N2 des in 2B gezeigten Anzeigesubstrats;
• 3C ist eine schematische Querschnittsansicht entlang der Linie M3-N3 des in 2B gezeigten Anzeigesubstrats;
• 4 ist eine schematische Querschnittsansicht eines Anzeigebereichs des in 2B gezeigten Anzeigesubstrats;
• 5A ist eine schematische Querschnittsansicht entlang der Linie M1-N1 des in 2B gezeigten Anzeigesubstrats gemäß einer anderen Ausführungsform der vorliegenden Offenbarung;
• 5B ist eine schematische Querschnittsansicht des Anzeigebereichs des in 2B gezeigten Anzeigesubstrats gemäß einer anderen Ausführungsform der vorliegenden Offenbarung;
• 6 ist eine schematische Draufsicht auf einen Bondbereich eines anderen Anzeigesubstrats gemäß einer Ausführungsform der vorliegenden Offenbarung;
• 7A ist eine schematische Querschnittsansicht entlang der Linie M4-N4 des in 6 gezeigten Anzeigesubstrats gemäß einer Ausführungsform der vorliegenden Offenbarung;
• 7B ist eine schematische Querschnittsansicht eines Anzeigebereichs des in 6 gezeigten Anzeigesubstrats gemäß einer Ausführungsform der vorliegenden Offenbarung;
• 8A ist eine schematische Querschnittsansicht entlang der Linie M4-N4 des in 6 gezeigten Anzeigesubstrats gemäß einer anderen Ausführungsform der vorliegenden Offenbarung;
• 8B ist eine schematische Querschnittsansicht des Anzeigebereichs des in 6 gezeigten Anzeigesubstrats gemäß einer anderen Ausführungsform der vorliegenden Offenbarung; und
• 9A bis 9M sind Prozessdiagramme eines Herstellungsverfahrens eines Anzeigesubstrats.

In order to make the technical solution of the embodiments of the present disclosure clear, the drawings of the embodiments are briefly described below. It is obvious that the drawings described below relate only to some embodiments of the present disclosure and are therefore not limitative of the present disclosure.

• 1A is a schematic representation of a three-layer laminated metal film (Ti/Al/Ti) supported by an electrode layer;
• 1B is a schematic diagram of the drop of an edge of a three-layer laminated metal film (Ti/Al/Ti);
• 2A is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure;
• 2 B is a schematic plan view of a bonding region of a display substrate according to an embodiment of the present disclosure;
• 3A is a schematic cross-sectional view along the line M1-N1 of the 2 B display substrate shown;
• 3B is a schematic cross-sectional view along the line M2-N2 of the 2 B display substrate shown;
• 3C is a schematic cross-sectional view along the line M3-N3 of the 2 B display substrate shown;
• 4 is a schematic cross-sectional view of a display area of the 2 B display substrate shown;
• 5A is a schematic cross-sectional view along the line M1-N1 of the 2 B shown display substrate according to another embodiment of the present disclosure;
• 5B is a schematic cross-sectional view of the display area of the 2 B shown display substrate according to another embodiment of the present disclosure;
• 6 is a schematic plan view of a bonding region of another display substrate according to an embodiment of the present disclosure;
• 7A is a schematic cross-sectional view along the line M4-N4 of the 6 shown display substrate according to an embodiment of the present disclosure;
• 7B is a schematic cross-sectional view of a display area of the 6 shown display substrate according to an embodiment of the present disclosure;
• 8A is a schematic cross-sectional view along the line M4-N4 of the 6 shown display substrate according to another embodiment of the present disclosure;
• 8B is a schematic cross-sectional view of the display area of the 6 shown display substrate according to another embodiment of the present disclosure; and
• 9A until 9M are process diagrams of a manufacturing process of a display substrate.

DETAILED DESCRIPTION

In order to make the objects, technical details and advantages of the embodiments of the present disclosure clear, the technical solutions of the embodiments are described in conjunction with the drawings relating to the embodiments of the present disclosure in a clear and fully understandable manner. Obviously, the described embodiments are only a part, but not all, of the embodiments of the present disclosure. Based on the embodiments described here, the person skilled in the art can obtain other embodiments without inventive work, which should fall within the scope of the present disclosure.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first,""second," etc. used in this disclosure are not intended to indicate any order, amount, or importance, but to distinguish various components. The terms "comprise,""contain,""include,""including," etc. are intended to indicate that the elements or items listed before these terms include the elements or items listed after these terms and their equivalents, but do not exclude the other elements or items. The terms "connect", "connected", etc. are not intended to define a physical or mechanical connection, but may directly or indirectly include an electrical connection. "On", "under" and the like are used only to indicate a relative positional relationship, and if the position of the object described is changed, the relative positional relationship may be changed accordingly.

At present, the resolution of the organic light-emitting diode (OLED) display device is getting higher and higher, and the frame of the display device is getting narrower and narrower, so the pixel size of the backplane circuit of the display device is gradually reduced. As the width of the traces in the backplane circuit and the line pitch of the traces are reduced, the metal residue and etching loss in the etching process of the backplane circuit in the actual manufacturing process can easily cause the backplane circuit to be short-circuited, which affects the yield of the display device.

The inventors found through their research that the anode of the OLED may be wet etched when manufacturing the backplane circuit of the display device. During the etching process, the acidic etching solution used may easily cause severe over-etching of other metal layers already formed under the anode. For example, the display device includes a transfer electrode metal layer or a source-drain metal layer located under the OLED, the transfer electrode metal layer is electrically connected to the anode, and the source-drain metal layer is electrically connected to the transfer electrode metal layer. During the patterning process of the anode, the over-etching phenomenon of the anode tends to cause a greater impact on the transfer electrode metal layer or the source-drain metal layer.

As in 1A For example, as shown in FIG. 1, in the case where the transfer electrode metal layer or the source-drain metal layer is made of a multi-metal laminated layer 10 (e.g., a three-metal (Ti/Al/Ti) laminated layer 10 consisting of titanium 11, aluminum 12, and titanium 13), the aluminum metal layer 12 located in the center is easily over-etched by the acidic etching solution, resulting in an under-etching phenomenon and also causing the titanium metal layer 11 to be suspended from the edge of the electrode pattern located on the aluminum metal layer 12. As shown in FIG. 1B As shown, in other subsequent manufacturing processes of the display device, such as a high pressure spray preparation process, the titanium metal 14 in the suspended part is easily peeled off. The peeled off titanium metal 14 is generally in the form of a long strip, which is easy to remain in the display device, thus causing a signal short circuit in the backplane circuit of the display device.

In addition, when the display device displays an image, residues of the falling titanium metal easily cause poor brightness and darkness of the display device. In particular, in the bonding area of the display device for bonding external circuits, the problem of poor brightness and darkness is particularly prominent.

At least one embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes a base substrate, a plurality of subpixels, a plurality of data lines, a plurality of data leads, at least one group of contact pads, and a first insulation layer. The base substrate includes a display region and a bonding region located on at least one side of the display region; a plurality of subpixels are located in the display region; the plurality of data lines are located in the display region and are configured to provide data signals to the plurality of subpixels; the plurality of data leads are located in the bonding region and are electrically connected to the plurality of data lines; the at least one group of contact pads is arranged in the bonding region, the at least one group of contact pads comprising a plurality of contact pads, at least one of the plurality of contact pads comprising a first contact pad metal layer and a second contact pad metal layer, the first contact pad metal layer is located on a side of the plurality of data leads remote from the base substrate and is electrically connected to one of the plurality of data leads, the second contact pad metal layer is located on a side of the first contact pad metal layer remote from the base substrate and is electrically connected to the first contact pad metal layer, and the second contact pad metal layer covers an edge of the first contact pad metal layer; the first insulation layer is arranged in the bonding region, the first insulation layer is arranged in gaps between the plurality of contact pads and covers edges of the plurality of contact pads and is configured to expose the surfaces of the plurality of contact pads facing away from the base substrate.

The display substrate described above contains the first insulation layer, which is located in the bonding region of the display substrate, in the gaps between the plurality of contact pads and covers the edges of the plurality of contact pads, so that in the manufacturing process of the display substrate, the first insulation layer can protect the edges of the metal layers of the plurality of contact pads, thereby preventing the etching solution used in the subsequent process of forming a transfer metal layer and the like from etching the metal layers in the exposed contact pads, and preventing the peeling phenomenon of the titanium metal of the suspended part, thereby improving the product yield and reliability of the display substrate.

Hereinafter, a display substrate and a display device provided according to embodiments of the present disclosure will be described with reference to the accompanying drawings.

It should be noted that in various accompanying drawings of the present disclosure, in order to describe clearly, a spatial rectangular coordinate system is established on the basis of the base substrate of the display substrate, and the positions of various structures of the display substrate are explained accordingly. In the spatial rectangular coordinate system, an X-axis and a Y-axis are parallel to the plane of the base substrate, and a Z-axis is perpendicular to the plane of the base substrate.

At least one embodiment of the present disclosure provides a display substrate, and 2A is a schematic plan view of the display substrate according to an embodiment of the present disclosure. 2 B is a schematic top view of a bonding region of a display substrate according to an embodiment of the present disclosure. The display substrate is configured for, for example, an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device.

As in 2A and 2 B For example, as shown, the display substrate 100 includes a base substrate 1000. The base substrate 1000 includes a display region 1100 and a peripheral region surrounding the display region 1100, and the peripheral region includes at least one bonding region 1200. In 2A Four bonding regions are shown, but embodiments of the present disclosure are not limited thereto. The display region 1100 includes a pixel array and scan lines (gate lines), data lines, power lines, sense lines, etc., configured to provide control signals, data signals, voltage signals, etc. to the pixel array.

In the present embodiment, the display region 1100 includes a plurality of subpixels and a plurality of data lines 1101. The plurality of data lines 1101 include signal lines 1102 (e.g., gate lines G) extending in a first direction (the X-axis direction in 2A) and signal lines 1103 (e.g. data lines D) extending in a second direction (the Y-axis direction in 2A) The display substrate includes a plurality of leads 1220 (i.e., data leads) located in the at least one bond region 1200. These signal lines extend or lead to the bond region located on at least one side of the display region 1100. For example, the signal lines 1103 are electrically connected to corresponding leads and thus may be electrically connected to a drive chip, flexible circuit board, etc. located in the bond region.

The at least one bonding region 1200 is located, for example, on one side of the display region 1100 to electrically connect an external circuit to the display substrate through a bonding process. For example, the external circuit may include a flexible circuit board on which a chip is mounted (e.g., Chip on Film, COF), and a control chip or a drive chip and the like are arranged on the flexible circuit board. The bonding region may further be configured to be directly electrically connected to the chips. The display substrate 100 may further include at least one group of contact pads, and the at least one group of contact pads includes a plurality of contact pads 1210 arranged in the at least one bonding region 1200. The plurality of leads 1220 are electrically connected to the plurality of contact pads 1210 in one-to-one correspondence. One end of the plurality of leads 1220 extends to the display region 1100 and is electrically connected to signal lines (e.g. data lines) in the display region 1100, and the other end of the plurality of leads 1220 extends to the at least one bonding region 1200 and is electrically connected to the plurality of contact pads 1210. The plurality of leads 1220 are formed, for example, on the same layer as the signal lines in the display region 1100, and the plurality of leads 1220 and the signal lines in the display region 1100 can thus be formed integrally. Or the plurality of leads 1220 and the signal lines in the display region 1100 can be formed on different layers, being connected by through holes in an insulation layer between the plurality of supply lines 1220 and the signal lines in the display area 1100 are electrically connected to one another.

As in 2 B For example, as shown, in each of the at least one bonding region 1200, at least one group of contact pads includes a plurality of contact pads 1210. The plurality of contact pads may be further divided into a first group of contact pads 1210 and a second group of contact pads 1210'. The second group of contact pads 1210' is located on one side of the first group of contact pads 1210 near the display region 1100, and at least one of the plurality of leads 1220 is connected to the first group of contact pads 1210 and the second group of contact pads 1210'. The plurality of contact pads 1210 are arranged in a direction in which the display region 1100 faces the side edge of the at least one bonding region 1200, and may be arranged in a single row or in multiple rows, for example in two rows referred to as L1 row (i.e., a first row) and L2 row (i.e., a second row). The L2 row is located between the L1 row and the display area. As described above, the embodiments of the present disclosure do not limit the number of rows of the plurality of contact pads. Intervals are arranged between a plurality of contact pads 1210 in the same row, and further intervals are arranged between a plurality of contact pads 1210 in different rows. As shown in 2 B As shown, a cutting line M1-N1 passes through a contact pad 1211 and a contact pad 1212 in the L1 row, a cutting line M2-N2 passes through a contact pad 1213 and a contact pad 1214 in the L2 row, and the cutting line M3-N3 passes through the contact pad 1212 in the L1 row and the contact pad 1214 in the L2 row.

For example, the display substrate further comprises a first insulating layer, and at least a portion of the first insulating layer is located in gaps between adjacent contact pads of the first group of contact pads. For example, at least a portion of the first insulating layer is located in gaps between adjacent contact pads of the second group of contact pads. In another example, at least a portion of the first insulating layer is located in the gaps between adjacent contact pads of the first group of contact pads and further in the gaps between adjacent contact pads of the second group of contact pads.

For example, in some examples of the present disclosure, the height of the surface of the first insulation layer relative to the surface of the base substrate is not greater than the height of the surface of the plurality of contact pads relative to the surface of the base substrate. As in 2 B As shown, the display substrate may further comprise a first insulation layer 1230 disposed on the bonding region 1200. The first insulation layer 1230 covers at least a portion of the edges of the plurality of contact pads 1210. The plurality of contact pads 1210 comprise at least one contact pad metal layer, e.g., multiple contact pad metal layers. The top metal layer of the at least one contact pad metal layer of the plurality of contact pads 1210 is exposed to provide electrical connection.

3A is a schematic cross-sectional view along the line M1-N1 of the 2 B shown display substrate. 3B is a schematic cross-sectional view along the line M2-N2 of the 2 B shown display substrate. 3C is a schematic cross-sectional view along the line M3-N3 of the 2 B As shown in 3A , 3B and 3C , the at least one contact pad metal layer of the plurality of contact pads 1210 may include a first contact pad metal layer 1215 and a second contact pad metal layer 1217, and the second contact pad metal layer 1217 is laminated on a side of the first contact pad metal layer 1215 remote from the base substrate 1000. In the above-mentioned structure, the topmost metal layer of the at least one contact pad metal layer of the plurality of contact pads is the second contact pad metal layer 1217. The first insulation layer 1230 includes gaps corresponding to each of the plurality of contact pads 1210, thereby being configured to expose the surfaces of the plurality of contact pads 1210 remote from the base substrate 1000. A region outside the plurality of contact pads 1210 in the at least one bonding region 1200 is covered by the first insulation layer 1230, and the region includes, but is not limited to, gaps between contact pads of the same row and gaps between contact pads of different rows. Therefore, in the manufacturing process of the display substrate, the first insulation layer can protect the edges of the plurality of contact pads and prevent the etching solution in the subsequent patterning process from etching the exposed edges of the contact pads, thereby improving the product yield and reliability of the display substrate.

The base substrate 1000 may be, for example, a glass plate, a quartz plate, a metal plate, a resin plate, etc. For example, the material of the base substrate may comprise an organic material, for example, the organic material may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, Polyethylene terephthalate and polyethylene naphthalate, etc., the base substrate 1000 may be a flexible substrate or a non-flexible substrate, and the embodiments of the present disclosure are not limited thereto.

When the thickness of the first insulating layer is large, there is a large segment difference between the surface of the first insulating layer relative to the base substrate and the surface of the plurality of contact pads, and poor contact between the external circuit and the plurality of contact pads in the bonding region is easy to occur when a bonding process is performed on the external circuit in the bonding region. In particular, in the flexible touch display device, due to the thicker laminated metal layer of the plurality of contact pads in the bonding region, in the case where the bonding process is performed on the external circuit, poor contact between the external circuit and the plurality of contact pads in the bonding region is easier to occur at grooves on the top metal layer of the plurality of contact pads, which further affects the product yield of the display device. Therefore, in at least one example of the embodiment, the thickness of the plurality of contact pads is further controlled to avoid the poor contact in the bonding region.

In the present embodiment, the edges of the plurality of contact pads include the edges of the plurality of contact pads in a circumferential direction, that is, in a cross-sectional view obtained by passing a cross-sectional line in either direction through at least one of the plurality of contact pads, the edges of the at least one of the plurality of contact pads are covered by the first insulation layer.

As in 3A , 3B and 3C For example, as shown, the first insulation layer 1230 covers the edges of the second contact pad metal layer 1217. The second contact pad metal layer 1217 is located on the first contact pad metal layer 1215 and covers the edges of the first contact pad metal layer 1215 to prevent the first contact pad metal layer 1215 from being exposed and attacked by the etching solution during the subsequent patterning process, while the second contact pad metal layer 1217 may form a step to enlarge the contact pad between the first insulation layer 1230 and the second contact pad metal layer 1217 and thereby prevent the second contact pad metal layer 1217 from peeling off. The height Hl of the surface of the first insulating layer 1230 relative to the surface of the base substrate 1000, that is, the vertical distance from the surface of the first insulating layer 1230 to the surface of the base substrate 1000, is not greater than the distance H2 from the surface of the second contact pad metal layer 1217 of the plurality of contact pads 1210 to the surface of the base substrate 1000. Setting the height of the first insulating layer 1230, that is, the thickness of the first insulating layer 1230, can improve the poor contact phenomenon in the bonding area and increase the product yield. In addition, the second insulating layer 1250 is arranged between the first contact pad metal layer 1215 and the second contact pad metal layer 1217. And the second insulation layer 1250 covers the edges of the first contact pad metal layer 1215 to prevent the edges of the first contact pad metal layer 1215 from being attacked by the etching solution in the subsequent patterning process.

In at least one example, the second contact pad metal layer 1217 on the second insulation layer 1250 extends further outward than the edges of the first contact pad metal layer 1215 to cover the edges of the first contact pad metal layer 1215, i.e., on the surface of the base substrate 1000, the orthographic projection of the second contact pad metal layer 1217 covers the orthographic projection of the first contact pad metal layer 1215. The above-mentioned structure can reduce the segment difference at the edges of the plurality of contact pads and is advantageous when the first insulation layer 1230 covers the edges of the second contact pad metal layer 1217.

As in 3A , 3B and 3C , the height Hl of the surface of the first insulating layer 1230 relative to the surface of the base substrate 1000, that is, the vertical distance between the surface of the first insulating layer 1230 and the surface of the base substrate 1000, is not greater than the distance H2 between the surface of the contact pads 1210 and the surface of the base substrate 1000. It should be noted that in the example shown in the figures, the surface of the plurality of contact pads 1210 is the surface of the second contact pads metal layer 1217 that is farthest from the base substrate 1000. Controlling the height of the first insulating layer 1230, that is, the thickness of the first insulating layer 1230, can improve the poor contact phenomenon in the bonding area and increase the product yield.

As for example in 3A , 3B and 3C As shown, the plurality of leads 1220 of the display substrate 100 are each located under the corresponding contact pads 1210. The display substrate 100 further includes a bonding area buffer layer 1241 on the base substrate 1000 and a first bonding area gate insulation layer 1242 on the side of the bonding region buffer layer 1241 remote from the base substrate 1000. The plurality of leads 1220 are located on the first bonding region gate insulation layer 1242. One end of the plurality of leads 1220 is electrically connected to the plurality of contact pads 1210. For example, the contact pad 1211 in the L1 row, the contact pad 1212 in the L1 row, the contact pad 1213 in the L2 row, and the contact pad 1214 in the L2 row are each electrically connected to one of the plurality of leads 1220, and in the present example, the plurality of leads 1220 are located in the same layer so that the plurality of leads 1220 can be manufactured in the same patterning process.

In other examples, the plurality of leads 1220 may also be arranged in different layers, e.g., the leads configured to connect to the plurality of contact pads 1210 of the L1 row are located in a layer closer to the base substrate, while the leads configured to connect to the plurality of contact pads 1210 of the L2 row are located in a layer relatively farther from the base substrate (but still between the plurality of contact pads of the L2 row and the base substrate). Therefore, the distances between the plurality of leads 1220 in the same layer are increased, the risk of lead-to-lead interference and short circuits is reduced, and the display device with high pixel resolution can be advantageously formed. Moreover, the plurality of leads 1220 in the same layer can be manufactured in the same patterning process. For example, the display substrate 100 may further include a second bonding region gate insulation layer 1243 located in the bonding region and a bonding region interlayer insulation layer 1244, and the bonding region interlayer insulation layer 1244 is located on a side of at least one lead 1220 remote from the base substrate 1000. The plurality of contact pads 1210 are arranged on the bonding region interlayer insulation layer 1244. The bonding area interlayer insulating layer 1244 is located in the bonding area and between the plurality of contact pads 1210 and the first insulating layer 1230 and the base substrate 1000. The second bonding area gate insulating layer 1243 is located between the first bonding area gate insulating layer 1242 and the bonding area interlayer insulating layer 1244 and is laminated with the bonding area interlayer insulating layer 1244. The second bonding area gate insulating layer 1243 includes first contact pad through holes 1216, the bonding area interlayer insulating layer 1244 includes second contact pad through holes 1219, and at least one of the plurality of leads 1220 is electrically connected to the contact pad through the first contact pad through holes 1216 and the second contact pad through holes 1219. The plurality of leads 1220 connected to the contact pads 1210 of the L1 row extend through the gaps between the contact pads of the L2 row in the bonding area and then extend to the display area 1100, so that the plurality of contact pads 1210 have larger arrangement spaces and can avoid mutual interference or short circuit with the plurality of leads 1220 connected to the contact pads 1210' of the L2 row.

As in 3C As shown, the second bonding area gate insulation layer 1243 includes a plurality of first contact pad vias 1216, the bonding area interlayer insulation layer 1244 includes a plurality of second contact pad vias 1219, and 3C shows three first contact pad through holes 1216 and three second contact pad through holes 1219 included in the contact pad 1212 and the contact pad 1214 along the section line M3-N3. In other examples of the present disclosure, the number of first contact pad through holes 1216 and the number of second contact pad through holes 1219 may be a multiple, e.g., 2 or 4. The present disclosure is not limited to the number of first contact pad through holes 1216 and the number of second contact pad through holes 1219.

In other examples, the plurality of leads 1220 may also be arranged in different layers, e.g., the leads configured to connect to the contact pads 1210 of the L1 row are arranged in a layer closer to the base substrate, while the leads configured to connect to the contact pads 1210 of the L2 row are arranged in a layer relatively farther from the base substrate (but still between the plurality of contact pads and the base substrate). Therefore, the distances between the plurality of leads 1220 in the same layer are increased, the risk of interference and short circuits between the plurality of leads is reduced, and the display device with high pixel resolution can be advantageously formed. Furthermore, the plurality of leads 1220 in the same layer can be manufactured in the same patterning process. The plurality of leads 1220 in different layers can be manufactured in different patterning processes.

The material of the first insulation layer 1230 can be, for example, inorganic insulation materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. or organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, etc. The material of the first insulating layer is not specifically limited in the present embodiments. The material of the leads may be made of a metal or an alloy, e.g. a single-layer metal structure or a multi-layer structure of molybdenum, aluminum, titanium, etc. The material of the first contact pad metal layer may be made of a metal or an alloy, e.g. a single-layer or multi-layer metal structure of molybdenum, aluminum, titanium, etc.

For example, in some embodiments of the present disclosure, the plurality of subpixels in each pixel unit in the pixel array of the display region of the display substrate include a pixel driver circuit, a first planarization layer, a first transfer electrode, a second planarization layer, and a light-emitting element. The first planarization layer is located on a side of the pixel driver circuit remote from the base substrate to provide a first planarization surface, and includes a first through-hole, the first transfer electrode is located on the first planarization surface and is electrically connected to the pixel driver circuit through the first through-hole, the second planarization layer is located on a side of the first transfer electrode remote from the base substrate to provide a second planarization surface, and includes a second through-hole, the light-emitting element is located on the second planarization surface and is electrically connected to the first transfer electrode through the second through-hole, and the first insulation layer and the second planarization layer are provided on the same layer.

For example, the pixel driver circuit may include a thin film transistor, a storage capacitor, etc., may be implemented in various types, such as a 2T1C type (i.e., with two thin film transistors and a storage capacitor), and may further include more transistors and/or capacitors based on the 2T1C type to have functions of compensation, reset, light emission control, detection, etc. The embodiments of the present disclosure do not limit the type of the pixel driver circuit. For example, in some embodiments, the thin film transistor directly and electrically connected to the light emitting element may be a driver transistor or a light emitting control transistor, etc.

In the embodiments of the present disclosure, “provided on a same layer” means that two functional layers (e.g., the first insulation layer and the second planarization layer) are in the same layer and are formed by the same material in the hierarchical structure of the display substrate, i.e., in the manufacturing process, the two structural layers may be formed by the same material layer, and the required patterns and structures may be formed by the same patterning process. For example, after the material layer is first formed, the two structural layers may be formed by the material layer by means of a patterning process.

In some embodiments of the present disclosure, 4 For example, a schematic cross-sectional diagram of the display area of the 2 B The plurality of subpixels 110 in each pixel unit in the pixel array of the display area of the display substrate are configured to realize light emission driving and light emission control. One of the plurality of subpixels 110 includes a pixel driving circuit 1120, a first planarization layer 1130, a first transfer electrode 1180, a second planarization layer 1190, and a light emitting element 1140.

For example, the one of the plurality of subpixels further includes a buffer layer 1121 on the base substrate 1000, and the pixel driving circuit 1120 includes an active layer 1122 on the display area buffer layer 1121, a first display area gate insulation layer 1128 on the side of the active layer 1122 remote from the substrate 1000, a gate electrode 11211 on the first display area gate insulation layer 1128, a second display area gate insulation layer 1129 on the side of the gate electrode 11211 remote from the base substrate 1000, a display area interlayer insulation layer 11210 on the second display area gate insulation layer 1129, and a source electrode 1125 and a drain electrode 1126 located on the Display region interlayer insulation layer 11210. Gate electrode 11211 may be disposed on the same layer as the plurality of leads 1220 in bonding region 1200. Therefore, gate electrode 11211 and the plurality of leads 1220 may be formed on the same layer in the manufacturing process, for example, gate electrode 11211 and the plurality of leads 1220 may be formed by a patterning process using the same material layer. Display region buffer layer 1121 is disposed on the same layer as bonding region buffer layer 1241, and the display region buffer layer 1121 and the bond region buffer layer 1241 may be formed on the same layer in the manufacturing process. The first display region gate insulating layer 1128 located in the display region is provided on the same layer as the first bond region gate insulating layer 1242 located in the bond region. The second display region gate insulating layer 1129 located in the display region is provided on the same layer as the second bond region gate insulating layer 1243 located in the bond region. And the display region interlayer insulating layer 11211 located in the display region is provided on the same layer as the bond region interlayer insulating layer 1244 located in the bond region. The display area buffer layer 1121 serves as a transition layer, which can not only prevent harmful substances in the base substrate from penetrating into the interior of the display substrate, but also increase the adhesion of the film layer in the display substrate to the base substrate 1000.

For example, the material of the display region buffer layer 1121 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The materials of the display region interlayer insulating layer 11210, the second display region gate insulating layer 1129, and the first display region gate insulating layer 1128, or the materials of more than one display region interlayer insulating layer 11210, the second display region gate insulating layer 1129, and the first display region gate insulating layer 1128 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The materials of the display region interlayer insulating layer 11210, the second display region gate insulating layer 1129, and the first display region gate insulating layer 1128 may be the same or different.

For example, in some examples of the above embodiments of the present disclosure, as in 4 , the active layer 1122 may include a source region 1123 and a drain region 1124, and a channel region located between the source region 1123 and the drain region 1124. The display region interlayer insulating layer 11210, the second display region gate insulating layer 1129, and the first display region gate insulating layer 1128 include via holes to expose the source region 1123 and the drain region 1124. The source electrode 1125 and the drain electrode 1126 are electrically connected to the source region 1123 and the drain region 1124 through the via holes, respectively. In a direction perpendicular to the base substrate 1000, the gate electrode 11211 overlaps with the channel region located between the source region 1123 and the drain region 1124 in the active layer 1122. The first planarization layer 1130 is located above the source electrode 1125 and the drain electrode 1126 and is configured to planarize the surface of the side of the pixel driver circuit remote from the base substrate. A first through hole 1131 is formed in the first planarization layer 1130 to expose the source electrode 1125 or the drain electrode 1126 (the case as in 4 shown). A passivation layer 11110 is formed between the pixel driving circuit 1120 and the first planarization layer 1130 and includes a passivation layer via hole 11111. The passivation layer can protect the source electrode and the drain electrode of the pixel driving circuit from corrosion by water vapor. The first transfer electrode 1180 is formed on the first planarization layer 1130. The first transfer electrode 1180 is electrically connected to the drain electrode 1126 through the first via hole 1131 and the passivation layer via hole 11111. The first transfer electrode can avoid the direct formation of via holes with relatively large openings in the first planarization layer and the second planarization layer, thereby improving the quality of electrical connection of the via holes. In addition, the first transfer electrode can also be formed in the same layer as other signal lines (e.g., power lines, etc.), thereby not increasing the number of manufacturing steps. The first transfer electrode 1180 and the second contact pad metal layer 1217 of the plurality of contact pads 1210 are provided on the same layer, so that the first transfer electrode 1180 and the second contact pad metal layer 1217 can be formed on the same layer in the manufacturing process, e.g., the first transfer electrode 1180 and the second contact pad metal layer 1217 can be formed by a patterning process using the same material layer, thereby simplifying the manufacturing process.

The material of the first transfer electrode 1180 may include, for example, a metal material or an alloy material, such as a single-layer metal structure or a multi-layer structure of molybdenum, aluminum, titanium, etc.

The material of the active layer 1122 may include, for example, polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate electrode 11211 may include a metal material or an alloy material, such as e.g., a single-layer metal structure or a multi-layer metal structure formed of molybdenum, aluminum, titanium, etc., wherein the multi-layer metal structure is a laminated layer of multiple metals (such as a three-layer laminated metal layer of titanium, aluminum, and titanium (Ti/Al/Ti). The material of the source electrode 1125 and the drain electrode 1126 may include a metal material or an alloy material, e.g., a single-layer metal structure or a multi-layer metal structure formed of molybdenum, aluminum, titanium, etc., e.g., the multi-layer metal structure is a laminated layer of multiple metals (such as a three-layer laminated metal layer of titanium, aluminum, and titanium (Ti/Al/Ti)). The embodiments of the present disclosure do not expressly limit the material of the individual functional layers.

For example, the material of the passivation layer may include an organic insulating material or an inorganic insulating material such as silicon nitride material, which can well protect the pixel driving circuit from corrosion by water vapor due to its high dielectric constant and good hydrophobic function.

In some examples of the present disclosure, such as in 4 , the pixel driver circuit 1120 may further include a first display area metal layer 1127 provided on the same layer as the first contact pad metal layer 1215. The first display area metal layer 1127 includes the source electrode 1125 and the drain electrode 1126 of the above-mentioned thin film transistor of the pixel driver circuit. The source electrode 1125 and the drain electrode 1126 are on the same layer as the first contact pad metal layer 1215. Therefore, the source electrode 1125 and the drain electrode 1126 as well as the first contact pad metal layer 1215 may be formed on the same layer in the manufacturing process, for example, by a patterning process using the same material layer, thereby simplifying the manufacturing process and reducing the manufacturing cost of the product.

For example, in some examples of the present disclosure, as in 4 shown, the second planarization layer 1190 is arranged on the side of the first transfer electrode 1180 remote from the base substrate 1000 to provide a planarization surface on the side of the first transfer electrode 1180 remote from the base substrate 1000. In addition, a second through hole 1191 is formed in the second planarization layer 1190. The second planarization layer 1190 is formed on the same layer as the first insulation layer 1230 in the bonding region 1200, so that the second planarization layer 1190 and the first insulation layer 1230 can be formed on the same layer in the manufacturing process, for example, the second planarization layer 1190 and the first insulation layer 1230 can be formed by a patterning process using the same material layer, thereby simplifying the manufacturing process.

For example, the light-emitting element 1140 is formed on the second planarization layer, that is, the light-emitting element 1140 is arranged on the side of the second planarization layer 1190 remote from the base substrate. The light-emitting element 1140 includes a first electrode 1141, a light-emitting layer 1142, and a second electrode 1143. The first electrode 1141 of the light-emitting element is electrically connected to the first transfer electrode 1180 through the second through-hole 1191 in the second planarization layer 1140. A pixel definition layer 1144 is formed on the first electrode 1141, and the pixel definition layer 1144 includes a plurality of openings to define a plurality of pixel units. Each of the plurality of openings exposes a corresponding first electrode 1141. Moreover, the light-emitting layer 1142 is disposed in the plurality of openings of the pixel definition layer 1144, and the second electrode 1143 is disposed on the pixel definition layer 1144 and the light-emitting layer 1142. For example, the second electrode 1143 may be disposed in a part or the entirety of the display region so that the second electrode 1143 is formed into an entire surface in the manufacturing process.

The material of the second planarization layer 1190 may include, for example, inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, etc., and may further include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, etc., and the embodiments of the present disclosure are not limited thereto.

For example, the first electrode 1141 may include a reflective layer, and the second electrode 1143 may include a transparent layer or a semi-transparent layer. Thus, the first electrode 1141 may reflect the light emitted from the light-emitting layer 1142, and the part of the light is emitted to the external environment through the second electrode 1143, so that a light emission rate can be provided. In the case where the second electrode 1143 includes a semi- transparent layer, a part of the light reflected by the first electrode 1141 is reflected again by the second electrode 1143, so that the first electrode 1141 and the second electrode 1143 form a resonance structure, thereby improving the light emission performance.

For example, the material of the first electrode 1141 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. Furthermore, the first electrode 1141 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

For OLED, for example, the light emitting layer 1142 may include a small molecular organic material or a polymeric molecular organic material, which may be a fluorescent light emitting material or a phosphorescent light emitting material and may emit red light, green light, blue light, or white light. In addition, the light emitting layer may include other functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, a hole transport layer, and the like. For QLED, the light-emitting layer can use quantum dot material, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, etc., and the particle size of quantum dots is 2-20nm.

For example, the second electrode 1143 may assume various conductive materials. For example, the second electrode 1143 may assume a metallic material such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc.

The material of the pixel definition layer 1144 may include, for example, organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, etc., or inorganic insulating materials such as silicon oxide, silicon nitride, etc., and the embodiments of the present disclosure are not limited thereto.

Furthermore, the display substrate includes a storage capacitor 1160, which may include a first capacitor electrode 1161 and a second capacitor electrode 1162. The first capacitor electrode 1161 is disposed between the first display region gate insulating layer 1128 and the second display region gate insulating layer 1129, and the second capacitor electrode 1162 is disposed between the second display region gate insulating layer 1129 and the display region interlayer insulating layer 11210. The first capacitor electrode 1161 and the second capacitor electrode 1162 are stacked and at least partially overlap each other in the direction perpendicular to the base substrate 1000. The first capacitor electrode 1161 and the second capacitor electrode 1162 incorporate the second display region gate insulating layer 1129 as a dielectric material to form the storage capacitor. The first storage capacitor electrode 1161 is located on the same layer as the gate electrode 11211 in the pixel driving circuit 1120 and the plurality of leads 1220 in the bonding region 1200. Similarly as described above, in the variation of the above example, the first capacitor electrode and the second capacitor electrode of the storage capacitor 1160 may also be arranged in other layers, thereby obtaining a plurality of subpixels with different structures.

In another example, as a variation of the 4 In the example shown, the first capacitor electrode of the storage capacitor is still provided on the same layer as the gate electrode 11211, while the second capacitor electrode of the storage capacitor is provided on the same layer as the source electrode 1125 and the drain electrode 1126 of the thin film transistor (i.e., also in the first display region metal layer 1127), whereby the first capacitor electrode and the second capacitor electrode use a stack of the second display region gate insulation layer 1129 and the display region interlayer insulation layer 11210 as dielectric materials to form the storage capacitor.

In another example, which is a variation of the 4 In the example shown, the first capacitor electrode of the storage capacitor is no longer provided on the same layer as the gate electrode 11211, but is located between the second display area gate insulation layer 1129 and the display area interlayer insulation layer 11210, while the second capacitor electrode of the storage capacitor is provided on the same layer as the source electrode 1125 and the drain electrode 1126 of the thin film transistor (ie, is also arranged in the first display area metal layer 1127), whereby the first capacitor electrode and the second capacitor electrode use the display area interlayer insulation layer 11210 as a dielectric Accept material to form the storage capacitor.

In some examples of the present disclosure, such as in 4 , the display substrate may further include an encapsulation layer 1150 disposed on the light-emitting element 1140. The encapsulation layer 1150 seals the light-emitting element 1140 so that deterioration of the light-emitting element 1140 due to moisture and/or oxygen in the environment may be reduced or avoided. The encapsulation layer 1150 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which inorganic layers and organic layers are stacked. For example, the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151, a first organic encapsulation layer 1152, and a second inorganic encapsulation layer 1153 disposed one behind the other. The encapsulation layer 1150 may extend to the bonding region, and in the above example, the encapsulation layer does not cover the plurality of contact pads.

The material of the encapsulation layer may include, for example, insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, polymer resin, etc. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high compactness and can prevent the ingress of water, oxygen, etc. The material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material configured to block water vapor, such as a polymer resin or the like, to planarize the surface of the display substrate and reduce the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer. The material of the organic encapsulation layer may further contain a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that intrude into the interior of the display substrate.

For example, in some examples of the present disclosure, 5A a schematic cross-sectional view along the line M1-N1 of the 2 B shown display substrate according to another embodiment of the present disclosure.

Compared to the 3A The structure of the bonding area shown in 5A shown structure of the bonding region, the second insulation layer 1250 is removed in the bonding region 1200 of the display substrate. The second contact pad metal layer 1217 directly covers the edges of the first contact pad metal layer 1215, whereby the thickness of the film layer of the plurality of contact pads 1210 can be reduced and the segment difference of the film layer can be further reduced, thereby further improving the poor contact phenomenon in the bonding region.

For example, in some examples of the present disclosure, 5B a schematic cross-sectional view of the display area of the display substrate as shown in 2 B according to another embodiment of the present disclosure.

Compared to the 4 The structure of the display substrate shown in 5B shown structure of the display substrate, the passivation layer 11110 in the plurality of subpixels (110) in the display area of the display substrate is removed.

For example, in some examples of the present disclosure, the display substrate further comprises a third bonding region insulating layer located in the bonding region and disposed on a side of the first insulating layer and the plurality of contact pads remote from the base substrate to cover the first insulating layer and the plurality of contact pads, and the third bonding region insulating layer comprises third contact pad vias to expose the surface of the plurality of contact pads.

For example, in some examples of the present disclosure, the display substrate further comprises an auxiliary conductive layer. The auxiliary conductive layer is located in the bonding region and is disposed on a side of the third bonding region insulation layer remote from the base substrate, the auxiliary conductive layer comprises a second transfer electrode pattern located in the bonding region, and the second transfer electrode pattern is electrically connected to the plurality of contact pads through the third contact pad vias.

6 For example, is a schematic plan view of a bonding region of another display substrate according to an embodiment of the present disclosure. 7A is a schematic cross-sectional view along the line M4-N4 of the 6 shown display substrate according to an embodiment of the present disclosure.

The display substrate includes, for example, a base substrate 2000. The base substrate 2000 includes a display region and a peripheral region surrounding the display region, and the peripheral region includes at least one bond area. Similarly, the display area includes a pixel array and scan lines (gate lines), data lines, power lines, sense lines, etc., which are configured to supply control signals, data signals, voltage signals, etc. to the pixel array.

As in 6 and 7A , the display substrate may further include a plurality of leads 2220 and at least one group of contact pads. At least one group of contact pads includes a plurality of contact pads 2210. The plurality of contact pads may be further divided into a first group of contact pads 2210 and a second group of contact pads 2210'. The second group of contact pads 2210' is located on a side of the first group of contact pads 2210 proximate the display region 1100. The display substrate further includes a bond region buffer layer 2241 on the base substrate 2000 and a first bond region gate insulation layer 2242 located on the side of the bond region buffer layer 2241 remote from the base substrate 2000. The plurality of leads 2220 are located on the first bonding area gate insulation layer 2242. The plurality of leads 2220 are electrically connected to the plurality of contact pads 2210 in one-to-one correspondence. One end of the plurality of leads 2220 extends to the display area and is electrically connected to signal lines (e.g., data lines) in the display area, and the other end of the plurality of leads 2210 extends to the bonding area 2200 and is electrically connected to the plurality of contact pads 2210. The plurality of contact pads 2210 are arranged in a single row or in multiple rows, e.g., in the manner shown in 6 For example, in the example shown, the plurality of contact pads are arranged in two rows called L3 row (first row) and L4 row (second row), and the L4 row is located between the L3 row and the display area. Intervals are arranged between the plurality of contact pads 2210 in the same row, and intervals are also arranged between the plurality of contact pads 2210 in different rows, and the intersection line M4-N4 passes through a contact pad 2211 in the L3 row and a contact pad 2212 in the L3 row.

Similarly, in other examples, the plurality of leads 2220 may also be arranged in different layers, for example, the leads configured to be connected to the contact pads 2210 of the L3 row are arranged in a layer closer to the base substrate, while the leads configured to be connected to the contact pads 2210 of the L4 row are arranged in a layer relatively farther from the base substrate (but still between the contact pads and the base substrate). Therefore, the distances between the plurality of leads 2220 in the same layer are increased, the risk of interference between the leads and short circuits is reduced, and the display device with high pixel resolution is advantageous to form. Moreover, the plurality of leads 2220 in the same layer can be manufactured in the same patterning process.

The display substrate may further comprise a first insulation layer 2230 and a third bonding region insulation layer 2260 arranged in the bonding region 2200. The first insulation layer 2230 covers at least a portion of the edges of the plurality of contact pads 2210. The plurality of contact pads 2210 comprises at least one contact pad metal layer, for example, multiple contact pad metal layers. In the 7A In the example shown, the at least one contact pad metal layer of the plurality of contact pads 2210 may include a first contact pad metal layer 2215 and a second contact pad metal layer 2217, and the second contact pad metal layer 2217 is laminated on a side of the first contact pad metal layer 2215 remote from the base substrate 2000. The third bonding area insulation layer 2260 covers the first insulation layer 2230 and the plurality of contact pads 2210 so that in the manufacturing process of the display substrate, the first insulation layer can protect the edges of the plurality of contact pads and prevent the etching solution from etching the exposed edges of the contact pads, thereby improving the product yield and the reliability of the display substrate.

As in 7A For example, as shown, the display substrate may further include a second bonding region gate insulating layer 2243 and a bonding region interlayer insulating layer 2244 in the bonding region. The bonding region interlayer insulating layer 2244 is located in the bonding region and is between the plurality of contact pads 2210 and the first insulating layer 2230 and the base substrate 2000. The second bonding region gate insulating layer 2243 is located between the first bonding region gate insulating layer 2242 and the bonding region interlayer insulating layer 2244 and is laminated to the bonding region interlayer insulating layer 2244. The second bonding area gate insulation layer 2243 includes first contact pad through holes 2216, the bonding area interlayer insulation layer 2244 includes second contact pad through holes 2219, and at least one of the plurality of leads 2220 is electrically connected to the contact pad through holes 2216 and the second contact pad through holes 2219. through holes. The leads 2220 connected to the contact pads 2210 of the L3 row extend through the gaps between the contact pads of the L4 row in the bonding area and then extend to the display area, so that the plurality of contact pads 2210 have larger arrangement spaces and can avoid mutual interference or short circuit with the plurality of leads 2220 connected to the contact pads 2210 of the L3 row.

As in 7A For example, as shown, the second contact pad metal layer 2217 is formed on the first contact pad metal layer 2215 and covers the edges of the first contact pad metal layer 2215 to prevent the first contact pad metal layer 2215 from being exposed and corroded by the etching solution in a subsequent patterning process. The first insulation layer 2230 covers at least part of the edges of the second contact pad metal layer 2217 of the plurality of contact pads 2210. The height of the surface of the first insulation layer 2230 relative to the surface of the base substrate 2000, that is, the vertical distance between the surface of the first insulation layer 2230 and the surface of the base substrate 2000, is not greater than the distance between the surface of the second contact pad metal layer 2217 of the plurality of contact pads 2210 and the surface of the base substrate 2000. Limiting the height of the first insulation layer 2230, that is, the thickness of the first insulation layer 2230, can improve the poor contact phenomenon in the bonding area and increase the product yield. In addition, the second contact pad metal layer 2217 directly covers the edges of the first contact pad metal layer 2215, whereby the thickness of the film layer of the plurality of contact pads 2210 can be reduced and the segment difference of the film layer can be further reduced, thereby further improving the poor contact phenomenon in the bonding area.

As in 7A For example, as shown, the display substrate may include an auxiliary conductive layer. The auxiliary conductive layer is located in the bonding region and display region, and is disposed on the third bonding region insulating layer 2260. The auxiliary conductive layer includes a second transfer electrode pattern 2270 located in the bonding region. The second transfer electrode pattern 2270 is for performing a bonding process with an external circuit. A third contact pad through-hole 2218 is formed in the third bonding region insulating layer 2260. The second transfer electrode pattern 2270 is electrically connected to the plurality of contact pads through the third contact pad through-holes 2218 to transmit electrical signals. The first insulating layer 2230 is configured to expose a surface of a plurality of contact pads 2210 facing away from the base substrate 2000. That is, a region not covered by the plurality of contact pads 2210 in the bonding region 2200 is covered by the first insulation layer 2230, and the region includes, but is not limited to, gaps between the plurality of contact pads of the same row and gaps between the plurality of contact pads of different rows.

For example, in some examples of the present disclosure, the height of the surface of the second transfer electrode pattern 2270 relative to the surface of the base substrate 2000 is not greater than the height of the surface of the third bonding region insulating layer 2260 relative to the surface of the base substrate 2000 in order to avoid a poor contact phenomenon of the bonding region.

For example, in some examples of the present disclosure, 7B a schematic cross-sectional view of the display area of the 6 according to an embodiment of the present disclosure. As shown in 7B As shown, each of the plurality of subpixels 210 in each pixel unit in the pixel array of the display area of the display substrate may include a pixel driver circuit 2120, a first planarization layer 2130, a first transfer electrode 2180, a second planarization layer 2190, and a light emitting element 2140.

For example, the one of the plurality of subpixels further includes a buffer layer 2121 on the base substrate 2000, and the pixel driving circuit 2120 includes an active layer 2122 on the display area buffer layer 2121, a first display area gate insulating layer 2128 on the side of the active layer 2122 remote from the substrate 2000, a gate electrode 21211 on the first display area gate insulating layer 2128, a second display area gate insulating layer 2129 on the side of the gate electrode 21211 remote from the base substrate 2000, the display area interlayer insulating layer 21210 on the second display area gate insulating layer 2129t, and the source electrode 2125 and the drain electrode 2126 located on the Display region interlayer insulation layer 21210. Gate electrode 21211 may be disposed on the same layer as the plurality of leads 2220 in bonding region 2200. Buffer layer 2121 in display region is disposed on the same layer as bonding region buffer layer 2241 in bonding region. Display region buffer layer 2121 and bonding region buffer layer 2241 may be formed on the same layer in the manufacturing process. First display region gate insulation layer 2128 in Display region is provided on the same layer as the first bonding region gate insulating layer 2242 in the bonding region, the second display region gate insulating layer 2129 in the display region is provided on the same layer as the second bonding region gate insulating layer 2243, and the display region interlayer insulating layer 21210 in the display region is provided on the same layer as the bonding region interlayer insulating layer 2244. The display region buffer layer 2121 serves as a transition layer, which can not only prevent harmful substances in the base substrate from penetrating into the interior of the display substrate, but also increase the adhesion of the film layer in the display substrate to the base substrate 2000.

In some examples of the present disclosure, such as in 7B For example, as shown, the active layer 2122 includes a source region 2123 and a drain region 2124, and a channel region located between the source region 2123 and the drain region 2124. The display region interlayer insulating layer 21210, the second display region gate insulating layer 2129, and the first display region gate insulating layer 2128 have through holes to expose the source region 2123 and the drain region 2124. The source electrode 2125 and the drain electrode 2126 are electrically connected to the source region 2123 and the drain region 2124 through the through holes, respectively. The gate electrode 21211 overlaps with the channel region located between the source region 2123 and the drain region 2124 in the active layer 2122 in the direction perpendicular to the base substrate 2000. The first planarization layer 2130 is located above the source electrode 2125 and the drain electrode 2126, and a first through hole 2131 is formed in the first planarization layer 2130 to expose the source electrode 2125 or the drain electrode 2126 (the through hole shown in 7B The first transfer electrode 2180 is formed on the first planarization layer 2130. The first transfer electrode 2180 is electrically connected to the drain electrode 2126 through the first via hole 2131. The first transfer electrode can avoid the direct formation of via holes with relatively large openings in the first planarization layer and the second planarization layer, thereby improving the quality of electrical connection of the via holes. In addition, the first transfer electrode can also be formed in the same layer as other signal lines (e.g., power lines, etc.), thereby not increasing the number of manufacturing steps. The first transfer electrode 2180 and the second contact pad metal layer 2217 are on the same layer.

In some examples of the present disclosure, such as in 7B , the pixel driver circuit 2120 may further include a first display area metal layer 2127 provided on the same layer as the first contact pad metal layer 2215. The first display area metal layer 2127 includes the source electrode 2125 and the drain electrode 2126 of the above-mentioned thin film transistor in the pixel driver circuit. The source electrode 2125 and the drain electrode 2126 are on the same layer as the first contact pad metal layer 2215. Therefore, the source electrode 2125 and the drain electrode 2126 as well as the first contact pad metal layer 2215 may be formed on the same layer in the manufacturing process, for example, by a patterning process using the same material layer, thereby simplifying the manufacturing process and reducing the manufacturing cost of the product.

For example, in some examples of the present disclosure, as in 7B As shown, the second planarization layer 2190 is disposed on the side of the first transfer electrode 2180 remote from the base substrate 2000 to provide a planarization surface on the side of the first transfer electrode 2180 remote from the substrate 2000. In addition, a second through hole 2191 is formed in the second planarization layer 2190. The second planarization layer 2190 is formed on the same layer as the first insulation layer 2230 in the bonding region 2200. The light-emitting element 2140 is formed on the second planarization layer 2190, that is, the light-emitting element 2140 is disposed on the side of the second planarization layer 2190 remote from the base substrate. The light-emitting element 2140 includes a first electrode 2141, a light-emitting layer 2142, and a second electrode 2143. A pixel definition layer 2144 is formed on the first electrode 2141, and the pixel definition layer 2144 includes a plurality of openings to define a plurality of pixel units. Each of the plurality of openings exposes a corresponding first electrode 2141, and the light-emitting layer 2142 is disposed in the plurality of openings of the pixel definition layer 2144. For example, the second electrode 2143 may be disposed in part or all of the display area so that the second electrode 2143 is formed into an entire surface in the manufacturing process. The first electrode 2141 of the light-emitting element is electrically connected to the first transfer electrode 2180 through the second through-hole 2191 in the second planarization layer 2140.

For example, the display substrate further includes a storage capacitor 2160, which may include a first capacitor electrode 2161 and a second capacitor electrode 2162. The first capacitor electrode 2161 is disposed between the first display region gate insulating layer 2128 and the second display region gate insulating layer 2129, and the second capacitor electrode 2162 is disposed between the second display region gate insulating layer 2129 and the display region interlayer insulating layer 21210. The first capacitor electrode 2161 and the second capacitor electrode 2162 are stacked and at least partially overlap each other in the direction perpendicular to the base substrate 2000. The first capacitor electrode 2161 and the second capacitor electrode 2162 use the second display region gate insulating layer 2129 as a dielectric material to form the storage capacitor. The first storage capacitor electrode 2161 is located on the same layer as the gate electrode 21211 in the pixel driving circuit 2120 and the plurality of leads 2220 in the bonding region 2200. Similarly as described above, in the variation of the above example, the first capacitor electrode and the second capacitor electrode of the storage capacitor 2160 may also be arranged in other layers, thereby obtaining a plurality of subpixels with different structures.

In some examples of the present disclosure, such as in 7B , the display substrate may further include an encapsulation layer 2150 disposed on the light-emitting element 2140. The encapsulation layer 2150 seals the light-emitting element 2140 so that deterioration of the light-emitting element 2140 due to moisture and/or oxygen in the environment may be reduced or avoided. The encapsulation layer 2150 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which inorganic layers and organic layers are stacked. For example, the encapsulation layer 2150 may include a first inorganic encapsulation layer 2151, a first organic encapsulation layer 2152, and a second inorganic encapsulation layer 2153 disposed one behind the other. The encapsulation layer 2150 may extend to the bonding region, and in the above example, the encapsulation layer does not cover the plurality of contact pads.

In some examples of the present disclosure, such as in 7B , the display substrate further includes a third display area insulation layer 21120 located in the display area. The third display area insulation layer 21120 is disposed on the encapsulation layer 2150 to cover the encapsulation layer 2150. The third display area insulation layer 21120 is disposed on the same layer as the third bonding area insulation layer 2160. The display substrate may further include an auxiliary electrode layer 21130 located in the display area. The auxiliary electrode layer 21130 is disposed on the third display area insulation layer 21120, and the auxiliary electrode layer 21130 may be used for other auxiliary functions, such as a touch function. The auxiliary electrode layer 21130 has an opening in a region of one of the plurality of subpixels. The material of the third display area insulating layer 21120 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, etc., or inorganic insulating materials such as silicon oxide, silicon nitride, etc., and the embodiments of the present disclosure are not limited thereto.

For example, the auxiliary electrode layer for realizing the touch function can be used to realize a capacitive touch structure that is of a self-capacitive type or a mutual capacitance type. The self-capacitive type touch structure includes a plurality of self-capacitor electrodes arranged in an array (on the same layer), and each of the plurality of self-capacitor electrodes is electrically connected to a touch processing circuit (such as a touch chip) via a touch line. Position detection is performed by detecting a capacitance change of the self-capacitor electrodes caused by, for example, the proximity of the finger during touch. The mutual capacitance type touch structure includes a plurality of first touch signal lines extending in a first direction and a plurality of second touch signal lines extending in a second direction, and the plurality of first touch signal lines and the plurality of second touch signal lines are electrically connected to a touch processing circuit (such as a touch chip) via touch leads. The first direction and the second direction intersect and form an opening, whereby a touch capacitor is formed at one of the crossing positions of the plurality of first touch signal lines and the plurality of second touch signal lines, and position detection is realized by detecting a capacitance change in the touch capacitor due to, for example, the proximity of the finger during touch. The embodiments of the present disclosure are illustrated by taking the mutual capacitance type contact structure as an example.

As shown in the figure, the mutual capacitance type touch structure includes excitation electrodes and induction electrodes that cross each other and are arranged in the same layer to realize the touch function of the display substrate. For example, the induction electrode includes a plurality of segments, and the excitation electrode is continuous. At the location where the excitation electrode and the induction electrode cross, bridge electrodes are provided that are in different layers with the induction electrode and the excitation electrode to electrically connect two adjacent segments of the induction electrode. The touch sensitivity of the display substrate can be improved by the arrangement of the induction electrode and the excitation electrode.

For example, the material for forming the auxiliary electrode layer 21130 may contain indium tin oxide (ITO), thereby obtaining a transparent electrode, or the material for forming the auxiliary electrode layer 21130 may contain a metal mesh, thereby also obtaining a transparent electrode.

It should be noted that the structure in the display area of the display substrate, as shown in 7B shown to be different from the structure in the display area of the display substrate as shown in 4 shown, differs in that the display substrate in 7B with a third display area insulation layer 21120 and an auxiliary electrode layer 21130 on the encapsulation layer without providing a passivation layer. Based on this, the structure of the same film layers of the display substrates in 7B and the in 4 and the materials used to produce the film layers are not described in detail.

In some examples of the present disclosure, 8A for example, a schematic cross-sectional view along the line M4-N4 of the 6 shown display substrate provided by another embodiment of the present disclosure.

Compared to the 7A shown structure in the bonding area adds the 8A shown structure in the bonding area adds a second insulation layer 2250 in the bonding area 2200 of the display substrate. The second insulation layer 2250 is located between the first contact pad metal layer 2215 and the second contact pad metal layer 2217. The second insulation layer 2250 covers the edges of the first contact pad metal layer 2215 to prevent the edges of the first contact pad metal layer 2215 from being attacked by the etching solution in the subsequent patterning process. In addition, the first insulation layer 2230 covers the edges of the second contact pad metal layer 2217 to prevent the edges of the second contact pad metal layer 2217 from being attacked by the etching solution in the subsequent patterning process. For example, at the gap between the contact pad 2211 and the contact pad 2212, the second insulation layer 2250 is located between the first insulation layer 2230 and the bonding region interlayer insulation layer 2244. The second insulation layer 2250 includes first contact pad vias 2251, and the second contact pad metal layer 2217 is electrically connected to the first contact pad metal layer 2215 through the first contact pad vias 2251.

In at least one example, as in 8A As shown, the second contact pad metal layer 2217 extends further outward on the second insulation layer 2250 compared to the edges of the first contact pad metal layer 2215 to cover the edges of the first contact pad metal layer 2215, that is, on the surface of the base substrate 2000, the orthographic projection of the second contact pad metal layer 2217 covers the orthographic projection of the first contact pad metal layer 2215. The structure described above can reduce the segment difference at the edges of the plurality of contact pads and is advantageous for the first insulation layer 2230 to cover the edges of the second contact pad metal layer 2217.

For example, in some examples of the present disclosure, 8B a schematic cross-sectional view of the display area of the 6 shown display substrate according to another embodiment of the present disclosure.

Compared with the structure of the display substrate as shown in 7B shown, the structure of the display substrate as shown in 8B , a passivation layer 21110 is added in the plurality of subpixels 210 in the display area of the display substrate. The passivation layer 21110 is located between the pixel driver circuit and the first planarization layer 2130 and includes a passivation layer via hole 21111. The passivation layer may protect the source electrode and the drain electrode of the pixel driver circuit from corrosion by water vapor. The pixel driver circuit and the first transfer electrode 2180 may also be electrically connected through the passivation layer via hole 21111. The second insulation layer 2250 is located on the same layer as the passivation layer 21110.

At least one embodiment of the present disclosure further provides a display device that may include the display substrate of any of the above embodiments.

For example, in some examples, the display device may further include a flexible circuit board and a control chip. For example, the flexible circuit board is bonded to the bonding region of the display substrate, and the control chip is installed on the flexible circuit board, thereby establishing an electrical connection with the display region. Alternatively, the control chip is directly bonded to the bonding region, thereby electrically connecting it to the display region.

The control chip may be, for example, a central processing unit, a digital signal processor, a system chip (SoC), etc. For example, the control chip may also include a memory, a power supply module, etc., and the power supply function and the signal input and output function are realized by additionally arranged wires, signal lines, etc. For example, the control chip may also include a hardware circuit, a computer executable code, etc. The hardware circuit may include conventional VLSI (Very Large Scale Integration) circuitry or gate arrays and existing semiconductors such as logic chips, transistors, or other discrete components. The hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

For example, the display device provided by at least one embodiment of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook, a digital photo frame, a navigation device, etc.

There is further described herein a manufacturing method for a display substrate, comprising: providing a base substrate, the base substrate comprising a display region and a bonding region located on at least one side of the display region; forming a plurality of subpixels in the display region; forming a plurality of data lines in the display region, the plurality of data lines configured to provide data signals to the plurality of subpixels; forming a plurality of data leads in the bonding region, the plurality of data leads electrically connected to the plurality of data lines; Forming at least one group of contact pads in the bonding region, the at least one group of contact pads comprising a plurality of contact pads, at least one of the plurality of contact pads comprising a first contact pad metal layer and a second contact pad metal layer, the first contact pad metal layer configured to be located on a side of the plurality of data leads remote from the base substrate and electrically connected to one of the plurality of data leads, the second contact pad metal layer configured to be located on a side of the first contact pad metal layer remote from the base substrate and electrically connected to the first contact pad metal layer, and the second contact pad metal layer covering an edge of the first contact pad metal layer; and forming a first insulation layer in the bonding region, the first insulation layer disposed in gaps between the plurality of contact pads and covering edges of the plurality of contact pads and configured to expose surfaces of the plurality of contact pads remote from the base substrate.

In the display substrate obtained by the manufacturing method, the first insulating layer located in the bonding region of the display substrate is configured to expose the surfaces of the plurality of contact pads facing away from the base substrate and cover the edges of the plurality of contact pads, so that in the manufacturing process of the display substrate, the first insulating layer can protect the edges of the metal layers of the plurality of contact pads, and prevent the etching solution in the subsequent patterning process from etching the edges of the exposed surfaces of the plurality of contact pads, and further improve the product yield and reliability of the display substrate.

In some examples of the present disclosure, forming the first insulation layer includes, for example: causing the height of the surface of the first insulation layer relative to the surface of the base substrate to be no greater than the height of the surface of the plurality of contact pads relative to the surface of the base substrate.

In various embodiments, the first insulating layer in the bonding region may be formed on the same layer as various insulating layers in the display region, thereby obtaining various laminated structures in the bonding region.

In some examples of the present disclosure, forming the plurality of subpixels in the display area includes, for example: forming the plurality of subpixels in the display area, wherein at least one of the plurality of subpixels comprises a pixel driver circuit, a first planarization layer, and a light emitting element. Forming the plurality of subpixels in the display region includes: forming the pixel driving circuit on the base substrate, forming the first planarization layer on the side of the pixel driving circuit remote from the base substrate to provide the first planarization surface, and forming the first through-hole in the first planarization layer, forming the first transfer electrode on the first planarization surface, the first transfer electrode being electrically connected to the pixel driving circuit through the first through-hole, forming the second planarization layer on the side of the first transfer electrode remote from the base substrate to provide the second planarization surface, and forming the second through-hole in the second planarization layer, the first insulating layer and the second planarization layer being formed by the same first insulating material layer; and forming the light-emitting element on the second planarization surface, the light-emitting element being electrically connected to the first transfer electrode through the second through-hole.

For example, in some examples of the present disclosure, forming the first insulating layer and the second planarization layer by the same first insulating material layer includes: depositing the first insulating material layer on the base substrate after the plurality of contact pads and the pixel driver circuit are formed; performing a patterning process on the first insulating material layer such that a portion of the first insulating material layer located in the display region is formed as the second planarization layer and the second via is formed in the second planarization layer, removing a portion of the first insulating material layer overlapping the plurality of contact pads, and thinning a portion of the first insulating material layer located in the bonding region and at edges of the plurality of contact pads to form the first insulating layer.

In some examples of the present disclosure, performing a patterning process on the first insulating material layer includes, for example: patterning the first insulating material layer using a gray tone mask plate patterning process or a halftone mask plate patterning process.

Next, the manufacturing process of the display substrate will be described with reference to 9A until 9M described in detail, wherein the manufacture of the display substrate as in 5B shown as an example.

For example, the base substrate 1000 is provided. The base substrate 1000 includes the display region and the peripheral region surrounding the display region, and the peripheral region includes at least one bonding region located on at least one side of the display region. For example, the display region buffer layer 1121 is formed in the display region of the base substrate 1000 by a deposition process, while the bonding region buffer layer 1241 is formed in the bonding region.

For example, the material of the base substrate 1000 may include an organic material. For example, the organic material may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate, etc. The base substrate 1000 may be a flexible substrate or a non-flexible substrate, and the embodiments of the present disclosure are not limited thereto.

The materials of the display region buffer layer 1121 and the bond region buffer layer 1241 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

For example, an active layer is formed on the display region buffer layer 1121. For example, a semiconductor material layer is deposited on the base substrate 1000, and then a patterning process is performed on the semiconductor material layer to form the active layer 1122. The active layer 1122 includes the source region 1123 and the drain region 1124.

The semiconductor material of the active layer 1122 may comprise, for example, polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide), etc.

For example, after the active layer 1122 is formed, the first display region gate insulating layer 1128 may be formed on the active layer 1212 by a deposition process or the like, and the first bonding region gate insulating layer 1242 may be formed on the bonding region buffer layer 1241 in the bonding region. The materials of the first Display region gate insulating layer 1128 and first bond region gate insulating layer 1242 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

As in 9A For example, as shown, after the first display region gate insulating layer 1128 is formed, the gate electrode 11211 and the first capacitor electrode 1161 may be formed on the first display region gate insulating layer 1128 in the display region by a patterning process, and a plurality of leads 1220 may be formed on the base substrate 1000 in the bonding region. For example, a first metal material layer 1410 is deposited on the base substrate 1000, and then a patterning process is performed on the first metal material layer 1410 to form the gate electrode 11211, the first capacitor electrode 1161, and the plurality of leads 1220. The first metal material layer 1410 may be made of a metal material or an alloy material, such as a silicon carbide material. B. a single-layer metal structure or a multi-layer structure formed of molybdenum, aluminum, titanium, etc., wherein the multi-layer structure is a laminated layer of multiple metals (such as a three-layer laminated metal layer of titanium, aluminum and titanium (Ti/Al/Ti)).

In this step, in some examples, the gate electrode may be used as a mask, and the source region 1123 and the drain region 1124, which are conductive, are formed by doping the active layer, while the channel region between the source region 1123 and the drain region 1124 is undoped due to the shielding effect of the gate electrode.

As in 9B For example, as shown, after the gate electrode 11211, the first capacitor electrode 1161, and the plurality of leads 1220 are formed, an insulating material may be deposited on the base substrate by a deposition process or the like, the second display region gate insulating layer 1129 may be formed on the gate electrode 11211, and the second bond region gate insulating layer 1243 may be formed on the plurality of leads 1220 by a patterning process in the bond region. The second bond region gate insulating layer 1243 includes first contact pad vias 1216. The material of the second bond region gate insulating layer may include, for example, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

For example, the second capacitor electrode 1162 is formed on the second display region gate insulating layer 1129, a metal material layer is deposited on the base substrate, and the second capacitor electrode 1162 is formed on a part overlapping with the first capacitor electrode 1161 by a patterning process. The first capacitor electrode 1161 and the second capacitor electrode 1162 are implemented as the storage capacitor 1160.

For example, after the second capacitor electrode 1162 is formed, the display region interlayer insulating layer 11210 may be formed in the display region by a deposition process or the like, and the bond region interlayer insulating layer 1244 may be formed in the bond region. The bond region interlayer insulating layer 1244 includes second contact pad vias 1219. The material of the bond region interlayer insulating layer 1244 may include, for example, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

As in 9C For example, as shown, through holes are formed in the first display region gate insulating layer 1128, the second display region gate insulating layer 1129, and the display region interlayer insulating layer 11210 to expose the source region 1123 and the drain region 1124 of the active layer 1122. The second metal material layer 1150 is formed on the base substrate by a deposition method or the like. The second metal material layer 1150 may be made of a metal material or an alloy material, e.g., a single-layer metal structure or a multi-layer metal structure of molybdenum, aluminum, titanium, etc., wherein the multi-layer metal structure is a laminated layer of multiple metals (e.g., a three-layer laminated metal layer of titanium, aluminum, and titanium (Ti/Al/Ti)).

For example, the source electrode 1125 and the drain electrode 1126 are formed in the display region by a patterning process, and the first contact pad metal layer 1215 is formed in the bonding region. The source electrode 1125 and the drain electrode 1126 are electrically connected to the source region 1123 and the drain region 1124 through the via holes in the first display region gate insulating layer 1128, the second display region gate insulating layer 1129, and the display region interlayer insulating layer 11210, respectively. The first contact pad metal layer 1215 is electrically connected to the source region 1123 and the drain region 1124 through the first contact pad via holes 1216 in the second bonding region gate insulating layer 1243 and the second contact pad via holes 1219 in the bonding area interlayer insulation layer electrically connected to the plurality of leads 1220. As in 9D For example, as shown, a first insulating material layer 1710 is deposited on the base substrate to cover the source electrode 1125 and the drain electrode 1126 and cover the display region interlayer insulating layer 11210. On the first insulating material layer 1710, a photolithographic process is performed to form the first planarization layer 1130 in the display region to provide the planarization surface, and the first planarization layer 1130 includes the first via hole 1131. The first insulating material layer 1710 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., or organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, etc.

For example, after the pixel driver circuit 1120, the storage capacitor 1160, the first planarization layer 1130 located in the display region, as well as the plurality of leads 1220, the bonding region interlayer insulation layer 1244, and the first contact pad metal layer 1215 located in the bonding region are formed on the display substrate, a third metal material layer 1510 is deposited on the base substrate. The third metal material layer 1510 may be a metal material or an alloy material, such as a single-layer metal structure or a multi-layer metal structure made of molybdenum, aluminum, titanium, etc.

As in 9E For example, as shown, a patterning process is performed on the third metal material layer 1510 to form the first transfer electrode 1180 in the display region and the second contact pad metal layer 1217 in the bonding region. The second contact pad metal layer 1217 covers the edges of the first contact pad metal layer 1215 to prevent the first contact pad metal layer 1215 from being corroded. In the present embodiment, the first contact pad metal layer 1215 and the second contact pad metal layer 1217 are laminated to realize the plurality of contact pads 1210.

As in 9F For example, as shown, the first insulating material layer 1710 is deposited on the base substrate and a photoresist 1720 is deposited on the first insulating material layer 1710. The first insulating material layer 1710 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

As in 9G For example, as shown, a first mask plate 1610 is provided to expose the photoresist 1720. The first mask plate 1610 includes a fully transparent region, a partially transparent region, and a non-transparent region. In the bonding region, the first mask plate 1610 includes a first translucent pattern 1611 overlapping the gaps between the plurality of contact pads 1210 and a second translucent pattern 1612 overlapping the plurality of contact pads 1210. In the display region, the first mask plate 1610 includes the second translucent pattern 1612 and a non-translucent pattern 1613. The first translucent pattern 1611 is located in the partially transparent region, the second translucent pattern 1612 is located in the fully transparent region, and the non-translucent pattern 1613 is located in the non-transparent region. That is, the first mask plate 1610 is a gray mask or a halftone mask. The photoresist is a positive photoresist, and accordingly, the light transmittance of the first translucent pattern 1611 is smaller than that of the second translucent pattern 1612. In the exposure process, a part of the photoresist 1720 corresponding to the first translucent pattern 1611 may be partially exposed, while a part of the photoresist 1720 corresponding to the second translucent pattern 1612 may be fully exposed. A portion of the photoresist 1720 corresponding to the non-transparent pattern 1613 in the display area is not exposed.

In another example, a negative photoresist may also be used in the patterning process described above, and in this case the mask plate used is, for example, a mask plate complementary to the first mask plate 1610, so that the photoresist pattern 1721 and the photoresist pattern 1722 are obtained after an exposure process and a development process.

As in 9H For example, as shown, the photoresist 1720 is developed, and the fully exposed portion of the photoresist 1720 is removed, that is, in the bonding area, the photoresist 1720 overlapping with the plurality of contact pads 1210 is removed. The partially exposed portion of the photoresist 1720 is thinned, and the thickness of the unexposed portion of the photoresist 1720 remains substantially unchanged, for example. After the development process, the photoresist 1720 in the bonding area is formed into the photoresist pattern 1721. Similarly, in the display area, a portion of the photoresist 1720 overlapping with the drain electrode 1126 is removed. After the development process, the photoresist 1720 in the display area is formed into the photoresist pattern 1722.

For example, as in 91 As shown, the first insulating material layer 1710 in the bonding region and the display region is etched to remove the insulating material layer overlapping with the plurality of contact pads in the bonding region, and the second via hole 1191 is formed in the display region.

For example, as in 9J As shown, an ashing process is then performed to remove the photoresist pattern 1721 in the bonding region and thin the photoresist pattern 1722 in the display region, while maintaining the photoresist pattern 1722 in the display region. Then, using the current photoresist pattern, the remaining first insulating material layer 1710 in the bonding region is etched, and the etching thickness is controlled to form the first insulating layer 1230 such that the height of the surface of the etched first insulating layer 1230 relative to the surface of the base substrate 1000 is not greater than the height of the surface of the second contact pad metal layer 1217 of the plurality of contact pads 1210 relative to the surface of the base substrate 1000.

For example, as in 9K shown, the photoresist pattern 1722 in the display region is removed. The second planarization layer 1190 is formed in the display region to provide a planarization surface.

As in 9L For example, as shown, the first electrode 1141 of the light-emitting element 1140 is formed on the second planarization layer 1190 in the display region. The pixel definition layer 1144 is formed on the second planarization layer 1190 and the first electrode 1141, and the pixel definition layer 1144 includes a plurality of openings to define a plurality of pixel units. Each of the plurality of openings exposes a corresponding first electrode 1141. The light-emitting layer 1142 is thereafter formed in the plurality of openings of the pixel definition layer 1144, for example, by a distillation process, and then the second electrode 1143 is formed on the pixel definition layer 1144 and the light-emitting layer 1142. For example, the second electrode 1143 may be formed in part or in all of the display region so that the second electrode 1143 is formed on an entire surface in the manufacturing process. The first electrode 1141 of the light-emitting element 1140 is electrically connected to the first transfer electrode 1180 through the second through hole 1191.

For example, the material of the first electrode 1141 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. Furthermore, the first electrode 1141 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

For OLED, the light-emitting layer 1142 may include, for example, a small molecular organic material or a polymeric molecular organic material, which may be a fluorescent light-emitting material or a phosphorescent light-emitting material and may emit red light, green light, blue light, or white light. In addition, the light-emitting layer may include other functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, a hole transport layer, and the like as needed. For QLED, the light-emitting layer may use a quantum dot material, e.g. Such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, etc., and the particle size of quantum dots is 2-20nm.

For example, the second electrode 1143 may be made of various conductive materials. For example, the second electrode 1143 may assume a metallic material such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc.

For example, the material of the pixel definition layer 1144 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, etc., or inorganic insulating materials such as silicon oxide, silicon nitride, etc., and the embodiments of the present disclosure are not limited thereto.

As in 9M For example, as shown, the encapsulation layer 1150 is formed on the light-emitting element 1140 in the display region. The encapsulation layer 1150 seals the light-emitting element 1140 so that deterioration of the light-emitting element 1140 due to moisture and/or oxygen in the environment can be reduced or avoided.

The encapsulation layer 1150 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which inorganic layers and organic layers are stacked. For example, the encapsulation layer 1150 may include the first inorganic encapsulation layer 1151, the first organic encapsulation layer 1152 and the second inorganic encapsulation layer 1153 arranged one behind the other. The encapsulation layer 1150 may extend to the bonding region and in the above example, the encapsulation layer does not cover the plurality of contact pads.

The material of the encapsulation layer may include, for example, insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, polymer resin, etc. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high compactness and can prevent the ingress of water, oxygen, etc. The material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material configured to block water vapor, such as a polymer resin or the like, to planarize the surface of the display substrate and reduce the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer. The material of the organic encapsulation layer may further contain a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that intrude into the interior of the display substrate.

In another example of the present disclosure, the 5B manufacturing processes of the display substrate shown 9F until 9K and the 9F until 9K The processes shown can refer to the relevant descriptions of the examples above.

For example, in this example, the first insulating material layer 1710 may include a photosensitive resin material such as a photoresist. The photosensitive resin material is, for example, a positive photoresist. After the photosensitive resin material is applied to form a first material layer, exposure is performed, for example, using the above-mentioned first mask plate 1610. The first mask plate 1610 includes a fully transparent region, a partially transparent region, and a non-transparent region. In the bonding region, the first mask plate 1610 includes a first translucent pattern 1611 overlapping with the gaps between the plurality of contact pads 1210 and a second translucent pattern 1612 overlapping with the plurality of contact pads 1210. In the display region, the first mask plate 1610 includes the second light-transmitting pattern 1612 and a non-light-transmitting pattern 1613 overlapping with the drain electrode 1126. The first light-transmitting pattern 1611 is located in the partially transparent region, the second light-transmitting pattern 1612 is located in the fully transparent region, and the non-light-transmitting pattern 1613 is located in the non-transparent region.

In the exposure process, the part of the first insulating material layer 1710 corresponding to the second light-transmitting pattern 1612 is fully exposed, the part corresponding to the first light-transmitting pattern 1611 is partially exposed, and the part corresponding to the non-light-transmitting pattern 1613 in the display area is not exposed. After the development process, the first insulating material layer 1710 not exposed in the display area is formed into a second planarization layer 1190. The first insulating material layer 1710 partially exposed in the bonding region is formed into the first insulating layer 1230, and the height of the surface of the formed first insulating layer 1230 relative to the surface of the base substrate 1000 is not greater than the height of the surface of the second contact pad metal layer 1217 of the plurality of contact pads 1210 relative to the surface of the base substrate 1000. Accordingly, the first insulating material layer 1710 fully exposed in the display region and the bonding region is removed to form the second through hole 1191 in the display region and to expose the plurality of contact pads in the bonding region. With the above manufacturing method, the display substrate of the type shown in 9K getting produced.

In another example, the photosensitive resin material may also be a negative photoresist, and the mask plate used in this case is, for example, a mask plate complementary to the first mask plate 1160, so that the second planarization layer is also formed in the display region after an exposure process and a development process, and the plurality of contact pads and the first insulation layer covering the edges of the plurality of contact pads are exposed in the bonding region.

In the display substrate obtained by the manufacturing method described above, the first insulating layer located in the bonding region of the display substrate is configured to expose the surfaces of the plurality of contact pads facing away from the base substrate and to cover the edges of the plurality of contact pads, so that in the manufacturing process of the display substrate, the first insulating layer can protect the edges of the metal layers of the plurality of contact pads, and prevent the etching solution in the subsequent patterning process in which the transfer metal layer is formed from etching the exposed metal layers of the plurality of contact pads, and increase the product yield and Reliability of the display substrate further improved.

Another example: a manufacturing process is described that is similar to the 4 Compared to the display substrate shown in 5B shown structure in the bonding area adds the 4 shown structure in the bonding area, the second insulation layer 1250 is added in the bonding area 1200 of the display substrate. The second insulation layer 1250 is arranged between the first contact pad metal layer 1215 and the second contact pad metal layer 1217. And the second insulation layer 1250 covers the edges of the first contact pad metal layer 1215 to prevent the edges of the first contact pad metal layer 1215 from being attacked by the etching solution in the subsequent patterning process. Moreover, the second contact pads metal layer 1217 on the second insulation layer 1250 extends further outward than the edges of the first contact pads metal layer 1215 to cover the edges of the first contact pads metal layer 1215, that is, on the surface of the base substrate 1000, the orthographic projection of the second contact pads metal layer 1217 covers the orthographic projection of the first contact pads metal layer 1215. This structure can reduce the segment difference at the edges of the plurality of contact pads and is advantageous for the first insulation layer 1230 to cover the edges of the second contact pads metal layer 1217. Similarly, the passivation layer 11110 is arranged in the plurality of subpixels in the display area of the display substrate. The passivation layer 11110 is located between the pixel driver circuit 1120 and the first planarization layer 1130 and includes the passivation layer via hole 11111. The passivation layer can protect the source electrode and the drain electrode of the pixel driver circuit from corrosion by water vapor. The pixel driver circuit and the first transfer electrode 1180 are also electrically connected through the passivation layer via hole 11111. In the bonding region, the second insulation layer 1250 is located on the same layer as the passivation layer 11110.

In the present embodiment, the step of forming the passivation layer may be performed between the steps of 9C and 9D For example, based on the data in 9C shown structure, a passivation layer film is formed to cover the source electrode 1125 and the drain electrode 1126 and to cover the display region interlayer insulation layer 11210, and then the passivation layer film is patterned to form a through hole in the display region configured to expose the drain electrode 1126 and the passivation layer through hole 11111 in the passivation layer configured to expose the first contact pad metal layer 1215. Then, as in 9D As shown, the deposition of the first insulating material layer 1710 on the base substrate continues to cover the passivation layer.

For example, the material of the passivation layer may include an organic insulating material or an inorganic insulating material such as silicon nitride material, which can well protect the pixel driving circuit from water vapor corrosion due to its high dielectric constant and good hydrophobic function.

As a further example, a manufacturing process is provided which corresponds to the 7A and 7B Based on the results obtained in 9L According to the structure shown, it is possible to form the third display region insulating layer 21120 located in the display region on the base substrate. The third display region insulating layer 21120 is disposed on the light-emitting element 2140 to cover the light-emitting element 2140 and provides a planarization surface on the side of the light-emitting element 2140 remote from the base substrate 2000. Then, an auxiliary conductive layer is formed on the third display region insulating layer 21120, and the auxiliary conductive layer may include the auxiliary electrode layer 21130 located in the display region. The auxiliary electrode layer 21130 is disposed on the third display region insulating layer 21120. The auxiliary electrode layer 21130 may be configured to realize other auxiliary functions such as a touch function.

The material of the third display area insulating layer 21120 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin, etc., or inorganic insulating materials such as silicon oxide, silicon nitride, etc., and the embodiments of the present disclosure are not limited thereto. For example, the auxiliary electrode layer for realizing the touch function may be used to realize a capacitive touch structure that is of a self-capacitive type or a mutual capacitance type.

The flow of the manufacturing method of the display device may include more or fewer operations, and these operations may be performed sequentially or in parallel. Although the flow of the manufacturing method described above includes a plurality of operations in a specific order, it should be clear that the order of the plurality of operations is not limited. The manufacturing process described above can be carried out once or several times according to a predetermined condition.

With regard to the technical effect of the manufacturing method of the provided display device, reference can be made to the technical effect of the display device provided in the embodiments of the present disclosure, which will not be repeated here.

• (1) Die begleitenden Zeichnungen beziehen sich nur auf die Struktur(en) in Verbindung mit der (den) Ausführungsform(en) der vorliegenden Offenbarung, und andere Struktur(en) können auf die gemeinsame(n) Ausführung(en) bezogen werden.
• (2) Falls kein Konflikt besteht, können die Ausführungsformen der vorliegenden Offenbarung und die Merkmale in den Ausführungsformen miteinander kombiniert werden, um neue Ausführungsformen zu erhalten.

The following statements should be noted:

• (1) The accompanying drawings refer only to the structure(s) associated with the embodiment(s) of the present disclosure, and other structure(s) may be referred to the common embodiment(s).
• (2) If there is no conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

The above are merely specific implementations of the present disclosure, without limiting the scope of the present disclosure thereto. The scope of the present disclosure should be based on the scope of the appended claims.

Claims (20)

A display substrate (100) comprising: a base substrate (1000, 2000) comprising a display region (1100) and a bond region (1200, 2200) located on at least one side of the display region (1100); a plurality of subpixels (110, 210) located in the display region (1100); a plurality of data lines (1101) located in the display region (1100) and configured to provide data signals to the plurality of subpixels (110, 210); a plurality of data leads (1220, 2220) located in the bond region (1200, 2200) and electrically connected to the plurality of data lines (1101); at least one group of contact pads located in the bonding region (1200, 2200), the at least one group of contact pads comprising a plurality of contact pads (1210, 2210), at least one of the plurality of contact pads (1210, 2210) comprising a first contact pad metal layer (1215, 2215) and a second contact pad metal layer (1217, 2217), the first contact pad metal layer (1215, 2215) being located on a side of the plurality of data leads (1220, 2220) remote from the base substrate (1000, (1217, 2217) and being electrically connected to one of the plurality of data leads (1220, 2220), the second contact pad metal layer (1217, 2217) being located on a side remote from the base substrate (1000, 2000) remote side of the first contact pad metal layer (1215, 2215) and electrically connected to the first contact pad metal layer (1215, 2215), and wherein the second contact pad metal layer (1217, 2217) covers an edge of the first contact pad metal layer (1215, 2215); a first insulation layer (1230, 2230) located in the bonding region (1200, 2200), wherein the first insulation layer (1230, 2230) is located in gaps between the plurality of contact pads (1210, 2210) and covers edges of the plurality of contact pads (1210, 2210) and exposes the surfaces of the plurality of contact pads (1210, 2210) remote from the base substrate (1000, 2000); and a bonding region insulation layer (1243, 1244, 2243, 2244) located in the bonding region (1200, 2200), and wherein a portion of the bonding region insulation layer (1243, 1244, 2243, 2244) is located between the first contact pad metal layer (1215, 2215) and the plurality of data leads (1220, 2220), the bonding region insulation layer (1243, 1244, 2243, 2244) extending continuously from a position between the first contact pad metal layer (1215, 2215) and the plurality of data leads (1220, 2220) to a position between the first insulation layer (1230, 2230) and the base substrate (1000, 2000). Display substrate according to Protection claim 1 , wherein the bond area insulation layer (1243, 1244, 2243, 2244) comprises: a first insulation portion located between the first contact pad metal layer (1215, 2215) and the plurality of data leads (1220, 2220), wherein an orthographic projection of the first insulation portion on the base substrate (1000, 2000) is within an orthographic projection of the first contact pad metal layer (1215, 2215) on the base substrate (1000, 2000) and within an orthographic projection of the plurality of data leads (1220, 2220) on the base substrate (1000, 2000); and a fourth insulation part located between the first insulation layer (1230, 2230) and the base substrate (1000, 2000), wherein an orthographic projection of the fourth insulation part on the base substrate (1000, 2000) lies within an orthographic projection of the first insulation layer (1230, 2230) on the base substrate (1000, 2000) and does not coincide with an orthographic projection of the first insulation layer (1230, 2230) on the base substrate (1000, 2000). projection of the second contact pad metal layer (1217, 2217) on the base substrate (1000, 2000). Display substrate according to Protection claim 2 , wherein the bonding area insulation layer (1243, 1244, 2243, 2244) further comprises: a second insulation part located between the first contact pad metal layer (1215, 2215) and the base substrate (1000, 2000), wherein an orthographic projection of the second insulation part on the base substrate (1000, 2000) is within the orthographic projection of the first contact pad metal layer (1215, 2215) on the base substrate (1000, 2000) and does not overlap with the orthographic projection of the plurality of data lines (1220, 2220) on the base substrate (1000, 2000); and a third insulation part located between the second contact pad metal layer (1217, 2217) and the base substrate (1000, 2000), wherein an orthographic projection of the third insulation part on the base substrate (1000, 2000) lies within the orthographic projection of the second contact pad metal layer (1217, 2217) on the base substrate (1000, 2000) and does not overlap with the orthographic projection of the first contact pad metal layer (1215, 2215) on the base substrate (1000, 2000). Display substrate according to Protection claim 3 , further comprising: a first bonding area gate insulation layer (1242, 2242) located in the bonding area (1200, 2200), the first bonding area gate insulation layer (1242, 2242) located between the plurality of data leads (1220, 2220) and the base substrate (1000, 2000) and between the bonding area insulation layer (1243, 1244, 2243, 2244) and the base substrate (1000, 2000). Display substrate according to Protection claim 4 , wherein the first insulation part and a part of the first bonding area gate insulation layer (1242, 2242) are located on opposite sides of a part of the plurality of data leads (1220, 2220) in a direction perpendicular to the base substrate (1000, 2000), and wherein the fourth insulation part is embedded between the first insulation layer (1230, 2230) and the first bonding area gate insulation layer (1242, 2242). Display substrate according to Protection claim 4 , wherein the second insulation part is embedded between the first contact pad metal layer (1215, 2215) and the first bonding area gate insulation layer (1242, 2242); and wherein the third insulation part is embedded between the second contact pad metal layer (1217, 2217) and the first bonding area gate insulation layer (1242, 2242). Display substrate according to one of the Protection claims 1 until 6 , wherein the bonding region insulating layer (1243, 1244, 2243, 2244) comprises: a second bonding region gate insulating layer (1243, 2243) and a bonding region interlayer insulating layer (1244, 2244) located on a side of the second bonding region gate insulating layer (1243, 2243) remote from the base substrate (1000, 2000); and the bonding area insulation layer (1243, 1244, 2243, 2244) includes a contact pad via hole (1216, 2216, 1219, 2219), and one of the plurality of data leads (1220, 2220) is connected to the first contact pad metal layer (1215, 2215) via the contact pad via hole (1216, 2216, 1219, 2219). Display substrate (100) according to Protection claim 1 or 7 wherein a portion of the edges of the plurality of contact pads (1210, 2210) are embedded between the first insulation layer (1230, 2230) and the bonding area insulation layer (1243, 1244, 2243, 2244). Display substrate (100) according to one of the Protection claims 1 - 8th , wherein the first insulation layer (1230, 2230) comprises an organic insulation material. Display substrate according to one of the Protection claims 1 until 9 , further comprising: a first bonding area gate insulation layer (1242, 2242) located in the bonding area (1200, 2200) and on a side of the plurality of data leads (1220, 2220) and the bonding area insulation layer (1243, 1244, 2243, 2244) near the base substrate (1000, 2000), the bonding area insulation layer (1243, 1244, 2243, 2244) comprising: a first part located between the first contact pad metal layer (1215, 2215) of one of the plurality of contact pads (1210, 2210) and the one of the plurality of data leads (1220, 2220), a second part located between the one of the plurality of contact pads (1210, 2210) and the first bonding area gate insulation layer (1242, 2242), and a third part located between the first insulation layer (1230, 2230) and the first bonding area gate insulation layer (1242, 2242), and the first part, the second part and the third part of the bonding area insulation layer are connected to each other. Display substrate (100) according to one of the Protection claims 1 until 10 , further comprising: a third bonding region insulation layer (2260) located in the bonding region (2200) and on a side of the first insulation layer (2230) and the plurality of contact pads (2210) remote from the base substrate (2000), wherein the third bonding region insulation layer (2260) comprises third contact pad vias (2218) to expose surfaces of the plurality of contact pads (2210). Display substrate (100) according to Protection claim 11 wherein the third bonding area insulation layer (2260) covers the first insulation layer (2230) and further covers and directly contacts a portion of the plurality of contact pads (2210). Display substrate (100) according to Protection claim 11 or 12 , further comprising: a second transfer electrode structure (2270) located in the bonding region (2200) and on a side of the third bonding region insulation layer (2260) remote from the base substrate (2000), the second transfer electrode structure (2270) being electrically connected to the plurality of contact pads (1210, 2210) via the third contact pad vias (2218). Display substrate (100) according to Protection claim 13 , wherein in the bonding region (1200, 2200), a height of the second transfer electrode structure (2270) relative to a surface of the base substrate (1000, 2000) is not greater than a height of the third bonding region insulation layer (2260) relative to the surface of the base substrate (1000, 2000). Display substrate (100) according to one of the Protection claims 1 until 14 , wherein the bonding area insulation layer (1243, 1244, 2243, 2244) comprises a plurality of contact pad vias (1216, 1219), and wherein one of the plurality of contact pads (1210, 2210) is electrically connected to one of the plurality of data leads (1220, 2220) via one of the plurality of contact pad vias (1216, 1219). Display substrate (100) according to one of the Protection claims 1 until 15 , wherein the at least one group of contact pads comprises a first group of contact pads (1210, 2210) and a second group of contact pads (1210', 2210'), wherein the first group of contact pads (1210, 2210) and the second group of contact pads (1210', 2210') each comprise a plurality of contact pads, wherein the second group of contact pads (1210', 2210') are located on a side of the first group of contact pads (1210, 2210) near the display area (1100), and wherein the plurality of data leads (1220, 2220) are electrically connected to the first group of contact pads (1210, 2210) and the second group of contact pads (1210', 2210') in one-to-one correspondence. Display substrate (100) according to Protection claim 16 , wherein the plurality of contact pads of the first group of contact pads (1210, 2210) are arranged in at least a first row (L1), and the plurality of contact pads of the second group of contact pads (1210', 2210') are arranged in at least a second row (L2); wherein a row direction of the first row (L1) and a row direction of the second row (L2) are parallel to an extension direction of a side edge of the display region (1100) facing the bonding region (1200, 2200), and wherein the first insulation layer (1230, 2230) comprises a first part which is located in a gap between the first row (L1) and the second row (L2). Display substrate (100) according to Protection claim 16 or 17 , wherein the first insulation layer (1230, 2230) comprises a second portion located in gaps between adjacent contact pads (1210, 2210) in the first row (L1) and in gaps between adjacent contact pads (1210', 2210') in the second row (L2). Display substrate (100) according to one of the Protection claims 1 until 18 , wherein at least one of the plurality of subpixels (110, 210) comprises: a pixel driver circuit (1120, 2120) comprising a thin film transistor, the thin film transistor comprising a gate electrode (11211, 21211), a source electrode (1125, 2125), and a drain electrode (1126, 2126), the source electrode (1125, 2125) and the drain electrode (1126, 2126) being located in a first display area metal layer (1127, 2127) on a side of the gate electrode (11211, 21211) remote from the base substrate (1000, 2000), the first display area metal layer (1127, 2127) and the first contact pad metal layer (1215, 2215) are provided on the same layer; a first transfer electrode (1180, 2180) located on a side of the first display area metal layer (1127, 2127) remote from the base substrate (1000, 2000) and electrically connected to the pixel driving circuit (1120, 2120), the first transfer electrode (1180, 2180) and the second contact pad metal layer (1217, 2217) being provided on the same layer; and a light emitting element (1140, 2140) electrically connected to the first transfer electrode (1180, 2180). Display substrate (100) according to Protection claim 19 wherein the gate electrode (11211, 21211) and at least one of the plurality of data lines (1220, 2220) are provided on the same layer.

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