DE202017007536U1 - Inductive equivalence in instruction machining - Google Patents

Abstract

Processor configured to execute a method comprising the following steps:
retrieving candidate source code having a candidate function from a data store;
accessing a surrogate function from the data store;
accessing a hypothesis strength level and a resource constraint, the hypothesis strength level being determined by successfully completing a number of equivalency evaluations;
automatically determining the equivalence between the candidate function and the replacement function, wherein the processor performs the number of equivalence evaluations by running inputs through a plurality of processing operations and comparing the corresponding outputs until either the hypothesis strength level or the resource limit is reached;
if equivalence is determined by reaching the hypothesis strength level, automatically providing indicia of equivalence associated with the candidate function and the surrogate function;
if the indicia are provided, automatically transforming the candidate source code, comprising replacing the candidate function with the replacement function;
outputting the modified candidate source code; and
Store or otherwise make available the modified source code for future access and/or processing.

Description

field of revelation

The present disclosure generally relates to one or more pattern recognition and selective editing machines.

Technical background

The development of programmable machines progresses with the advancement of software and software writing tools. However, programmers often still write software that has already been written, whether for reasons of time associated with finding and verifying existing software, personal preference, ignorance of the existence of existing software, or other reasons. As a result, the software often has sections that are not ideal, even though they are functionally equivalent. Previous solutions include "Software Equivalence Checking," U.S. Patent Publication 2011/0138362, the contents of which are incorporated herein by reference in their entirety.

Compilers and interpreters convert human-readable source code into machine-readable code (e.g., object code, executable code, etc.) for execution. Compilers can eliminate the effects of many coding problems, but not all and not always completely. For example, software code that involves iterating through each element of an array may perform differently if the programmer iterates through the array by row elements and then increments the column, or by column elements and then increments the row. object code, such as An assembly language, for example, can store values differently and require more processing using one technique than another, even if the end result is the same. Likewise, the choice of a particular sorting method can have a significant performance impact, depending on the data being sorted. For example, a bubble sort is efficient when sorting a relatively small number of items, or a large number of items with only a few items that are not in the sort order. However, for most other uses or logins, the Bubble Sort is probably a poor choice.

Even if two software sets each give the same result, not every software has the same effect, e.g. B. within an application or a software management system. Software may have inefficiencies or other undesirable issues. As a result, computers or other machines running software cannot perform optimally.

Summary presentation

Certain disclosed embodiments may use SMT solvers and may be described using "Decision Procedures, An Algorithmic Point of View," Kroening and Strichman, 2008, ISBN: 978-3-540-74104-6, incorporated herein by reference in its entirety and for everything it teaches is absorbed, better understood. Additionally, the embodiments disclosed herein may be better understood by reviewing International Application Machine-Based Instruction Editing, PCT/US2016/017160 , filed on February 9, 2016 and published as WO 2016/130551 , which is incorporated herein by reference in its entirety and for all that it teaches.

Software or "code" refers to instructions written by a human for use by a machine such as an a microprocessor (or more generally "processor"), once the code has been put into a machine-readable form. Software may also be embodied in circuitry (eg, logic circuitry, firmware, etc.). Software has many properties that go beyond the functionality it was written to provide or the result it produces. For example, software requires space, requires machine cycles, is read by humans who may or may not have written the software, may have security vulnerabilities, may need to be updated, need to be ported to another platform, and/or other considerations. Often an ideal or preferred function is available that has previously been tested, studied, and determined to be preferred. As a general introduction and in one embodiment, a machine-based instruction is provided to automatically identify candidate function source code, determine whether the candidate function is functionally equivalent (e.g., produces the same result) to a preferred function source code previously checked and determined to be authorized source code, and if equivalent within a given hypothesis strength and/or resource constraint, the candidate Modify source code to preferred source code by replacing the candidate function with the preferred function and storing or otherwise making the modified source code available for future access and/or processing.

A "function" as used herein includes software functions, subprograms, procedures, (machine-executable) methods, predicates, sequences of instructions, or rules within a larger computer program, a relationship that associates an input with a single output according to a rule. The single output can be a primitive data type or a more complex data type such as a composite or abstract data type.

In one embodiment, two sections of source code are considered: a candidate function and a preferred function. As explained in more detail herein, it is determined that the candidate function and the preference function produce identical results or identical results with at least a predetermined hypothesis strength. For example, the output of the candidate function and the preference function is equivalent over all the inputs provided. In another embodiment, a logical equation for the candidate function and the preference function is determined and then submitted to an automated theorem prover, e.g. B. a Satisfiability Modulo Theories ("SMT") solver that can determine the equivalence of the functions over a finite set of inputs. However, differences may still exist. The candidate function may have been checked for one or more factors such as memory efficiency, execution performance, readability, maintainability, security, and/or other function-independent differences. In one embodiment, the difference includes the programming language. In another embodiment, the difference indicates compactness of the code. For example, "C=2A+2B" may be preferred over "C=A+A+B+B" and C=2*(A+B) over "C=2A+2B". In another embodiment, the difference indicates readability. For example, RectanglePerimeter=2(SideA + SideB) may be preferred over X=2A+2B. In another embodiment, the difference may include resource efficiency. So it can e.g. For example, it may be more efficient to access the entirety of a record from a remote database and keep the record in memory even if not all of the record's fields are needed than to access the remote database repeatedly to retrieve only the fields needed. The foregoing is an introduction to role-independent differences that may exist between a candidate role and a preferred role, and is not intended to be an exhaustive list.

In another embodiment, the candidate function differs from the preferred function; however, the difference is limited to members (e.g. inputs and/or outputs) within the same equivalence class. An equivalence class can be, for example, the binary value pairs (e.g. {(1,0), (TRUE, FALSE), (ON, OFF)}) or numeric equivalents (e.g. {".1", "0.1", "0.1000"}). .

Given the same input(s), if the preferred function and the candidate function produce different outputs, but they are all in the same equivalence class, then the preferred function and the candidate function can be determined to be functionally equivalent. For example, if the preferred function and the candidate function receive the same inputs, and the preferred function outputs TRUE and the candidate function outputs 1 (of a binary data type), then there can be functional equivalence, even if the outputs are not identical. However, if the preferred function returns "ON" and the candidate function returns "0" given the same input, the equivalence is broken.

In certain embodiments disclosed herein, the problems posed by previous computer systems and software development can be mitigated. The computer programming industry has been able to ignore many of the problems associated with limited processing, bandwidth, and storage capacity. The hardware has become cheaper and smaller. The investments required to turn adequate software code into efficient code that performs the function it was designed to do are often solved in hardware. Improving the software beyond its functionality has largely been abandoned in favor of developing adequate functionality and, once done, moving on to other tasks - a compromise easily accepted in prior art development practice.

In the early days of programming, concise programming was an artifact of language. Languages like assembler left few opportunities to do more than the essentials to enable the processor to provide the required functionality. Today there are many functional and object-oriented languages that give programmers ample opportunity to develop their programming and beautify documentation. However, when the program performs its functional task, it rarely offers more than that.

It is no longer enough to provide software that only performs a desired function. Certain computer implementations remain very sensitive to code memory requirements, processing time, and power requirements. While desktop computers and other fixed-location computing systems often solve any processing or storage limitations with additional hardware, mobile computing is particularly sensitive to storage, processing, and power requirements. Even a very modest improvement in storage, processing, and performance requirements can mean a game-changing breakthrough that turns a previously impractical device into a practical product. In addition, factors such as reusability are often touted but rarely used in practice, and when they are, a significant effort by a human programmer is required to ensure functional equivalence. However, with the aid of the disclosure contained herein, the computer sciences can benefit from software machining to achieve more robust, secure, and reusable code.

Another advantage of the embodiments disclosed herein is that testing and verification can be reduced or even eliminated since functional equivalence is guaranteed within a given constraint on hypothesis strength and/or resource usage (e.g., processors, process cycles, time, etc.). An essential part of any software development project that uses the state of the art involves confirming that the functional goals will be met by the program. However, the present disclosure provides the advantage that once a function is approved, any functionally equivalent subsequent code can be replaced with the approved code and functional equivalence is assured without the need to subsequently test the approved code.

The expressions "at least one", "one or more" and "and/or" are indefinite expressions that can be used both conjunctively and disjunctively. For example, each of the phrases means "at least one of A, B and C", "at least one of A, B or C", "one or more of A, B and C", "one or more of A, B or C ' and 'A, B and/or C', A alone, B alone, C alone, A and B together, A and C together, B and C together or A, B and C together.

The term "a" or "an" entity refers to one or more of such entities. The terms "a" (or "an"), "one or more" and "at least one" may be used interchangeably herein. It is also noted that the terms "comprising," "including," and "comprising" can be used interchangeably.

The term "automatic" and variations thereof, as used herein, refers to any process or operation that is performed without significant human input when the process or operation is executed. However, a process or operation may be automatic even if execution of the process or operation requires tangible or intangible human input if the input is received prior to execution of the process or operation. Human input is considered material if it affects how the process or operation is performed. Human input consenting to the execution of the process or operation is not considered "essential".

As used herein, the term "computer-readable medium" refers to any tangible storage device that helps deliver instructions to a processor for execution. Such a medium may take many forms, including but not limited to non-volatile media, volatile media, and transmission media. Non-volatile media have z. B. NVRAM or magnetic or optical disks. Volatile media include dynamic memory, such as B. main memory on. Common forms of computer-readable media include, for example, a floppy disk, flexible disk, hard disk, magnetic tape or other magnetic medium, magneto-optical medium, CD-ROM, other optical medium, punched cards, paper tape, other physical medium with punched patterns , RAM, PROM, EPROM, FLASH EPROM, a solid state medium such as a memory card, other memory chip or cartridge, or other medium from which a computer can read. If the computer-readable medium is embodied as a database, the database can be any type of database, such as e.g. B. relational, hierarchical, object-oriented and / or the like. Accordingly, the disclosure is deemed to exist on a tangible medium and as of the prior art includes art-recognized equivalents and successor media in which the software implementations of the present disclosure are stored.

While machine-executable instructions may be stored and executed locally on a specific machine (e.g., a personal computer, mobile computing device, laptop, etc.), it should be recognized that the storage of data and/or instructions and/or execution at least a portion of the instructions may be provided via a connection to a remote data storage and/or processing device or collection of devices commonly known as "the cloud," but public, private, dedicated, shared, and/or other service bureau, a computing service and/or a "server farm".

The terms "determine," "calculate," and "calculate," and variations thereof, are used interchangeably herein and encompass any type of methodology, process, mathematical operation, or technique.

The term "module" as used herein refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and software capable of performing the functionality associated with that element to execute. Although the disclosure is described in terms of exemplary embodiments, it should be understood that other aspects of the disclosure may be separately claimed.

The term "human-readable" in relation to source code, code, software, or equivalent, as used herein, refers to computer instructions that use a computer-readable format that cannot be read by any machine for the purpose of executing the instructions without interpretation or compilation can. The source code may have symbolic representations, such as named variables, functions (e.g. "float payment (int principle, float interest)"), which may have linguistic representations (e.g. "if", "return", "get", "fetch" , etc.) and linguistic character representations (e.g. "=", ".", "(", ")", etc.) which may be known as "reserved words". The programming language used for the human-readable source code may have specific rules as to what is and is not a reserved word or equivalent symbol. In general, the source code is the human output of a developed programming instruction and is commonly known by the source code language (e.g. Python, C, C++, FORTRAN, BASIC, etc.).

As used herein, the term "machine-readable" in relation to machine code, code, software, or equivalent, refers to human-readable code that has been processed via a compiler or interpreter to have a machine-readable and executable form of human-readable source code. In one embodiment, the machine-readable code is assembler. In another embodiment, the machine-readable code is machine code (e.g., binary code). The machine-readable code may use standardized identifiers that translate symbolic representations from human-readable source code (e.g., "principle" and "interest" become "$01" and "$02", "sale" and "tax" become "$03" and "$04 ', etc.) to eliminate, in whole or in part, differences between similar functions provided by different source code languages, and may also become more platform-specific (e.g. Intel x86, Motorola 8000x, CISC, RISC, etc.) to improve the instruction set for Processors or processor families to consider. Machine-readable code may not require further processing to be read by a machine, such as a microprocessor, but may require additional processing (e.g., linking) to be executable by the machine. While a skilled programmer may be able to "read" machine code, if such form of software does not contain language-based symbols, such machine code is considered non-human readable.

The term "data storage" as used herein is a device, medium, component, portion of a component, collection of components, and/or other structure capable of storing data required for a processor are accessible. Examples of data storage considered here include processor registers, on-chip memory, on-board storage, hard drives, solid-state devices, fixed media devices, removable media devices, logically attached storage, networked storage, distributed local and/or remote storage (eg server farms, "cloud" storage, etc.), media (eg, solid-state, optical, magnetic, etc.), and/or combinations thereof. The data store can be accessed by at least one processor, but may be logically and/or physically separate from the processor if no processor has a current need for access. The data storage can be accessed directly or via a or multiple intervening components including, but not limited to, a cache and/or buffer. In certain embodiments, data storage may be organized into a database, file, record, or other logical storage structure and/or a portion or collection thereof.

character list

• 1 zeigt ein erstes System gemäß den Ausführungsformen der vorliegenden Offenbarung;
• 2 zeigt ein zweites System gemäß den Ausführungsformen der vorliegenden Offenbarung;
• 3 zeigt ein drittes System gemäß den Ausführungsformen der vorliegenden Offenbarung;
• 4 zeigt ein viertes System gemäß den Ausführungsformen der vorliegenden Offenbarung;
• 5 zeigt ein Verfahren gemäß den Ausführungsformen der vorliegenden Offenbarung;
• 6 zeigt ein fünftes System gemäß den Ausführungsformen der vorliegenden Offenbarung;
• 7 zeigt eine Begrenzungskomponente der Äquivalenzbestimmung gemäß den Ausführungsformen der vorliegenden Offenbarung;;
• 8 zeigt eine Ressourcenbelegungskomponente der Äquivalenzbestimmung gemäß den Ausführungsformen der vorliegenden Offenbarung;
• 9 zeigt ein sechstes Verfahren gemäß den Ausführungsformen der vorliegenden Offenbarung; und
• 10-71 zeigen eine Lösung gemäß den Ausführungsformen der vorliegenden Offenbarung.

The present disclosure is described in connection with the attached figures:

• 1 Figure 1 shows a first system according to embodiments of the present disclosure;
• 2 12 shows a second system according to embodiments of the present disclosure;
• 3 Figure 13 shows a third system according to embodiments of the present disclosure;
• 4 12 shows a fourth system according to embodiments of the present disclosure;
• 5 Figure 12 shows a method according to embodiments of the present disclosure;
• 6 12 shows a fifth system according to the embodiments of the present disclosure;
• 7 12 shows a limiting component of the equivalence determination according to the embodiments of the present disclosure;
• 8th FIG. 12 shows a resource allocation component of the equivalency determination according to embodiments of the present disclosure; FIG.
• 9 12 shows a sixth method according to the embodiments of the present disclosure; and
• 10-71 show a solution according to the embodiments of the present disclosure.

Detailed description

The following description is merely exemplary in nature and is not intended to limit the scope, applicability, or phrase of the claims. Rather, the following description should enable the person skilled in the art to implement the embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the appended claims.

Any reference in the specification having an element number without a sub-element identifier when a sub-element identifier is present in the figures, when used in the plural, is intended to refer to two or more elements with a same element number. When such a reference is in the singular, it shall refer to one of the elements with the same element number, without being limited to any particular element. Any express use herein to the contrary, or any further qualification or identification, takes precedence.

The example systems and methods of this disclosure are also described in terms of analysis software, modules, and associated analysis hardware. However, in order not to unnecessarily obscure the present disclosure, the following description avoids well-known structures, components, and devices that may be shown in block diagram form that are known or otherwise summarized.

For purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be appreciated that the present disclosure can be practiced in a variety of ways beyond the specific details set forth herein.

1 10 shows a system 100 according to embodiments of the present disclosure. The system 100 includes a processor 106 that accesses the source code 102 in which the candidate functions 104A-104D reside. In one embodiment, at least one of the candidate functions 104 comprises a function that receives at least one input to produce at least one output. In another embodiment, at least one of the inputs and outputs may be a function parameter, input from a human input device, memory address, register, port, or other data source. In another embodiment, the output may be a function output written to an address presented on an output device written to a memory written to a memory address or a register that is output at a port, and/or any other input and/or output device known in electronic data processing.

In one embodiment, source code 102 may include candidate functions 104 written by a programmer, for example using an integrated development environment or other software authoring tool. In one embodiment, source code 102 is presented with a variety of functions 104 . In another embodiment, source code 102 may include a single function 104, such as 104A.

Processor 106 accesses source code 102 and functions 104 and compares some of candidate functions 104 to some of preferred functions 108A-108n maintained in data store 114. The processor 106 can then identify which of the candidate functions 104 to replace with which of the preferred functions 108, and the processor 106 can then create data sets, such as: e.g., those having capability identifiers 110 associated with indicia 112 to establish an association between some of candidate capability identifiers 116A-116D and some of surrogate identifiers 118A-118-D. For example, the function identifier 116A ("candidate function 1"), which identifies a particular function, candidate function 1 (104A), is associated with the function indicia 118A indicating replacement with preferred function 108C (identified as "preferred function C"). In another embodiment, the replacement indicia 118B associated with the function identifier 116B may indicate that the associated function candidate function 2 (104B) should be retained. For example, candidate function 2 ( 104B ) may have no counterpart or determinable counterpart in data storage 114 or may otherwise not be functionally equivalent to one of preferred functions 108 . In another embodiment, a recommendation or teaching may be implemented in addition to or as an alternative to performing the replacement. For example, a programmer may be presented with a message indicating that a function written by the programmer (e.g., "Candidate Function 1") can be improved, and optionally presented with the improvement criterion to make another function (e.g., "Preferred Function C") more similar .

The indicia 112 are illustrated as having human-readable English data entries, an embodiment chosen in part for the sake of clarity. Other embodiments contemplated herein include a data value such as an entry in a data element (e.g., binary, enumerated data type, data structure, etc.) and/or the presence of a data element (e.g., flag/no flag, record/ (not a record, object/object, etc.) held in volatile memory, non-volatile memory, media, data storage 114, other data storage, media, and/or other data-storing component, collection of components, or portions thereof and may be implemented in the embodiments disclosed herein without departing from the scope of the disclosure.

2 10 shows the system 200 according to embodiments of the present disclosure. In one embodiment 2 , how the system 200 the source code 102 (see 1 ) changed to preferred source code 202 using function indicia 112. Processor 106 accesses functional indicia 112 having entries 118 and associated with respective functional indicia 110 having entries 116 . The processor 106 then accesses the source code 102 to produce a preferred source code 202, a source code that is functionally equivalent to the source code 102, but provided with substitutions, wherein at least one candidate function 104 is replaced by a functionally equivalent preferred function 108, where the equivalence is within a defined hypothesis strength and/or resource limitation. The processor 106 accesses the preferred functions 108 specified in the function indicia 112 from the data store 114 and provides automatic substitution to generate the preferred source code 202 .

In one embodiment, preference 1 (104A) is replaced with preference C (108C), preference 2 (104B) is retained, preference 3 (104C) is replaced with preference A (108A), and preference 4 (104D ) is replaced by the preferred function X (108X). Preferred source code 202 may then be saved and designated as preferred source code and made available for additional development, compilation or interpretation, linking, execution, and/or storage to be accessible at a later time.

3 10 shows the system 300 according to embodiments of the present disclosure. In one embodiment, system 300 depicts source code 102 being modified into preferred source code 202, with indicia of functional equivalence within a defined hypothesis strength and/or Resource limitations are maintained exclusively by the processor 106, so that the processor 106 can issue the preferred source code 202 directly. For example, processor 106 may access source code 102 and determine that candidate functions 1 (104A), 3 (104C), 4 (104D) are replaced by preferred functions 108 (see 1 ) maintained by the data store 114 are to be replaced. As a result, the processor 106 can directly issue preferred source code 202 that has preference function C (108C) and retains preference function 2 (104B), preference function A (108A), and preference function X (108X).

4 10 shows the system 400 according to embodiments of the present disclosure. In one embodiment, it is determined whether two functions are equivalent within a defined hypothesis strength and/or resource constraint, e.g., whether candidate function 1 (104A) is functionally equivalent to preferred function C (108C), i.e. equivalent within a defined hypothesis strength and/or resource constraint, and by applying logic. The logic is implemented in various embodiments. In one embodiment the logic comprises first order logic, in another embodiment the logical equation comprises second order logic. In one embodiment, a single candidate function 402 is considered to determine equivalency with a single preference function 404 . In other embodiments, candidate function 402 may include a variety of functions, such as: B. a plurality of candidate functions 104 and / or the preference function 404 may have a variety of functions such. a plurality of preference functions 108. While a logical equation may show equivalence with identical values, e.g. B. "A or B" is identical and therefore equivalent to "A or B". But non-identical but functionally equivalent representations can also indicate equivalence, e.g. B. "A or B" is non-identical but functionally equivalent to "B or A". Additionally, symbolic representations can be used to represent at least a portion of an equation, e.g. "A or B" is not identical but functionally equivalent to "A or (X and Y nor Z)" when "B" stands for "X and Y still Z” stands.

In another embodiment, functional equivalence is determined by non-equivalence with all but one member of an enumerated set for which candidate function 402 is a known member. For example, candidate function 402 may be known to perform a basic mathematical function, namely one of addition, subtraction, multiplication, and division. Preference function 404 can be determined to be functionally equivalent to candidate function 402 if preference function 404 is a member of the set of four basic mathematical functions and non-equivalence is determined for three other functions such that preference function 404 is the only function for which an equivalence is determined, and is therefore functionally equivalent.

int sum_mod (int x, int y) {
      if (y == 0) {

           }throw domain_error ("Modulus cannot be 0.");
      }

      if (y<0) {
            int pos_y = -y;
            }return sum_mod(x, pos_y);
      }

      if (x<0) {
            while (x<0) {
                 x+=y;
            }
            return x;
      }

      while (x>=0) {
           x -= y;
      }
      }return (x+y)
      }

The candidate function 402 has an input/output signature that is parsed via the parse function I/O 406 . Similarly, preference function 404 has an input/output signature that is parsed via parse function I/O 408 . Listing 1 contains an example of candidate function 402:

 int sum_mod (int x, int y) {
      if (y == 0) {

           }throw domain_error ("Modulus cannot be 0.");
      }

      if (y<0) {
            int pos_y = -y;
            }return sum_mod(x, pos_y);
      }

      if (x<0) {
            while (x<0) {
                 x+=y;
            }
            return x;
      }

      while (x>=0) {
           x -= y;
      }
}return (x+y)
      }

LIST 1

             int div_mod (int x, int y) {
                  if (y==0) {
                       throw domain error ("Modulus cannot be 0.");
                  }
                  int div = x/y;
                  int rem = x - (div*y);
                  return rem;
             }

Listing 2 shows an example of preference function 404:

 int div_mod (int x, int y) {
                  if (y==0) {
                       throw domain error ("Modulus cannot be 0.");
                  }
                  int div = x/y;
                  int rem = x - (div*y);
                  return rem;
             }

LIST 2

In one embodiment, the preference function 404 has been examined and determined to be preferred, e.g. B. due to the conciseness of the human-readable code it contains. Conciseness can be achieved through an abstract syntactic structure, such as an Abstract Syntax Tree (AST). For example, fewer nodes, fewer leaf nodes, node depth, and node width can represent a succinct metric. The functional equivalence service 410 then determines whether the equivalence is true. In one embodiment, the functional equivalence service derives first order logic 412 for parsed candidate function 402 and first order logic 414 for parsed preference function 404 to derive first order logic comprising SMT query 416 in one embodiment.

                             f1-sum_mod:
                             [...f1 Logic ...]
                             Inputs:
                             [f1(x), f1(y)]
                             Outputs:
                             [f1(retVal)]

Listing 3 shows an example of a function broken down into logic, inputs and outputs.

 f1-sum_mod:
                             [...f1 logic...]
                             inputs:
                             [f1(x), f1(y)]
                             outputs:
                             [f1(retVal)]

LIST 3

                             f2-div_mod:
                             [...f2 Logic ...]
                             Inputs:
                             [f1(x), f2(y)]
                             Outputs:
                             [f2(retVal)]

Listing 4 shows another example of a function broken down into logic, inputs, and outputs.

 f2-div_mod:
                             [...f2 logic...]
                             inputs:
                             [f1(x), f2(y)]
                             outputs:
                             [f2(retVal)]

LIST 4

List 5 shows an example of an SMT query. $$\left(\text{<figure-callout id="1" label="f" filenames="DE202017007536U1\_0008.png,DE202017007536U1\_0009.png" state="{{state}}">f</figure-callout>}1\text{logic}\right)\left(\text{<figure-callout id="2" label="f" filenames="DE202017007536U1\_0008.png,DE202017007536U1\_0009.png" state="{{state}}">f</figure-callout>}2\text{logic}\right)\left(\text{f}1\left(\text{x}\right)=\text{f}2\left(\text{x}\right)\right)\left(\text{f}1\left(\text{y}\right)=\text{f}2\left(\text{y}\right)\right)\left(\neg \left(\text{f}1\left(\text{retVal}\right)=\text{f}2(\text{retVal}\right)\right)$$

LIST 5

In another embodiment, the SMT query 416 is submitted to the SMT solver 420 to produce an output that indicates a satisfied ("SAT") non-equivalence result or a NO result 422 or a non-satisfiable (" UNSAT") equivalence result or a 424 YES result.

5 FIG. 5 shows the process 500 according to embodiments of the present disclosure. In one embodiment, process 500 is performed, eg, by processor 106. Process 500 may begin with either or both of steps 502, 504, where step 502 accesses a candidate function, such as from candidate source code 102 that includes a plurality of Functions 104 may have. Step 504 accesses a preference function comprising, for example, one or more preference functions 108 within a preference source code 202 .

Next, step 506 determines whether the functions are functionally equivalent (e.g., produce the same results given the same inputs) within a defined hypothesis strength and/or resource constraint, and if so, the process 500 continues to optional step 508 to provide indicia for replacement or, if step 508 is not implemented, to provide the indicia external to the process 500. Otherwise, processing continues with step 510. In step 510, the candidate function 502 is replaced with the preferred function 504. If step 506 is determined negatively, no replacement is required and process 500 may end. Optionally, following step 510, the source code comprising the now replaced preference function 504 may be stored on media or otherwise preserved for additional or future processing and/or reference.

As provided herein, preferred source code, for example having one or more preferred functions 108, may be provided by automatically replacing a functionally equivalent but non-preferred candidate source code, for example having one or more candidate functions 104. The preferred source code may be determined to be preferred based on a prior review, with the preferred source code being approved for use. Preferred Source Code may vary due to storage requirements of human-readable form and/or machine-readable form, performance metrics, security, existence of internal documentation, existence of a certain amount of internal documentation, use of verbose variable names, conciseness of instructions, error handling, and/or other attributes are designated as preferred source code. In another embodiment, source code is preferred based on prior verification. In a further embodiment, the source code in question has not undergone any prior testing. In another embodiment, the preferred source code has been reviewed by a higher authority than the candidate source code, which may have been reviewed by a lower authority, such as the developer of the candidate source code. In another embodiment, the determination of preferred source code may be determined according to a criterion, e.g. one or more of fewer lines of code, fewer procedural calls, more comments, longer variable names, etc.

6 6 shows the system 600 according to embodiments of the present disclosure. System 600 shows processor 106 accessing candidate source code 102 having candidate function 602 . In one embodiment, processor 106 determines that candidate function 602 is functionally equivalent to at least one preferred function 606A-606n maintained in data store 114 within a defined hypothesis strength and/or resource constraint.

In one embodiment, processor 106 transforms the candidate source code into one of preferred source codes 604A-606E. In another embodiment, the processor 106 changes the preferred source code to two or more of the preferred source codes 604A-604E. The processor 106 modifies the source code 102 to one or more of the preferred source codes 604A-604E to provide a source code, e.g. B. a source code file to issue, which meets at least one preferred aspect. The preferred source code can lead to a more optimal operation of a machine or component of a machine, e.g. by performing fewer operations, faster operations, smaller memory requirements, performing an operation with fewer resource requirements, using less expensive resources (e.g. energy, expenses, etc.), executing more secure operations, etc. The preferred aspect takes a variety of forms and includes security, CPU efficiency, bandwidth efficiency, memory requirements, conciseness of code, database access, or a combination of two or more.

In one embodiment, processor 106 determines that candidate function 602 is functionally equivalent to preferred function 606A, determined to be preferred in terms of CPU usage (e.g., clock cycles, operations, etc.), within a defined hypothesis strength and/or resource constraint. Accordingly, processor 106 changes source code 102 to preferred source code 604A, which has preferred function 606A in place of candidate function 602. As a result, source code 102 is transformed into source code 604A.

In another embodiment, the processor 106 determines that the candidate function 602 is functionally equivalent, within a defined hypothesis strength and/or resource constraint, to the preferred function 606B that has been determined to be preferred in terms of security. For example, function 606B may use a previously approved communications encryption protocol, communications port, error handler, and so forth.

In another embodiment, the processor 106 determines that the candidate function 602 is functionally equivalent, within a defined hypothesis strength and/or resource constraint, to the preferred function 606C determined to be preferred in terms of code conciseness. For example, function 606C may use human-readable source code that has been determined to be more concise to promote readability and optionally machine efficiency. For example, it may be preferable to use source code that uses fewer operators, such as "X++" versus "X = X+1."

In another embodiment, processor 106 determines that candidate function 602 is functionally equivalent, within a defined hypothesis strength and/or resource constraint, to preferred function 606D that has been determined to be preferred for storage. Even with modern data storage technology, data storage can still be an issue, particularly in embedded systems and mobile technology where chip and board real estate is more critical. For example, function 606D may use source code that requires less memory, such as "i=r*b" may be preferred over verbose "interest= rate * balance".

In another embodiment, processor 106 determines that candidate function 602 is functionally equivalent, within a defined hypothesis strength and/or resource constraint, to preferred function 606E, which has been determined to be preferred in terms of both security and bandwidth. For example, preference function 606E may use fewer network dependent operations and a preferred port and/or security protocol.

7 7 shows the component 700 for determining equivalency, in accordance with embodiments of the present disclosure. In one embodiment, equivalence is determined with absolute certainty. For example, all possible inputs to both candidate source code (e.g., candidate source code 102, candidate function 1 (104A), candidate function 2 (104B), etc.) and a preferred source code (e.g., preferred source code 112, preferred function A (108A), preferred function B (108B) , etc.) are input, and then equivalence can be determined with absolute certainty if, for one of the inputs, the resulting output is identical for both the candidate source code and the preferred source code. However, in other embodiments it is not possible to test to exhaustion. resources, such as B. processing, time and bandwidth resources are not unlimited. Such resources are often mutually exclusive. Accordingly, equivalence may be determined if the candidate source code and the preferred source code are determined to be equivalent when compared within the constraints of a resource constraint.

Often the resource limitations and/or an acceptable hypothesis strength requirement make testing equivalence to exhaustion undesirable or unnecessary. For example, a complex candidate source code can be evaluated against a preferred source code. There may be an assumption, e.g. by a human, that the candidate source code is likely to be equivalent to a particular preferred source code or set of preferred source codes. Often, however, such assumptions cannot be made or they are inaccurate. For example, a fully automated system may not be able to find preliminary matches to a particular preferred source code or set of codes, and must therefore determine equivalency against an entire pool of preferred source codes until sufficient equivalence is found. In other embodiments, a preferred source code may include names of variables, functions, modules, etc. that provide an indication of which preferred source code or codes are best suited for determining equivalence. For example, if the variables are "interest" and "account number" then it is "banking". "Accounting" or similar source code may be considered for equivalence, or at least first. If no match is found, another area of the preferred source code (e.g. "insurance", "broker", etc.) can be selected.

Consequently, failure to determine equivalence may be viewed as failure to determine equivalence with a candidate source code and a particular preferred source code. Other source code may be equivalent.

In one embodiment, the equivalency is determined against a system limitation under time pressure. With unlimited time, even the smallest processor can perform the most intense processing activity. Likewise, with an unlimited amount of hardware, only a trivial amount of time is required to perform the same intensive processing activity. Such unbounded constraints are often outside of reality, as processing tasks must be performed on a limited processing platform and/or within a limited time frame. If the equivalence is not proven, the task can be aborted. However, proof of equivalence can also consist in the fact that no non-equivalence is found during a resource-constrained equivalence test.

In one embodiment, the processing resource is fixed and the time available for the processing resource to perform the equivalence assessment is variable. For example, a desktop computer can run the assessment and a response is expected within an hour. A fixed resource may be fully committed (e.g., dedicated solely to the assessment task) or partially committed (e.g., a multitasking processor that performs the assessment task and other tasks). A partially committed resource may perform more or less judgment processing depending on the demands that other tasks place on the processor. Accordingly, an evaluation for a fixed period of time may result in a variable number of processor operations, or a fixed number of processor operations may result in a variable duration. Preferably, a human or supervisory computer process is provided with the potential impact that may exist if extraneous processing requests are made to the processor executing the assessment for management (e.g., setting a priority level sufficient to assign the processor to do the assessment within the desired number of operations/time, disabling foreign tasks, changing a requested resource limit in view of additional resource limits imposed by foreign tasks, etc.).

In one embodiment, the equivalence limit component 700 indicates a relative priority for an equivalence operation. For example, the joystick 702 can select a relative position along the time axis 704, the hypothesis strength axis 706, and the resource use axis 708. As shown, the joystick 702 is located near the center of the equivalence limit component 700, indicating a nearly balanced strategy. In particular, the reduction in resource usage is emphasized but not maximized, as indicated by line segment 712, which has non-zero length but is shorter than line segments 710 and 714. Hypothesis strength is the second axis that is emphasized, as represented by line segment 710, which is longer than line segment 712 but shorter than line segment 714. Time is the third axis and is relatively less emphasized, as represented by line segment 714, which is longer than line segments 710 and 712.

In another embodiment, a system, e.g. e.g., using processor 106, receive input from equivalence constraint component 700 and perform an equivalency determination based on lower resource usage, further reduced hypothesis strength, and with less consideration of time requirements. The system can convert such inputs into machine-executable instructions, e.g., allocate a single processor to execute a high-priority equivalence process (e.g., reduced use of resources), execute equivalence and/or the absence of non-equivalence with an 85% hypothesis strength ( e.g., a reduced hypothesis strength) and to carry out the instructions for twenty hours (e.g., with less regard for the time taken).

Those skilled in the art will recognize that hypothesis strength can be determined as the successful completion of a number of equivalence assessments that meet a certain standard deviation or other statistical requirement. The system may provide the user with an output based on a particular setting in the equivalence limit component 700 . For example: "To determine equivalence with at least your chosen hypothesis strength, the processor will run almost exclusively on this machine for twenty hours, performing twelve million operations to determine whether the 'candidate source code' matches the 'preferred source code ' is equivalent, and if successful, equivalence is provided with a hypothesis strength of 85.04%. Press 'Start' to begin.”

In another embodiment, a system may run until interrupted, and equivalency limiting component 700 may be a display showing a current state indicates. For example, when an equivalence operation is initiated, joystick 702, which may be physical or a display element, may be near the bottom of 7 to indicate that the time is currently at its lowest value. Because the number of operations may be trivial, the joystick 702 may indicate that the hypothesis strength is lowest. As more operations are executed, the joystick 702 can move accordingly to display a current execution time and a current hypothesis strength.

In another embodiment, the equivalence constraint component 700 may include specific axes, such as e.g. e.g. resource 712, if the processing resources are at least substantially fixed or at least not significantly variable. For example, a user who has a rack of blade servers available cannot increase the processing capacity of the rack without adding additional blades. While resource-limiting component 700 may display an option to add hardware, in other embodiments resource-limiting component 700 is limited to currently available options, e.g. B. to those available within the few seconds it may take a user to enter the desired parameters and initiate the equivalence operations.

In another embodiment, a system boundary may be determined and used to quantify an operation. For example, if a given candidate code could be traversed in 1 millisecond using a single set of input variables, and a full set of input variables would have 10 million values, then equivalence would be determined with absolute certainty in about 2.8 hours. For the sake of simplicity, it is assumed in the example that the iteration of the preferred source code has already been performed, with the input-output combinations being held in memory and requiring only a negligible access time. It should be noted that if it has not already been done, the time taken to iterate through the preferred source code with the set of inputs to get the set of output values may need to be added to get a better estimate of the time required. Similarly, the time taken to compare each output from the candidate and preferred source code can be added to the time taken.

Considering the time needed, an alternative can be chosen, e.g. B. to perform the determination on another computer system and/or perform fewer operations. For example, assuming a standard distribution where a hypothesis strength of 50% corresponds to a cumulative percentile of 50%, a first test can be performed. An additional or more powerful processor can be used to achieve a hypothesis strength of 75%, which corresponds to a cumulative percentile of 75%, within the same time window. It should be noted that the tests may deviate from a particular statistical curve due to the complexity or detail of a particular value being tested. For example, running 1,000 tests on a section of code may require setup or other overhead that causes such a test to fail differently than two groups of 500. Also, a specific value may cause a specific section of the Code is executed that is particularly time-consuming or time-saving. For example, randomly testing code with a numeric input given a relatively small number of values for such an input may trigger an offline operation (e.g., accessing a remote server, mounting a tape drive, etc.). Accordingly, running a test that has a fixed number of iterations two or more times may cause the time required for each test to vary. In another embodiment, these times can be recorded and a probability curve of the times constructed with the resulting confidence values (e.g., a test with 1,000,000 inputs based on multiple tests of 1,000 iterations each takes 75 with 97.7% probability seconds +/- 10 seconds).

In another embodiment, the user decides that the target error rate for functional equivalence is a certain percentage (D). The user also selects a black-box statistical sampling method with a sample size N. In such an embodiment, the hypothesis strength (HS) is calculated as the random probability of not detecting an error at the assumed error rate, as given in Formula 1, when no case of different outputs is discovered with the same entries for a candidate code and a preference code.

$$\text{HS}=1-{\left(1-\text{D}\right)}^{\text{N}}$$

Functional equivalence is the property of two arithmetic functions to be equivalent. Equivalency can be embodied in various embodiments. One embodiment is formal (or deductive) and another embodiment is empirical (or inductive). According to the formal embodiment, two functions are equivalent if the consecutive operations performed by one can be mathematically or logically reduced to the consecutive operations performed by the other. According to the empirical embodiment, if the arguments given as input are the same, the value returned by the two functions is the same. The formal embodiment can entail the empirical embodiment, but not vice versa.

The empirical embodiment assumes a non-zero theoretical error probability, even if this probability is very small. The strength of the functional equivalence hypothesis is then the level of confidence that this probability of failure is bounded by an extremely low upper bound.

Functional equivalence or Functional Equivalence Hypothesis Strength (FEHS) can be defined as follows:

Suppose "G" and "F" are functions whose functional equivalence to each other is currently unknown. The G-F function equivalence hypothesis is the hypothesis that the functions G and F are inductively equivalent, i.e. with respect to their inputs and outputs. Formally, for all inputs (“x”), G(x) is equivalent to F(x), so we have formula 2:

$$\forall \text{x},\text{G}\left(\text{x}\right)=\text{f}\left(\text{x}\right).$$

The defect rate (DR) of a G-F functional equivalence hypothesis is the probability that F and G will give two different values given an input. If x is a random input to F and G, the formula 3 is:

$$\text{DR}\left(\text{f},\text{G}\right)=\text{Pr}\left(\text{f}\left(\text{X}\right)\ne \text{G}\left(\text{X}\right)\right).$$

We define a parameter called Maximum Defect Rate (MDR) as the maximum defect rate that is acceptable in a given context. By default, this rate is set to MDR = 0.0001.

The strength, see Formula 4, of the G-F functional equivalence hypothesis is the confidence level for its error rate, which is chosen between 0 and 0.0001 after N successful trials, see Formula 5.

$${\text{S}}^{\text{G}-\text{f}}\left(\text{N}\right)$$

$$\text{S}=1-{0.9999}^{\text{N}}.$$

Formally, according to formula 6:

$$\text{FEHS}\left(\text{f},\text{G}\right)=\text{P}\left[0<\text{DR}\left(\text{f},\text{G}\right)<0.0001\text{/N achievements}\right].$$

It should be noted that the error rate is a value between 0 and 1 or a narrower fraction thereof. For example, and as used here (see Formula 5), the error rate is 0.0001. Of course, other error rates can also be selected. In another embodiment, the selected inputs can also be random (e.g., an unbiased selection of values for all potential values of a particular data type), weighted random (e.g., a preferred tendency to select a more likely value, such as a normal distribution curve of inputs that can lead to that the selection follows a similar normal distribution curve), historical (e.g., a set of known prior inputs), or other sets of values that can be determined according to known or conjectured distributions. For example, an input for a signed short integer is -32,768 to 32,767. However, if the input has the variable name "Month", the value for the "short" can be selected via a lookup function or other data set from the set of numbers from 1 to 12 that indicate the possible values for a month. However, to avoid possible errors in such a selection (e.g. months from a particular event can be accumulated and not just a calendar value), additional and/or different distributions of inputs can be used. It should be clear that such an approach is an optional embodiment, since comparing two functions that use calendar months and input a large value should both return an error code or otherwise provide equivalent processing.

In another embodiment, the hypothesis strength may correspond to statistical confidence. In other embodiments, hypothesis strength represents a similar concept but a different representation of the selected input, e.g. B. when the values selected as inputs are not random or not completely random. Accordingly, and in another embodiment when less than all possible inputs are considered, the selection of the input set may be a random sample of all possible inputs. However, in other embodiments, the inputs may be partially random (e.g., random but having at least one specific value, such as zero and/or one for an integer), non-random, fixed, or deliberately selected, such as as a result of path analysis, to determine the Consistent with the goal of ensuring that code branches are tested at least a desired number of times. For example, a candidate source code may be analyzed and determined to have a branch that occurs when an integer is between 1 and 50. Accordingly, values can be chosen where a more than random portion of the inputs falls between 1 and 50. Additionally or alternatively, a source code candidate with a finite or enumerated branch type based on a relatively small number of inputs compared to all possible values for an input can be weighted such that more or even all values necessary for the branch or another operation are crucial. Time and/or other resource estimates may be made accordingly. if e.g. For example, if an integer between 1 and 50 triggers a call to a backup tape that requires ten seconds per call, and any other value does not perform such a time-consuming operation, the time estimate can reflect that event based on the number of input values passed in will fall or are estimated to fall within the range of 1 to 50. Alternatively, in another embodiment, another system, e.g. a solid-state backup system, may be chosen to avoid the time required to access data on magnetic tape. The associated costs (e.g., setup effort, allocation of other resources, deprioritization of other programs, etc.) may be considered. Advantageously, the determination of equivalence can be made to a certain extent based on the computing requirements and the available system capacities and vice versa.

The input values can be selected according to their data type. For example, testing all possible combinations of letters in a string is probably not very useful. However, testing a different number of characters, a different mix of uppercase and lowercase letters, special characters, numbers, and/or other input may have a higher test value, since string processing errors are known to occur more frequently when unexpected values are provided. For data structures (e.g. a specific combination of a large number of data types), the test time can be estimated using the data types that make up them. However, for some data structures and standard data types, a small sample can be run and timed to more accurately determine the time required for a given equivalence test to reach the selected hypothesis strength. Data types and/or data structures that selectively access resources with an unknown response time can be evaluated more precisely by such a pilot test. The sample size can be fixed or determined dynamically based on the variability of the time it takes a given iteration to produce an output. For example, if twenty pilot trials are run and the variation in test duration for each iteration is significant, an additional test may be required compared to another equivalence test with twenty pilot trials yielding an answer within the same time frame. Alternatively, instead of an individual time estimate, a test time period or a probability curve can also be specified. Similarly, certain resources may be selectively available, utilized, and/or required during an equivalence test. A resource and/or time range can be specified to indicate the fluctuating availability of a particular resource for an equivalence test.

8th 8 shows the resource allocation component 800 of the equivalence determination according to embodiments of the present disclosure. In one embodiment, a more explicit resource allocation may be provided, e.g. B. to provide indicia of specific available/utilized resources for various locations along axis 708. For example, gauge 804 may indicate a particular available resource or resources. Indicator 802 may indicate one or more resources used in performing an equivalency operation. For example, a particular system may have a local machine with a shared processor can (e.g., run a low-priority process), cannot be shared (e.g., run a high-priority process), or can offload processing, e.g., to a server, server rack, server farm, or "cloud" , which includes many, often thousands, of high-performance servers.

The resource allocation component 800 of the equivalency determination may indicate the resources available for performing an equivalency determination. Accordingly, gauge 804 may be configured to indicate available processing elements and combinations, which may or may not be exclusive to a particular setting. For example, a single microprocessor performing a "high priority" task can also perform operations of a "low priority" task, but the allocation of another component, e.g. a "server" can deallocate a local processor. In other embodiments, the use of another component, e.g. a "server", and a local processor performs at least some of the operations. In other embodiments, the resource allocation component of the equivalence determination 800 allows a user to select which components from a pool of available components are used for the equivalence determination.

In another embodiment, the resource usage component 800 of the equivalency determination is an output that provides indicia of computational resources that are, can be, and/or have been executed to perform an equivalency determination.

9 9 shows the process 900 in accordance with embodiments of the present disclosure. In one embodiment, process 900 represents steps to be performed by one or more processors. Process 900 may be executed in whole or in part by a processor other than the processor(s) used to perform the equivalence determination (eg, step 924) of the steps of process 900. It should be understood that the steps of process 900 can be performed by a processor, such as a processor. B. the processor 106, a processor of a server, blade, core and/or other processing device. Virtual processors offer advantages, for example, by giving the appearance of a dedicated hardware component, although such components can be one of a variety of components, a shared component, or a changing hardware component, or by providing an interface that simulates a processor instruction set while the underlying underlying hardware component uses a different processor instruction set (e.g. an emulator). In certain embodiments described herein, the actual processor operations may make it appear that the software performs processor operations; however, the underlying hardware remains and ultimately performs the operations described herein.

In one embodiment, step 902 obtains an equivalence limit threshold. Step 902 can be performed, e.g. B. by the limitation component 700 of the equivalence determination, the resource allocation component 800 of the equivalence determination, the access to a data record in a memory or a data storage component and/or other input means. Step 904 performs one or more of sub-processes 906, 908, and 910 according to the input received in step 902. Threads 906, 908, and 910 may be executed in parallel or sequentially, depending on the implementation choice. Sub-process 906 is executed and step 912 determines whether the input received in step 902 represents a time constraint. If so, step 912 is executed to set a clock, countdown, timer, or other means by which processing (e.g., steps 924 and 926) may terminate when a timing condition occurs that is determined by the conditions defined in step 902 received input is displayed. Sub-process 908 is executed and step 916 determines whether the resource is limited by the input received in step 902, and if so, step 918 performs the allocation step. Step 918 may allocate resources, e.g. by signaling a monitoring resource to reserve use of monitored resources and/or deny access to foreign processes for the monitored resource during execution of at least a portion of process 900 (e.g., steps 924 and 926). Sub-process 910 is executed and step 920 determines whether process 900 is hypothesized ("HS") constrained, such that steps 924 are to be executed until a certain hypothesis strength of the result is determined.

In one embodiment, at least one of steps 912, 916, 920 is determined in the affirmative. If any of steps 912, 916, 920 is determined negatively, the next step (e.g. 914, 918 or 922) can be omitted. If one of the steps 912, 916, 920 is executed in succession, after the completion of one or more of the steps 912, 916, 920 an unexecuted step 912, 916, 920 can be executed.

In another embodiment, step 904 may resolve a conflict between two or more of threads 906, 908, and 910. For example, a user may enter a request to perform an equivalency determination using a specified processing resource, generate a 99.8% hypothesis strength, and stop after fifteen minutes. A processor, such as processor 106, may perform steps of process 900 and determine that the requested equivalency determination cannot be performed within the specified time limit to provide a result with the specified level of hypothesis strength. Accordingly, the process 900 may loop (not shown) back to step 902 to receive alternative input from the user. As can be imagined, the system performing process 900 may prompt the user to enter an achievable outcome in terms of time, hypothesis strength, and resources. Alternatively, the process 900 may continue until one of the conditions (see step 926) is met to prompt the user if the results are sufficient or if he should continue. For example, after a first threshold (eg, step 928 determines that fifteen minutes has elapsed), the user may be prompted to say, eg, “The fifteen minute time limit has been met with a hypothesis strength of 9.8%. End? Next?” and continue or end accordingly. Alternatively, the user may be prompted to approve and/or allocate additional processing resources, and/or an automatic resource allocation component may allocate processing resources to meet a hypothesis strength and/or time constraint.

Once constraints are known or become known (e.g., an interrupt), step 924 performs processing associated with determining equivalence. In one embodiment, the processing operations may be a series of iterations of a test, where a given input is provided to both a candidate source code and a preferred source code, and the outputs of both are then checked for equivalency, processor clock cycles, processor operations, FLOPs, etc. be rated. Additionally or alternatively, a conversion of one value into another can be provided and used (e.g. the number of iterations can be converted into processor cycles, etc.)

Next, in step 924, processing operations are performed by the selected/assigned processing resource. Step 926 determines whether processing step 924 should be aborted. Step 926 includes substeps 928, 930, and 932. In one embodiment, if any of sub-steps 928, 930, and 932 are true, processing is to be interrupted and process 900 proceeds to step 934. In another embodiment, if all of sub-steps 928, 930, and 932 are determined negatively, process 900 continues and proceeds to step 924. Step 928 includes step 928 determining whether a time limit has been reached, such as a time limit. B. a time, duration, etc., which was determined in step 914. Step 928 includes step 930 determining whether the equivalence failed, i.e., an operation of step 924 determined that a candidate source code and a preferred source code, when provided with equivalent inputs, do not produce equivalent outputs. Step 928 includes step 932 which determines whether a certain hypothesis strength ("HS") as determined in step 922 has been met. Step 934 is then executed, in which equivalence or lack of equivalence is indicated if step 930 is affirmative. Optionally, in step 934, a substitution operation can be performed, in which the preferred source code replaces the candidate source code.

the 10-71 show a solution according to the embodiments of the present disclosure. 10 FIG. 12 shows at least part of an overview of a problem and a solution according to embodiments of the present disclosure. 11 FIG. 12 shows at least part of another overview of solved problems according to embodiments of the present disclosure. 12 10 shows at least a portion of a target according to embodiments of the present disclosure. 13 12 shows at least a portion of an analogy in accordance with embodiments of the present disclosure. 14 FIG. 12 shows at least part of an additional overview section according to embodiments of the present disclosure. 15 12 shows at least a portion of an additional overview section according to embodiments of the present disclosure.

16 shows at least part of the in the 10-71 solution shown having a code 1602 with a function 1604, a function 1606, a function 1608 and a function 1610. 17 shows at least part of the in the 10-71 solution shown, which has code 1602 with function 1604, function 1606, function 1608 and function 1610. Function 1604 and function 1610 are highlighted. 18 shows at least part of the in the 10-71 solution shown, which has code 1602 with function 1604, function 1606, function 1608 and function 1610. Function 1604 and function 1610 are highlighted. 19A shows at least part of the in the 10-71 solution shown, which has code 1602 with functions 1604, 1606, 1608, and 1610. Function 1604 and function 1610 are highlighted.

the 19B , 20 , 27 each show at least part of the in the 10-71 solution shown and each have the code 1902 with the function 1604 and the function 1610. 19 will through 19A showing the left part of 19 represents, and 19B showing the right part of 19 represents, illustrates. 20 shows at least part of the in the 10-71 solution shown having function 1606, function 1608 and function 1610.

21 shows at least part of the in the 10-71 shown solution. 21 shows at least part of the in the 10-71 shown solution. 22 shows at least part of the in the 10-71 shown solution. 23 shows at least part of the in the 10-71 shown solution. 24 shows at least part of the in the 10-71 shown solution. 24 shows at least part of the in the 10-71 shown solution. 25 shows at least part of the in the 10-71 shown solution. 26 shows at least part of the in the 10-71 shown solution. 27 shows at least part of the in the 10-71 solution shown, comprising source code 1902, function 1604, and function 1610. 28 shows at least part of the in the 10-71 solution shown having source code 1902, function 1604 and function 1610. 29 shows at least part of the in the 10-71 shown solution. 30 shows at least part of the in the 10-71 shown solution. 31 shows at least part of the in the 10-71 shown solution.

32 shows at least part of the in the 10-71 solution shown, which has the code 3202.

33 is through 33A showing the left part of 33 shows and 33B showing the right part of 33 shows, represented. 33A shows at least part of the in the 10-71 solution shown, which has code 3302. 34 will through 34A showing the left part of 34 shows and 34B showing the right part of 34 shows, illustrates. 35 is through 35A showing the left part of 35 indicates, 35B , which is the middle part of 35 shows and 35C showing the right part of 35 shows, represented. 35C shows at least part of the in the 10-71 solution shown, which has functions 3502, 3504, and 3506. 36 shows at least part of the in the 10-71 shown solution. 37 shows at least part of the in the 10-71 shown solution. 38 shows at least part of the in the 10-71 shown solution. 39 shows at least part of the in the 10-71 shown solution. 40 shows at least part of the in the 10-71 solution shown, which has the function 3502, the function 4002 and the function 4004.

41 shows at least part of the in the 10-71 solution shown, which has the function 3502, the function 3508 and the function 3510. 42 shows at least part of the in the 10-71 solution shown, which has functions 3502, 3508, and 3510, respectively. 43 shows at least part of the in the 10-71 solution shown, which has functions 3502 and 3510.

44 shows at least part of the in the 10-71 shown solution. 45 shows at least part of the in the 10-71 shown solution. 46 shows at least part of the in the 10-71 shown solution. 47 shows at least part of the in the 10-71 shown solution. 48 shows at least part of the in the 10-71 shown solution. 49 shows at least part of the in the 10-71 shown solution. 50 shows at least part of the in the 10-71 shown solution. 51 shows at least part of the in the 10-71 shown solution and is carried out by 51A showing the left part of 51 shows and 51B showing the right part of 51 shows, illustrates. 52 shows at least part of the in the 10-71 shown solution. 50 shows at least part of the in the 10-71 shown solution. 53 shows at least part of the in the 10-71 solution shown, which has the function 3202

54 will through 54A showing the left part of 54 indicates, 54B , which is the middle part of 54 shows and 54C showing the right part of 54 shows, represented. 54A shows at least part of the in the 10-71 solution shown, which has code 3502, functions 3502, function 4002 and function 4004. 54B shows at least part of the in the 10-71 solution shown, which has functions 5402, 5404, and 5406. 54C shows at least part of the in the 10-71 solution shown, which has functions 5408, 5410, 5412, 5414, and 5416.

55 shows at least part of the in the 10-71 solution shown, which has functions 5502, 5404, 5406, and 5408. 56 shows at least part of the in the 10-71 shown solution. 57 shows at least part of the in the 10-71 shown solution. 58 shows at least part of the in the 10-71 shown solution. 59 shows at least part of the in the 10-71 shown solution. 59 shows at least part of the in the 10-71 shown solution.

60B shows at least part of the in the 10-71 solution shown, which has code 1602 with function 1604, function 1606, function 1608 and function 1610. Function 1604 and function 1610 are highlighted. 60C shows at least part of the in the 10-71 solution shown, which has the function 6002. 60 is through 60A shown showing an upper part of 60 illustrated, and the lower part of 60 is through 60B shown showing the lower left part of 60 illustrated, and 60C , which is the lower right part of 60 illustrated.

61 shows at least part of the in the 10-71 shown solution. 62 shows at least part of the in the 10-71 solution shown, which has the interaction 6202. 62 will through 62A illustrates showing the left part of 62 illustrated, 62B showing the right part of 62 illustrated.

63 shows at least part of the in the 10-71 solution shown having code 3502 and function 5402, function 5404, function 5406, function 5408, function 5410, function 5412, function 5414, and function 5416. 63 shows at least part of the in the 10-71 shown solution and is carried out by 63A showing the left part of 63 indicates, 63B showing the upper right part of 63 shows and 63C , which is the lower right part of 63 shows, represented.

64 shows at least part of the in the 10-71 shown solution. 65 shows at least part of the in the 10-71 shown solution. 66 shows at least part of the in the 10-71 shown solution. 67 shows at least part of the in the 10-71 shown solution.

68 shows at least part of the in the 10-71 solution shown, which has code 3502 and interaction 6202. 69 shows at least part of the in the 10-71 shown solution. 69 will through 69A shown showing the left part of 69 illustrated, and 69B showing the right part of 69 illustrated. 70 shows at least part of the in the 10-71 shown solution. 71 shows at least part of the in the 10-71 shown solution.

• Verfahren, das Folgendes aufweist:
  • Abrufen eines Kandidaten-Quellcodes, der eine Kandidatenfunktion aufweist und eine erste menschenlesbare Maschinenanweisung aufweist, durch einen Prozessor aus einem Datenspeicher;
  • Zugreifen des Prozessors aus dem Datenspeicher auf eine Vorzugsfunktion, die eine zweite menschenlesbare Maschinenanweisung umfasst und zuvor als autorisierter Quellcode identifiziert wurde;
  • Zugreifen des Prozessors auf einen Schwellenwert für die Äquivalenzbegrenzung;
  • automatisches Bestimmen der Äquivalenz zwischen der Kandidatenfunktion und der Vorzugsfunktion durch den Prozessor, wobei der Prozessor eine Vielzahl von Verarbeitungsoperationen ausführt, die die Bestimmung der Äquivalenz zwischen der Kandidatenfunktion und der Vorzugsfunktion aufweisen, bis der Schwellenwert für die Äquivalenzbegrenzung erreicht ist;
  • bei Feststellung der Äquivalenz, automatisches Bereitstellen von Äquivalenzindikatoren durch den Prozessor, die mit der Kandidatenfunktion und der Vorzugsfunktion verbunden sind;
  • bei Vorliegen der Indizien automatische Umwandlung des Kandidaten-Quellcodes durch den Prozessor, wobei die Kandidatenfunktion durch die Vorzugsfunktion ersetzt wird; und
  • die Ausgabe des transformierten Kandidaten-Quellcodes.
• Wobei der Schwellenwert für die Äquivalenzbegrenzung mindestens eines der folgenden Elemente aufweist: Niveau der Hypothesenstärke, Anzahl der Verarbeitungsvorgänge, die erforderlich sind, um das Niveau der Hypothesenstärke zu erreichen, Taktzeit, Prozessorzyklen, Verarbeitungsressourcen, die die Verarbeitungsvorgänge zusätzlich zum Prozessor durchführen, und Verarbeitungsressourcen, die die Verarbeitungsvorgänge ohne den Prozessor durchführen.
• Wobei die Vorzugsfunktion menschenlesbare Elemente aufweist, die nicht mit der zweiten menschenlesbaren Maschinenanweisung verbunden sind.
• Wobei der Schritt der Bestimmung der Äquivalenz fehlschlägt, wenn festgestellt wird, dass eine Anzahl von Eingabe-/Ausgabeparametern zwischen der Kandidatenfunktion und der Vorzugsfunktion unterschiedlich ist.
• Wobei der Schritt der Bestimmung der Äquivalenz fehlschlägt, wenn:
  • bestimmt wird, dass mindestens eines Eingabe-/Ausgabeparameter sich zwischen der Kandidatenfunktion und der Vorzugsfunktion unterscheidet; und
  • wobei die Differenz eine Differenz von Äquivalenzklassen aufweist.
• Bereitstellen einer ersten maschinenlesbaren Übersetzung der Kandidatenfunktion;
• Bereitstellen einer zweiten maschinenlesbaren Übersetzung der Vorzugsfunktion;
• Ausführen sowohl der ersten maschinenlesbaren Übersetzung als auch der zweiten maschinenlesbaren Übersetzung mit Eingaben aus einem endlichen Satz von Eingaben; und
• Bestimmen der Äquivalenz nach dem Schritt des Ausführens sowohl der ersten maschinenlesbaren Übersetzung als auch der zweiten maschinenlesbaren Übersetzung, die jeweils äquivalente Werte von jeder der ersten maschinenlesbaren Übersetzung und der zweiten maschinenlesbaren Übersetzung der Kandidatenfunktion ausgeben.
• Wobei der Schritt des Bestimmens der Äquivalenz weiterhin aufweist:
  • Ableiten einer logischen Gleichung für die Kandidatenfunktion;
  • Zugreifen auf eine logische Gleichung für die Vorzugsfunktion; und
  • wobei die Äquivalenz nicht festgestellt wird, wenn festgestellt wird, dass die logische Gleichung für die Kandidatenfunktion sich von der logischen Gleichung für die Vorzugsfunktion unterscheidet.
• Wobei die Bestimmung, ob die logische Gleichung der Kandidatenfunktion als äquivalent zu der logischen Gleichung der Vorzugsfunktion bestimmt wird, ferner aufweist:
  • Bereitstellen der logischen Gleichung für die Kandidatenfunktion und der logischen Gleichung für die Vorzugsfunktion für einen automatischen Theorembeweiser; und
  • Empfang von Indizien aus dem automatischen Theorembeweiser, die die Äquivalenz anzeigen.
• Wobei die Vorzugsfunktion eine Gruppe von Anweisungen aufweist, die, wenn sie in Maschinencode umgewandelt werden, eine Maschine veranlassen, die Vorzugsfunktion auf eine zuvor bestimmte optimale Weise auszuführen.
• Wobei die zuvor bestimmte optimale Art und Weise eine bestimmte Art und Weise aufweist, die mit mindestens einem Sicherheitsziel übereinstimmt.
• Wobei die Maschine einen Prozessor aufweist und die zuvor bestimmte optimale Art und Weise eine bestimmte Anzahl von Prozessoroperationen aufweist.
• Wobei die Maschine einen Speicher aufweist und die zuvor bestimmte optimale Art und Weise eine bestimmte Größe des Speichers aufweist, die zum Speichern des Maschinencodes erforderlich ist.
• Wobei die Vorzugsfunktion eine Gruppe von Anweisungen aufweist, die zuvor als prägnanter Quellcode identifiziert wurden.
• Wobei der Schritt des Bestimmens der Äquivalenz weiterhin aufweist:
  • Erzeugen einer Gruppe von Äquivalenzklassen für die Kandidatenfunktion aus der Kandidatenfunktion, wobei die Äquivalenzklassen eine Gruppe von äquivalenten Funktionen aufweisen und jedes Element der Gruppe eine Funktion-zu-Quelle-Zuordnung hat.
• Wobei die Vorzugsfunktion ein prägnantestes Element aufweist, das gemäß einer abstrakten syntaktischen Strukturbestimmung der Äquivalenz zwischen der Kandidatenfunktion und der Vorzugsfunktion ausgewählt wird.
• Wobei die abstrakte syntaktische Struktur einen abstrakten Syntaxbaum (AST) aufweist.
• System, aufweisend:
  • einen Prozessor, der außerdem einen Speicher und eine erste Kommunikationsschnittstelle aufweist;
  • einen Datenspeicher, wobei der Datenspeicher eine zweite zugängliche Kommunikationsschnittstelle aufweist;
  • der Prozessor:
    • über die erste und zweite Kommunikationsschnittstelle einen Kandidaten-Quellcode abruft, der eine Kandidatenfunktion hat und eine erste menschenlesbare Maschinenanweisung enthält;
    • auf eine Vorzugsfunktion zugreift, die eine zweite menschenlesbare Maschinenanweisung aufweist und zuvor als autorisierter Quellcode identifiziert wurde;
    • auf einen Schwellenwert für die Äquivalenzbegrenzung zugreift;
    • die Äquivalenz zwischen der Kandidatenfunktion und der Vorzugsfunktion bestimmt, wobei der Prozessor eine Vielzahl von Verarbeitungsoperationen ausführt, die die Bestimmung der Äquivalenz zwischen der Kandidatenfunktion und der Vorzugsfunktion aufweisen, bis der Schwellenwert für die Äquivalenzbegrenzung erreicht ist,
    • bei festgestellter Äquivalenz, Äquivalenzkennzeichen für die Kandidatenfunktion und die Vorzugsfunktion erstellt und bereitstellt;
    • bei Bereitstellen der Indizien, den Kandidaten-Quellcode umwandelt, wobei auch die Kandidatenfunktion durch die Vorzugsfunktion ersetzt wird; und
    • den transformierten Kandidaten-Quellcodes über die erste Kommunikationsschnittstelle ausgibt.
• Nicht-flüchtiges computerlesbares Medium mit darauf befindlichen Anweisungen, die, wenn sie von einem Computer ausgeführt werden, den Computer dazu veranlassen:
  • aus einem Datenspeicher einen Kandidaten-Quellcode abzurufen, der eine Kandidatenfunktion hat und eine erste menschenlesbare Maschinenanweisung enthält;
  • aus dem Datenspeicher auf eine Vorzugsfunktion zuzugreifen, die eine zweite menschenlesbare Maschinenanweisung umfasst und zuvor als autorisierter Quellcode identifiziert wurde;
  • auf einen Schwellenwert für die Äquivalenzbegrenzung zuzugreifen;
  • Äquivalenz zwischen der Kandidatenfunktion und der Vorzugsfunktion durch Ausführen einer Vielzahl von Verarbeitungsoperationen automatisch zu bestimmen, was die Bestimmung der Äquivalenz zwischen der Kandidatenfunktion und der Vorzugsfunktion aufweist, bis der Schwellenwert für die Äquivalenzbegrenzung erreicht ist;
  • bei Feststellung der Äquivalenz, Äquivalenzindikatoren durch den Prozessor automatisch bereitzustellen, die mit der Kandidatenfunktion und der Vorzugsfunktion verbunden sind;
  • bei Vorliegen der Indizien, den Kandidaten-Quellcodes durch den Prozessor automatisch umzuwandeln, wobei die Kandidatenfunktion durch die Vorzugsfunktion ersetzt wird; und
  • den transformierten Kandidaten-Quellcode auszugeben.

The following aspects are also disclosed:

• A method that includes:
  • retrieving, by a processor, from a data store, candidate source code having a candidate function and having a first human-readable machine instruction;
  • the processor accessing from the data store a preference function comprising a second human-readable machine instruction previously identified as authorized source code;
  • accessing the processor to an equivalence constraint threshold;
  • the processor automatically determining the equivalence between the candidate function and the preferred function, the processor performing a plurality of processing operations including determining the equivalence between the candidate function and the preferred function until the equivalence constraint threshold is met;
  • upon determination of equivalence, the processor automatically providing equivalence indicators associated with the candidate function and the preferred function;
  • upon the presence of the indicia, the processor automatically converting the candidate source code, replacing the candidate function with the preferred function; and
  • the output of the transformed candidate source code.
• Where the equivalence constraint threshold comprises at least one of the following: hypothesis strength level, number of processing operations required to reach the hypothesis strength level, clock time, processor cycles, processing resources required by the perform processing operations in addition to the processor, and processing resources that perform the processing operations without the processor.
• Wherein the preference function comprises human-readable elements that are not associated with the second human-readable machine instruction.
• Wherein the step of determining equivalence fails if it is determined that a number of input/output parameters differ between the candidate function and the preferred function.
• Where the step of determining equivalence fails if:
  • determining that at least one input/output parameter differs between the candidate function and the preferred function; and
  • where the difference has a difference of equivalence classes.
• providing a first machine-readable translation of the candidate function;
• providing a second machine-readable translation of the preference function;
• performing both the first machine-readable translation and the second machine-readable translation with inputs from a finite set of inputs; and
• determining equivalence after the step of performing both the first machine-readable translation and the second machine-readable translation that each output equivalent values of each of the first machine-readable translation and the second machine-readable translation of the candidate function.
• Wherein the step of determining equivalence further comprises:
  • deriving a logical equation for the candidate function;
  • accessing a logical equation for the preference function; and
  • wherein equivalence is not determined if the logical equation for the candidate function is determined to be different from the logical equation for the preferred function.
• Wherein determining whether the logical equation of the candidate function is determined to be equivalent to the logical equation of the preference function further comprises:
  • providing the logical equation for the candidate function and the logical equation for the preferred function to an automatic theorem prover; and
  • Receiving evidence from the automatic theorem prover indicating equivalence.
• Where the preference function comprises a set of instructions which, when converted to machine code, cause a machine to execute the preference function in a predetermined optimal manner.
• Wherein the previously determined optimal manner comprises a determined manner that conforms to at least one security objective.
• Wherein the machine has a processor and the predetermined optimal manner has a certain number of processor operations.
• Wherein the machine has memory and the predetermined optimal way has a certain amount of memory required to store the machine code.
• Where the preference function comprises a set of instructions previously identified as concise source code.
• Wherein the step of determining equivalence further comprises:
  • generating a set of equivalence classes for the candidate function from the candidate function, the equivalence classes comprising a set of equivalent functions and each member of the set having a function-to-source mapping.
• Wherein the preference function has a most succinct element that is selected according to an abstract syntactic structure determination of the equivalence between the candidate function and the preference function.
• Where the abstract syntactic structure comprises an abstract syntax tree (AST).
• system comprising:
  • a processor also having a memory and a first communication interface;
  • a data store, the data store having a second accessible communication interface;
  • the processor:
    • retrieves, via the first and second communication interfaces, candidate source code having a candidate function and including a first human-readable machine instruction;
    • accesses a preferred function having a second human-readable machine instruction and previously identified as authorized source code;
    • accesses an equivalence limit threshold;
    • determining the equivalence between the candidate function and the preferred function, wherein the processor performs a plurality of processing operations comprising determining the equivalence between the candidate function and the preferred function until the equivalence constraint threshold is reached,
    • if equivalence is determined, creates and provides equivalence identifiers for the candidate function and the preferred function;
    • upon providing the indicia, converting the candidate source code, also replacing the candidate function with the preferred function; and
    • outputs the transformed candidate source codes via the first communication interface.
• A non-transitory computer-readable medium bearing instructions that, when executed by a computer, cause the computer to:
  • retrieve from a data store candidate source code having a candidate function and including a first human-readable machine instruction;
  • access from the data store a preferred function comprising a second human-readable machine instruction previously identified as authorized source code;
  • access an equivalence limit threshold;
  • automatically determining equivalence between the candidate function and the preferred function by performing a plurality of processing operations, including determining equivalence between the candidate function and the preferred function, until the equivalence constraint threshold is reached;
  • upon determination of equivalence, the processor automatically providing equivalence indicators associated with the candidate function and the preferred function;
  • upon the presence of the indicia, automatically converting, by the processor, the candidate source code, replacing the candidate function with the preferred function; and
  • output the transformed candidate source code.

In addition to the above, other embodiments within the embodiments disclosed herein are also contemplated. For example, a feature may be a preferred feature based on comments (e.g. internal documentation). In another embodiment, a function may be preferred if it is tested and approved and therefore a known function as opposed to an untested and/or unapproved and therefore unknown function.

In the foregoing description, the methods have been described in a particular order for purposes of illustration. It should be noted that, in alternative embodiments, the methods may be performed out of the order noted. It should also be noted that the methods described above may be executed by hardware components or embodied in sequences of machine-executable instructions that may be used to execute a machine, such as a computer. B. an electrical circuit executed as a general purpose or special purpose processor (GPU or CPU), or logic circuits programmed with the instructions are to cause the methods to be executed (FPGA). The machine has and/or accesses components for storing data and/or instructions via an electrical and/or optical communication interface. These machine-executable instructions may be stored on one or more machine-readable media, such as CD-ROMs or other types of optical disks, floppy disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, flash memories, or other types of machine-readable media that suitable for storing electronic instructions. Alternatively, the methods can also be performed by a combination of hardware and software.

Specific details are provided in the description to provide a thorough understanding of the embodiments. However, one skilled in the art will appreciate that the embodiments may be practiced without these specific details. For example, circuits may be represented in block diagram form in order not to obscure the embodiments with unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

It is also noted that the embodiments have been described as a process represented as a flowchart, flowchart, data flow diagram, structural diagram, or block diagram. Although a flowchart can describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations can be rearranged. A process is complete when its operations are complete, but may have additional steps not included in the figure. A process can correspond to a method, function, procedure, sub-program, sub-program, and so on. When a process corresponds to a function, its termination corresponds to the function's return to the calling function or to the main function.

Additionally, the systems, methods, and protocols may be implemented using one or more special purpose computers, a programmed microprocessor or microcontroller and peripheral integrated circuit elements, an ASIC or other integrated circuit, a digital signal processor, a hardwired electronic or logic circuit such as a circuit with discrete elements, a programmable logic device such as PLD, PLA, FPGA, PAL, a modem, a transceiver, a comparable means, or the like. In general, any device capable of implementing a state machine capable of implementing the methodology presented herein may benefit from the various communication methods, protocols, and techniques consistent with the disclosure presented herein.

Examples of the processors described herein may include at least one of the following processors: Qualcomm® Snapdragon® 800 and 801, Qualcomm® Snapdragon® 610 and 615 with 4G LTE integration and 64-bit computing, Apple® A7 processor with 64-bit architecture, Apple® M7 motion coprocessors but not only, Samsung® Exynos® series, the Intel® Core™ processor family, the Intel® Xeon® processor family, the Intel® Atom™ processor family, the Intel Itanium® processor family, Intel® Core® i5-4670K and i7-4770K 22nm Haswell, Intel® Core® i5-3570K 22nm Ivy Bridge, the AMD@ FX™ processor family, AMD® FX-4300, FX-6300 and FX-8350 32nm Vishera, AMD® Kaveri processors , Texas Instruments® Jacinto C6000™ automotive infotainment processors, Texas Instruments® OMAP™ automotive-grade mobile processors, ARM® Cortex™-M processors, ARM® Cortex-A and ARM926EJ-S™ processors, Broadcom® AirForce BCM4704/BCM4703 processors for wireless networks, the AR7100 Wireless Network Processing Unit their industry-equivalent processors, and may perform computational functions using any known or hereafter developed standard, instruction set, library, and/or architecture.

Furthermore, the disclosed methods are easily implemented in software using objects of an object-oriented software language that provide portable source code that can be used on a variety of computer or workstation platforms. Alternatively, the disclosed system can be implemented partially or entirely in hardware using standard logic circuits or VLSI designs. Whether software or hardware is used to implement the systems according to embodiments depends on the speed and/or efficiency requirements of the system, the particular function, and the particular software or hardware systems or microprocessor or microcomputer systems being used. The communication systems, methods and protocols presented here can be used by persons skilled in the art who are familiar with the functional description given here and who have a general basic knowledge of computer and telecommunications technology, can be readily implemented in hardware and/or software using known or hereafter developed systems or structures, devices and/or software.

Furthermore, the disclosed methods can be readily implemented in software and/or firmware, which can be stored on a storage medium to improve the performance of a programmed general purpose computer in cooperation with a controller and memory, a special purpose computer, a microprocessor or the like. In these cases, the systems and methods may be implemented as an embedded program on a personal computer, such as an B. an applet, JAVA.RTM. or CGI script, as a resource resident on a server or computer workstation, as a routine embedded in a dedicated communications system or system component, or the like. to be implemented. The system can also be implemented by physically integrating the system and/or method with a software and/or hardware system, such as the hardware and software systems of a communications transceiver.

Various embodiments may also or alternatively be implemented in software and/or firmware in whole or in part. This software and/or firmware may take the form of instructions embodied in or on a non-transitory computer-readable storage medium. These instructions can then be read and executed by one or more processors to enable the operations described herein to be performed. The instructions can be in any suitable form, such as B. source code, compiled code, interpreted code, executable code, static code, dynamic code and the like. Such computer-readable medium may include any tangible, non-transitory medium for storing information in a form readable by one or more computers, such as, but not limited to, read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory, etc.

Example systems and methods for machining instructions are presented here. While the embodiments have been described in connection with a number of embodiments, it is evident that many alternatives, modifications and variations are or would be apparent to those skilled in the applicable arts. Accordingly, this disclosure is intended to embrace all such alternatives, modifications, equivalents, and variances that fall within the spirit and scope of this disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US2016017160PCT[0005]
• WO 2016/130551 [0005]

Claims (15)

Processor configured to execute a method comprising the following steps: retrieving candidate source code having a candidate function from a data store; accessing a surrogate function from the data store; accessing a hypothesis strength level and a resource constraint, the hypothesis strength level being determined by successfully completing a number of equivalency evaluations; automatically determining the equivalence between the candidate function and the replacement function, wherein the processor performs the number of equivalence evaluations by running inputs through a plurality of processing operations and comparing the corresponding outputs until either the hypothesis strength level or the resource limit is reached; if equivalence is determined by reaching the hypothesis strength level, automatically providing indicia of equivalence associated with the candidate function and the surrogate function; if the indicia are provided, automatically transforming the candidate source code, comprising replacing the candidate function with the replacement function; outputting the modified candidate source code; and Store or otherwise make available the modified source code for future access and/or processing. processor after claim 1 , where the resource constraint is at least one of the following: number of operations required to reach the hypothesis strength level, clock time, processor cycles, processing resources that perform the operations in addition to the processor, and processing resources that perform the operations exclusive to the processor carry out. The processor of any preceding claim, wherein the step of determining equivalence fails if it is determined that a number of input/output parameters differ between the candidate function and the replacement function. A processor as claimed in any preceding claim, wherein the step of determining equivalence fails if: determining that at least one input/output parameter differs between the candidate function and the replacement function; and where the difference has a difference of equivalence classes. A processor as claimed in any preceding claim, the method further comprising the steps of: providing a first machine-readable translation of the candidate function; providing a second machine-readable translation of the replacement function; performing both the first machine-readable translation and the second machine-readable translation with inputs from a finite set of inputs; and determining the equivalence when both the first machine-readable translation and the second machine-readable translation are performed, respectively outputting equivalent values of each of the first machine-readable translation and the second machine-readable translation of the candidate function. The processor of any preceding claim, wherein the method further comprises the step of requesting a new resource limit if the resource limit has been reached prior to the hypothesis strength level. The processor of any preceding claim, wherein the surrogate function comprises a set of instructions which, when converted to machine code, cause a machine to execute the surrogate function in a predeterminable optimal manner. processor after claim 7 , wherein the previously determined optimal manner comprises a determined manner that conforms to at least one security objective. processor after claim 7 , where the previously determined optimal way has a certain number of processor operations of the processor. processor after claim 7 , wherein the machine has a memory and the predetermined optimal way has a certain amount of memory required to store the machine code. A processor as claimed in any preceding claim, wherein the replacement function comprises a set of instructions previously identified as concise source code. The processor of any preceding claim, wherein the step of the method of determining equivalency further comprises: generating from the candidate function a set of equivalence classes for the candidate function, the equivalence classes comprising a set of equivalent functions, each member of the set comprising a function-to-source mapping. system comprising: a processor according to any one of the preceding claims, the processor further comprising a memory and a first communication interface; and a data memory, the data memory having a second communication interface. A non-transitory computer-readable medium having instructions thereon that, when executed by the processor, cause the processor to perform the steps of any of Claims 1 until 12 carry out the mentioned procedure. Machine that has a processor according to one of the Claims 1 until 12 having.

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