DE202011101272U1 - Device for controlling an LED arrangement - Google Patents

Abstract

Device for controlling an LED arrangement in the form of a driver circuit, characterized by a driver module (1) and a processor (2) connected to the driver module in a command / feedback circuit, the driver module comprising a total of controllers (3) connected in parallel A control circuit with at least one LED (4) and one energy detection unit (5) is assigned to each controller.

Description

The invention relates to a device for controlling a LED arrangement according to the preamble of claim 1.

To drive a set of light-emitting diodes, hereinafter referred to as LED, driver circuits are commonly used. These control the power of the LED by controlling the current flowing through one or more series-connected LEDs. The operating voltage required for the power consumption of the LED or the series-connected LED string results from the multiplication of a forward voltage of the individual LED by the number of LEDs in the string. The LED current is converted by a resistor into a voltage. This is constantly regulated to a predetermined value. The power supply is usually a switching regulator. This is based on different topologies and in particular acts as either an up or a down converter. In many applications, there is the case that the input voltage of the regulator is lower than the operating voltage of the LED string and therefore must be increased. To increase the regulator's input voltage to the LED string voltage, the boost converter topology is used. Their efficiency is the lower, the higher the ratio between the input voltage and the voltage of the LED string.

It is therefore the object to provide a device for controlling a LED array, with the disadvantages described can be sustainably reduced and eliminated. In particular, the device sought should be less susceptible to external interference signals and provide the user with additional degrees of freedom for the design of the LED circuit.

The object is achieved with a device for controlling a LED arrangement with the features of claim 1. The dependent claims contain expedient and / or advantageous embodiments of the modulation device.

The object is achieved with a device for controlling an LED arrangement in the form of a driver circuit. This is characterized according to the features of claim 1 by a driver module and a processor connected to the driver module in a command / feedback circuit. The driver module comprises a set of regulators connected in parallel, wherein in each case one controller is assigned a control circuit with at least one LED and one energy detection unit.

According to the invention, it is therefore assumed that there is a whole of LEDs which are not connected in series in a single LED string, but in parallel. Each individual LED is connected in its own control loop. This includes the LED itself, an energy detection unit and a controller, which takes over the control of the LED. Each different controllers are combined to form a driver module. This driver module is coupled to a processor via a command / feedback circuit.

An essential advantage of such an arrangement is that the parallel connection offers an additional degree of freedom in LED application development. Individual power consumption of individual LEDs can thus be specifically detected and controlled separately from the rest of the LED and controlled.

In an advantageous embodiment, the energy detection unit is designed as a shunt resistor, wherein the controller has an integrator for a time-integrating measurement of a voltage drop across the shunt resistor. This circuit does not detect the instantaneous current, but the amount of charge that has flowed through the LED or the LED group within a certain time unit.

In this device, it is possible to use a comparatively small shunt resistor. This reduces the power loss at the resistor. Furthermore, the use of the integrator reduces the bandwidth of the control loop. The integrator acts as a low-pass filter that shields external interference from the control loop.

The controller has an internal threshold and a shutdown unit for switching off the LED when the threshold value is exceeded. The driver module includes a generating unit for generating a periodic pulsed operating voltage having a predetermined pulse duration, the pulse duration corresponding to a maximum integration interval of the integrator.

In an expedient embodiment, the processor is coupled to an optical power measurement unit of the LED. As a result, the operating state of the LED is detected not only on their power consumption, but also on their emitted radiation power.

In a particularly expedient embodiment, the driver module is designed in the form of an application-specific integrated circuit (ASIC). It contains a module for an SPI communication, a controller module containing the parallel controllers, a clock generator module and a Current drive module. The SPI communication module provides an interface for external configuration of the ASIC. The controller module is used to control the LED. The clock generator module provides a basic clock for individual measurement frames and the mentioned time integration intervals. The current driver module enables connection of additional I / O modules to the ASIC and their operation with an adjustable constant current.

Conveniently, the controller module contains a frame register. Using the frame register, a temporal specification of individual measurement frames is possible. Furthermore, a pulse duration register for specifying the pulse duration and / or a duty cycle within a measurement frame is contained within the regulator module. Moreover, it is also possible to include a threshold value register contained in the controller module via which the internal threshold value can be set.

Conveniently, the clock generator module includes a clock mode register, with which a pulse mode can be optionally specified. In this case, in particular the choice is possible between a pulse mode with a fixed pulse width with a variable pulse period or a pulse mode in which a pulse-width-modulated signal is generated. As a result, the timing of the driver module eats adapt to the design of the measurement frame of the individual controller modules.

The current driver module expediently contains at least two independent current drivers, wherein a current driver register is provided for presetting a current value. Thus, a current value can be externally set via the current driver register with which the peripherally arranged components can be charged.

The device for controlling a LED arrangement will be explained in more detail below with reference to exemplary embodiments. The same reference numbers are used for identical or equivalent parts.

It shows:

1 an exemplary block diagram with a representation of the device underlying switching principle,

2 an exemplary block diagram of an ASIC for hardware implementation of the device according to the invention,

3 an exemplary application circuit of the device according to the invention,

4 exemplary current-time and voltage-time diagrams for explaining the executed LED modulation,

5 exemplary representations of the basic pulse modes based on voltage-time diagrams.

1 shows an exemplary block diagram illustrating the switching principle of the device.

The modulation device is as a driver module 1 educated. The driver module interacts with a processor 2 together and is connected to this bidirectional. The processor is either executed as part of a computer, in particular a PC, or forms a self-sufficient controller as a microcontroller.

The driver module 1 contains several controller modules 3 , Each of the controller modules controls an LED channel. The respective LED channel contains at least one LED 4 and and is connected to the associated regulator module via energy detection unit 5 connected together. In the following embodiments, the energy detection unit includes a shunt resistor 6 above which a voltage and / or current value is tapped and an integrator 7 in each of the rule modules 3 which integrates the voltage value measured at the shunt resistor over a time interval. In this integration, not the current flow in the LED as such, but is detected within a certain time flowed through the respective LED charge amount, which is in the form of a time-varying voltage value at the integrator. If this value exceeds a predetermined size, the corresponding LED channel is switched off. The LEDs are operated in a controlled duty cycle, which is specified either individually for each channel or for all channels together.

Compared to standard technology, a shunt resistor whose resistance value is significantly lower can be used with this arrangement. As a result, the power loss occurring at the current measuring resistor is significantly reduced and the efficiency of the system is further increased. This is particularly important when application-related high load currents are driven, which are associated with high power losses.

The reduction of the shunt resistance also leads to a reduction in the regulated voltage drop across the resistor. This increases the sensitivity of the driver module to external noise and switching, reducing the signal-to-noise ratio of the controllers, thereby compromising the functionality of the control circuitry. By using the integrator, which is functional has a certain low-pass characteristic and thus acts as a filter and thereby reduces the bandwidth within the control loop, this effect can not only counteract, but the insensitivity of the modulation against external disturbances are even increased.

The modulation of the LEDs is time-discrete. The time base used here is a time interval whose length may expediently be between 2 μs and 2 ms. The time base for the synchronization can be specified both by an internal, arranged within the controller itself, as well as by an external clock source.

The LED arrangement thus decouples control technology into individual parallel-connected LEDs, which are interconnected instead of a single LED strand. The parallel connection enables a Buck topology, in which down-converters can be used. It also allows the arrangement of many different LEDs in one entity. With the arrangement shown here, the different LED currents can be detected independently of each other metrologically and compensated for each LED.

The arrangement is supplemented by a device for optical power measurement 8th , This registers the radiant powers of the LED either as a whole or individually and outputs a measured value parameter derived therefrom as a signal to the processor. As a result, on the one hand, the power consumption of the LED is controlled, as well as their output optically detected.

A device for power supply 9 Provides the forward voltage for LEDs connected to the driver module. The power supply is from the processor 2 controllable. Thus, the forward voltage can be adapted to different LED configurations and / or responded to changes in operating conditions, such as heating.

2 shows an exemplary hardware implementation of the modulation device according to the invention by means of an application-specific integrated circuit (ASIC). In the present example, the ASIC 16 has parallel channels, in each of which one or more LEDs can be operated. If an LED is to be controlled as accurately as possible with regard to their brightness, their temperature and color temperature or their color location, assigning a channel to only one LED proves to be expedient. Such a control is, for example, in the field of display backlighting, ie the backlight for displays, into consideration, since the best possible temperature-independent brightness homogeneity over the entire surface of the display is desired. If, on the other hand, the LEDs are used for pure lighting tasks, in the sense of a lamp or a spotlight, in which the greatest possible luminous efficacy is required, it is not necessary to have particularly precise control of the individual LED. Here several LEDs can be connected in series and assigned to one channel, whereby 16 independent light sources can be controlled.

In the present example, the ASIC allows a parallel drive, which is designed in this example for sixteen high-power LEDs. Optionally, a controllable power supply is provided to maximize the duty cycle of the channels, if required. The light output of the LEDs can be kept constant regardless of temperature and aging. By another calibration, a homogeneous or defined light distribution for each required application can be achieved. Alternatively, as described, optical sensors may be associated by which the parameters of each channel can be continuously corrected. The independent controllability of the individual LED channels allows the realization of dynamic light profiles.

Another feature that can be realized by the ASIC is the possibility of addressing the individual channels out of phase with one another. Such a configuration is advantageous when an LED array is to be controlled, which converts a considerable amount of power, for example, 200 watts and more. A synchronous switching on of all LED channels thus forms a considerable load peak for the power supply. The phase-shifted control, in particular, allows the switch-on times of the individual channels to be defined and shifted in time relative to one another. The load peaks are damped or even eliminated. Furthermore, by the phase-shifted response flicker and possible interference in the overall picture of the LED can be reduced, because the different switching times of the LED gaps are avoided in both the flow of current and in the light emission.

A further advantageous possibility is to provide an individually adjustable frame time for each channel.

When using an optical sensor, a comprehensive optical feedback is possible with regard to the optical parameters of the brightness, the spectrum and / or the color location. In this way, all parameters, both electrical and optical, can be controlled. The electrical parameters are controlled via the ASIC and the optical parameters via the optical sensor. Since LEDs offer the possibility in multi-color systems, such as in the field of Stage technology, or other media such as video walls in particular to cover color spaces, the spectrum emitted by the LED is dependent on the current level, the temperature of the LED and their age. Together with the optical sensor, such moods can be readjusted via the independent channels of the ASIC.

The parallel control makes it possible to use the same power supply for LED channels, which are characterized by a similar forward voltage. This is especially the case when colored LED configurations are to be controlled, in which the LED to a color have a similar structure, with their forward voltage is virtually identical. In full color systems, which are operated independently of the number of LED channels, for example, in RGBW mode, in such a case, a maximum of four power supply modules are required, each associated with the R, G, B and W associated LED. The power supply modules can be controlled by means of built-in ASIC digital-to-analog converter.

The modulation by the module itself is independent of its actual topology or the topology of the power supply used for it. With the use of switched buck regulators, the so-called buck topology, LED applications with electrical efficiencies of more than 90% can be realized very easily. The integrated frequency generators can be used to clock the switching stages.

The ASIC is operated via an external microcontroller, which is coupled by means of an SPI bus system. Individual enable signals can also be used to operate several ASICs on the same bus in order to increase the number of controllable LED channels.

The ASIC incorporates a built-in quartzoscillator, programmable pulse width modulated PWM outputs, and an I²C interface, which will be discussed in more detail below. These serve, in particular, to control power drivers for fans, actuators and the like as well as to integrate digital sensors and / or electronic memories, in particular EEPROMS, into the system with which calibration data can be stored.

The ASIC consists of several independent functional modules. For operating the modules and for setting operating states, internal registers are provided which are assigned to the respective modules. The registers and modules conform to a naming convention stored in a header file of the ASIC. Using the header file, the names listed there are used when programming the ASIC.

In the present embodiment, the following modules are provided: A first module is in each case by a regulator module 9a given for an LED channel. The controller module contains a hardware implementation of the controller 3 in conjunction with the integrator 7 and a comparator 10 , The controllers of the individual controller modules each have inputs CTL0 to CTL15 with which control signals can be output to the circuit breaker. The integrators of the individual controller modules are each supplied with input signals via integrator inputs INT0 to INT15 and are connected to ground via an output INTGND. Furthermore, a digital / analog converter 10a intended. The controller module may also be present only once. In such a case, the individual LED channels are sequentially controlled.

For the purpose of modulation, two registers are provided in the ASIC for each of the LED channels to be controlled, via which, on the one hand, a switch-off threshold of the integration and, on the other hand, a maximum switch-on time can be determined. In addition, the period of a common switch-on time can be defined. This is done by specifying a so-called frame time in another register. The frame time can be defined on the basis of internal or external clocks. The exact layout of the registers and the function of the frame time are described below.

There is also an SPI module 11 in the form of an SPI host with a register. The abbreviation SPI means "serial peripheral interface" and forms a standard for operating a serial data bus. This module forms a central interface for commissioning and using the ASIC. Above all, it provides access to all registers within the ASIC. While all modules of the ASIC are configurable via their registers, the configuration of the SPI module is fixed. In particular, the SPI module can not be deactivated.

The SPI module is designed for a data width of 8 bits, for example, and is operated at a clock frequency of, for example, 4 MHz. Within SPI communication, the ASIC acts as a slave. The bit significance is set so that the most significant bit (MSB) is set to "first". The polarity and the phase are each set to "zero". A rising edge is assigned to a setting of a level, a falling edge to a reading of a level.

Eleven typical read / write access to the ASIC consists of the transmission of two blocks of 16 bits each, ie two data words each. The first block includes the destination address of the register to be read or write accessed according to the second block, the second block the data to be written to or read from the register. Before the transmission starts, the SPI module within the ASIC is activated via a "low" active signal at an input SS (slave select). On a clock line SCK, the SPI module is then given a clock by a bus master. At the same time, data transfer takes place on data lines SDI and SDO with each clock. The data line SDI is operated as MOSI, ie as a master-out-slave-in line. The data line SDO serves as MISO, ie as a master-in-slave-out line. In this case, the data level is set at a rising clock level of the respective transmitter and read at a falling level of the associated transmitter.

An exemplary SPI communication takes place in such a way that first a defined address value is transmitted to the ASIC. In a subsequent transfer, the ASIC is signaled by a set bit, for example bit 14, that the following bits will be written. When an address or data is written by the master, no data or all zeros are sent by the ASIC. The read access of the master in turn takes place when it sends zeros. Such a data exchange takes place in particular when one of the controller modules is to be activated. In such a case, an ENABLE register is addressed within the ASIC and then set a start bit to enable the controller module. This is followed by reading the ENABLE register, i. H. a feedback that the controller module is ready for use.

At the in 2 The example shown contains the SPI module 11 on the one hand, an L-active SPI bus enable SS, an SPI data input SDI in the form of a master OUT slave IN access (MOSI) and an SPI data output SDO in the form of a master IN-slave OUT access (MISO). In addition, an input for a SPI bus clock SCK is provided.

For clock generation is a clock generator 12 intended. This is designed either as a clock generator with a fixed clock frequency or in the form of a generator for a pulse width modulated signal (PWM clock generator). An embodiment is advantageous in which both operating modes are possible and can be activated by switching. The operating mode is switched by setting a bit in a designated register, the parameters of the pulse operation are expediently specified by a data word. A series of bits, for example the first 4, are used to set the pulse period in pulse mode.

If several LED channels are used in the pulse width modulated mode, a common period expediently applies to them. This can be set in a designated register. The setting of the pulse width is done by means of another register. For PWM operation, individual registers designated PWM0, PWM1 and PWM2 are provided for this purpose. For a pulse operation with a fixed pulse width, which is realized, for example, using a quartz oscillator, connections XTIN and XTOUT are provided.

Furthermore, there is a power driver module 13 provided, which can also act as a power supply to the ASIC. The current driver module makes it possible to operate additional I / O modules directly from the ASIC and to supply them with an adjustable constant current. Depending on the specific embodiment, it is also possible to provide a plurality of current driver modules which operate independently of one another. The current can be set via a register IDACx. In this case, the current value associated with the least significant bit is dependent on a bias voltage, a bias resistor and the length of the data word. The current driver module has a connection VDDD for supplying power to the digital part of the ASIC and a connection VDDA for supplying power to the analog part of the ASIC and corresponding mass outputs GNDD and GNDA. Approaches are provided for setting a reference voltage REFSDC, for specifying an analog reference potential SDC, a reference current programming BIASR and for executing test procedures TEST.

Another module is through a control logic module 14 given. Above all, trigger signals for the start of the integration cycles can be specified via the control logic module. The control logic module has an input SYNC for supplying integration cycle trigger signals and an input RDY for enabling the ASIC components and a RESET access for resetting and restarting the ASIC.

A serial data bus 15 In particular, which is designed as an I²C bridge, establishes the connection of the ASIC with external components. The serial data bus expediently interacts with the SPI module. It has an interface SDA for data and an interface SCL for a clocking.

3 shows an exemplary application circuit based on a circuit diagram. The driver module 1 is here designed as a black box with several inputs and outputs, which are interconnected by the user. The black box of the driver module includes a ground terminal GNDD for its digital and a GNDA ground connection for its analog components, and a ground terminal INTN for the integrator (s) included in the black box. For the power supply of the digital components is an input VDDD, for powering the analog components, an input VDDA is provided.

Furthermore, an input and an output XTIN and XTOUT for the quartz oscillator contained in the black box or a corresponding clock generator is provided. These are capacitively connected in the present case.

The black box of the driver module 1 contains in this example sixteen outputs and inputs for coupling the LED channels. These consist of one voltage connection MF1 to MF16 and one integrator connection INTPLUS1 to INTPLUS16. The driver module's black box is also powered by one or more I _DAC outputs 9 connected. This also serves to supply power to the LED channels. The I _DAC outputs are controllable current sources with a rated current of, for example, up to 1 mA. The ASIC thus provides a set current that controls the power supply and thus adjusts the forward voltage to, for example, the LED channels.

For data exchange via the SPI protocol, a serial data input MOSI, a serial data output MISO, a clock channel SCK and one or more bus enable channels SSXN and one or more bus reset channels RSTXN are provided.

The black box of the driver module 1 communicates with the processor through channels designated for the SPI protocol 2 included microcontroller MCU. The microcontroller MCU contains a power supply VDDD and a ground output. Furthermore, the microcontroller MCU has a communication interface, which is designed, for example, as a PC, SPI, USB, DMX or CAN interface and enables data exchange with other external components. Both the microcontroller and the driver module are coupled to each other via a bidirectional pulse width modulatable synchronization PWMSYNC. This can be given by an external generator on both components.

The interconnection of the LED, ie the coupling of the parallel LED channels to the driver module via field effect transistors. The voltage terminals MF1 to MF16 for the respective LED channel x = 1 to 16 are respectively connected to the gate of a normal-blocking n-type MOSFET 16. The drain of the MOSFET is led to the LED 5 of the respective channel. The source of the MOSFET is in each case via a resistor R _x derived to ground. This resistor R ₁ to R ₁₆ serves as a shunt resistor for the respective integrator in the driver module.

The source branch of each MOSFET is coupled to the respective integrator input INTPLUSx on the driver module of the respective channel. The current flows from the SOURCE of the MOSFET through the shunt into the ground. Above the shunt, a voltage proportional to the current is generated, which serves as an input signal for the integrator constructed with operational amplifiers. This is very high impedance and therefore draws only insignificant power from the measuring branch.

4 illustrates the course of the executed by the arrangement LED control for three LED channels based on exemplary current-time and voltage-time diagrams. For each LED an individual _flux current I _{LED1 arises} . I _LED2 and I _{LED3 on} . This causes a charge transport, which is integrated in the integrator within a given time interval to a time-increasing voltage value U _integrator . Therefore, the integration carried out in each case takes place within predefinable and variable time intervals. These time intervals result from the operation of the LED by means of a pulse operation.

A first time interval t _onmax designates a maximum pulse duration of the operating voltage applied to the LED. The time interval t _onmax can be specified by a register in the driver module. A second time interval is defined by a so-called frame time t _frame . The _frame time t _frame denotes the time period that elapses between two switch- _on times T _on . At these switch-on times, all LED channels are activated, the LEDs are switched on independently of the preceding drive cycles. The frame time thus defines a maximum time frame within which all subsequent control processes can be executed. It is at least as large as the maximum pulse duration t _onmax and is expediently chosen slightly larger in order to gain time for certain relaxation and compensation processes in the ASIC. The modulation of the LED is carried out so that the LED is deactivated after a certain period of time. This period of time is referred to as the actual on-time t ₀ x and is usually different for each individual LED. In 4 is an example of the actual switch-on time t ₀ 2 for the LED2 highlighted.

The modulation is now carried out for each LED channel in such a way that the current I _LED1,2,3 flowing within the frame time is _measured for each LED channel. This current flow manifests itself as an integrated quantity in the form of a voltage value U _integrator measured at the _integrator . As a comparison and reference variable of the modulation, a generally valid reference voltage value U _{ref is} specified. This is set by a register entry in the driver module and determines the threshold value of the integrator, at which the associated LED channel is switched off. The comparison between the currently present voltage value and the reference voltage value takes place in the comparator in the controller module provided for the relevant LED channel.

In the present example, the LED1 is traversed by a comparatively high current I _LED1 . The voltage measured at the integrator now reaches the reference voltage value U _ref after a certain time. In response, the LED1 is now turned off and is disabled for the remaining frame time t _frame . In comparison, the LED2 is traversed by a lower current I _LED2 . The voltage measured at the integrator thus reaches the voltage _{reference value} only at a later point in time, which is, however, before the end of the maximum pulse duration t _onmax . The LED2 is therefore also deactivated before the end of the maximum pulse duration. The current through the LED 3 current I _LED3 has the lowest value. Therefore, the voltage measured at the integrator always remains below the voltage reference value U _ref . The LED3 thus remains always active within the maximum pulse duration and is not _put into the inactive state until the maximum pulse duration t _{onmax elapses} . Both LED1, LED2 and LED3 are reactivated at the beginning of a new frame time interval and the described process of modulation is repeated. The actual switch-on time t ₀ 1 for the LED1 is thus smaller than the actual switch-on time t ₀ 2 for the LED 2 and the actual switch-on time t ₀ 3 for the LED 3. This corresponds to the maximum pulse duration t _onmax . The reference _voltage value U _ref is digitally predefined in a register. The least significant bit (LSB) corresponds to a value of 2 mV, for example. The maximum pulse duration t _onmax , ie the maximum switch-on time, is set, for example, in a register whose register _addresses correspond identically to the actual switch-on time. The values are distinguished by a read-write bit during SPI communication. For example, the least significant bit corresponds to a value of 2 μs.

At the beginning of a new frame, the actual switch-on time t ₀ x of the previous frame is adopted for each individual LED channel until the reference voltage value is again reached. The register _addresses are identical to those of the maximum switch-on time t _onmax . The distinction between the two values is made via the read-write bit during SPI communication. The least significant bit therefore also corresponds to a value of 2 μs.

The type of synchronous start time of a new frame can be specified by means of a register SYNC. The integration cycle can be started by an internal signal, but can also be triggered by an external signal. Such an external synchronization clock is received via a pin FRMSYNC. In the case of an internal synchronization, the internal synchronization clock can be output via the same pin, so that this clock can be passed on to further driver modules. In such a case, all driver modules are synchronized to a common clock and in effect act as a unified driver module. With such a design, very large totalities of LED can be controlled.

Another register allows the digital integrator block in the ASIC to be switched on and off. The switching state of the integrator block is output at a designated pin.

If the frame start is synchronized by an external signal, the cycle time of the external signal measured by the ASIC can be read out via a dedicated register. The register value is updated with the rising edge of the synchronization signal and the counter is reset in the ASIC. For example, the least significant bit corresponds to a value of 2 μs.

The PWM generators PWM0 to PWM2 are additional peripherals in the ASIC, with them, for example, fan speeds can be controlled.

5 shows exemplary representations of usable pulse modes based on exemplary pulse-time diagrams. The upper diagram shows a representation of a pulse operation with a fixed pulse width at a variable pulse period, which is generated for example by a clock generator. The lower diagram shows a pulse-width-modulated PWM pulse mode in which both the pulse period and the pulse width are variable. The pulse mode is switchable by setting a bit in a designated register of the ASIC.

The following three register addresses PULSE_TB0 to PULSE_TB2 respectively determine the operating modes of the individual PWM generators. Expediently, the first four bits within the register addresses PWM0 to PWM2 indicate the pulse width if the pulse width-modulated operating mode is activated within the register addresses PULSE_TB0 to PULSE_TB2. The least significant bit of the register entries in the addresses PULSE_TBx corresponds to a time of, for example, 500 ns.

Within the register addresses PULSE_TBx, one bit each can be switched between the pulse-width modulated mode and the normal pulse mode. If the normal pulse mode is active, the remaining bits set the pulse period. The least significant bit corresponds to a time of, for example, 2 μs. The pulse width itself corresponds to one clock of the ASIC. It is firmly coupled and therefore not adjustable. At a system clock of 16 MHz, the pulse width corresponds to a time of approximately 62 ns.

Finally, a further register address PWM_BASE can be provided, via which the pulse width and period of all three channels can be set. The first four bits of the register give the pulse width modulated periods when the PWM mode of operation is enabled in the associated register PULSE_TBx. For example, the least significant bit corresponds to a time of 500 ns.

The arrangement according to the invention has been described on the basis of exemplary embodiments. In the context of expert action, further embodiments are possible. These arise in particular from the dependent claims.

LIST OF REFERENCE NUMBERS

1

driver module

2

processor

3

Control module

4

LED

5

Power detection unit

6

Shunt resistor

7

integrator

8th

optical power meter

9

power supply

9a

Control module

10

comparator

10a

Digital / analog converter

11

SPI module

 12

clock generator

13

Current drive module

14

Control logic module

15

bus

Biasr

Reference current programming

CTLx

Output for control signals to circuit breakers

GNDA

Mass output analog part

GNDD

Mass output digital part

INTx

Integrating inputs

INTGND

Ground connection for integrator

INTN

Mass for integrators

INTPLUSx

Integriereranschluss

MCU

microcontrollers

MFx

voltage connection

PWMSYNC

Pulse width modulated synchronization

RDY

Activation ASIC / controller module

REFSDC

Set reference voltage

RESET

system reset

RSTXN

Bussrücksetzkanal

_Rx

Shunt resistance per channel

SCK

SPI bus clock

SCL

I²C clock (clocking)

SDA

I²C data

SDI

SPI data input

SDC

analog reference potential

SDO

SPI data output

SS

SPI bus release

SSXN

Busfreigabekanal

SYNC

Trigger signal for new integration cycle (frame)

TEST

Input for test procedures

VDDD

Power supply digital part

VDDA

Power supply analog part

XTIN

Crystal oscillator input

XTOUT

Crystal oscillator output

Claims (9)

Device for controlling an LED arrangement in the form of a driver circuit, characterized by a driver module ( 1 ) and a processor connected to the driver module in a command / feedback circuit ( 2 ), wherein the driver module is a set of regulators connected in parallel ( 3 ), wherein in each case one controller in each case a control circuit with at least one LED ( 4 ) and an energy detection unit ( 5 ) assigned. Apparatus according to claim 1, characterized in that the energy detection unit ( 5 ) a shunt resistor ( 6 ), the controller ( 3 ) an integrator ( 7 ) for a time-integrating measurement of a voltage drop across the shunt resistor. Device according to one of claims 1 or 2, characterized in that the controller has an internal threshold (U _ref ) and a shutdown unit for switching off the LED when the threshold value is exceeded. Device according to one of the preceding claims, characterized in that the driver module ( 1 ) _comprises a generating unit for generating a periodic pulsed operating voltage having a predetermined pulse duration (t _onmax ), the pulse duration corresponding to a maximum integration _{interval of} the integrator ( ₁₂ ). Device according to one of the preceding claims, characterized in that the Processor ( 2 ) with an optical power measurement unit ( 8th ) of the LED is coupled. Device according to one of the preceding claims, characterized in that the driver module ( 1 ) in the form of an Application Specific Integrated Circuit (ASIC) with a module for SPI communication ( 11 ), a regulator module containing the parallel regulators ( 9a ), a clock generator module ( 12 ) and a current driver module is formed. Device according to one of the preceding claims, characterized in that the regulator module ( 3 ) contains a frame register for timing of individual measurement frames, a pulse duration register for specifying the pulse duration (t _onmax ) and / or a duty cycle (t _on ) within a measurement frame and / or a threshold value register for specifying the internal threshold value (U _ref ). Device according to one of the preceding claims, characterized in that the clock generator module ( 12 ) includes a clock mode register (XTIN, XTOUT, PWMx) for selectively specifying a fixed pulse width pulse mode at a variable pulse period or a pulse width modulated signal (PWM). Device according to one of the preceding claims, characterized in that the current driver module ( 13 ) contains at least two independent current drivers, wherein a current driver register is provided for setting a current value.

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