DE202009009895U1 - Integrated circuit with control of the supply voltage based on weighted error detection - Google Patents

Abstract

A circuit or part thereof, characterized in that:
• He has an error detection.
• It has a circuit for error evaluation.
• The error evaluation circuit considers errors of varying severity.
• The circuit for error evaluation controls the supply voltage.

Description

1 overview

1.1 Technical area

at Integrated circuits, the aspect of power consumption always occurs more in the foreground. Especially for battery powered devices such as mobile phones or notebooks is a lower Power consumption desired to maximize battery life. In some circuits, such as microprocessors or Graphics chips is due to the high power consumption and the resulting caused heat generation, the cooling to a. Problem has become.

A Possibility to save electricity is lowering the supply voltage. However, this also reduces the steepness of the signal edges, which can lead to errors. When lowering the supply voltage dynamically depending on parameters like those of the Circuit to be performed tasks or digital circuits the tact with which it is operated takes place, one speaks of Dynamic Voltage Scaling (DVS). Even in the context of manufacturing tolerances, fluctuations in the supply voltage, etc a reliable function the circuit must be ensured in the case of Choice of supply voltage can be estimated conservatively. However, this estimate will be possible in individual cases Energy savings not realized.

on the other hand There are possibilities that occur in integrated circuits To recognize mistakes. These have been around for a long time in environments which are safety critical, or where the occurrence of errors for other reasons (eg radiation) is likely such as space travel, used.

1.2 State of the art

One approach that uses error detection to optimize the lowering of the supply voltage is Razor Ernst et al. (2003) , In this case, the memory elements contained in a clocked circuit (eg bistable flip-flops) are provided with additional latches. These latches are operated with an offset clock, so that errors that have occurred due to lack of steepness of signal edges are visible as differences between the value actually used, stored in the memory element and the value stored in the latch. Upon detection of an error, an error correction mechanism will take action. The supply voltage is regulated as a function of the error rate, that is increased at high error rate, lowered at low error rate in order to obtain an optimal compromise between energy consumption and effort for error correction.

Regardless of the issue of power consumption (instead of investigating which parts of a circuit should be hardened especially against radiation induced errors), errors in image processing integrated circuits have already been divided into critical and tolerable errors Nowroth and others (2008) , Tolerable errors were considered to be those that had barely visible effects on the output image.

In order to keep energy consumption as low as possible in view of manufacturing tolerances, there is the approach of the Voltage Islands Stefano et al. (2008) , In this case, the minimum possible supply voltage at which no errors occur, determined independently for subcircuits and then operated each subcircuit within the integrated circuit with the minimum possible for them.

At the Dynamic Voltage and Frequency Scaling that in modern day Processors, such as the AMD Phenom will be used depending on how busy the processor is, Clock rate and supply voltage lowered. The lowering of the clock rate on the one hand directly reduces the power consumption, on the other hand it can thereby the lower steepness of the signal edges caused by the lowering the supply voltage is caused to be tolerated.

1.3 The invention

An integrated circuit or a part thereof is provided with error detection. Depending on the number and severity of the errors that have occurred, the supply voltage is regulated, or the errors may be corrected. For example, whenever the heavy weighted sum of errors occurred in a certain period of time exceeds a threshold, the supply voltage could be increased. New to this approach is, in particular, that the errors can be weighted by gravity, not just as in Nowroth and others (2008) be divided into tolerable and critical.

2 Detailed description

In this section, an advantageous embodiment of the invention 1 described.

An integrated circuit or part ( 101 ) of which is provided with error detection. Information ( 201 ) errors that have occurred are displayed on an error evaluation circuit ( 103 ) (this circuit is usually part of the same inte be grated circuit). The circuit for error evaluation now outputs signals for changing the supply voltage as a function of this information ( 203 ) to the supply voltage regulation ( 102 ). Possibly contains ( 101 ) also has an error correction mechanism. In this case, there are 103 ) depending on ( 201 ) also a signal ( 202 ) to activate the error correction ( 101 ).

A possible embodiment of ( 103 ) It would be weighted to add occurred errors to a stored value. At fixed time intervals, a constant would be subtracted from the stored value. Depending on the undershooting or exceeding of certain threshold values, voltage supply and, if present, error correcting mechanism would be controlled.

literature

[Serious u. a. 2003] ERNST, Dan; KIM, Nam S .; THAT, Shidhartha; PANT, Sanjay; RAO, Rajeev; PHAM, Toan; ZIESLER, Conrad; BLAAUW, David; AUSTIN, Todd; FLAUTNER, Krisztian; MUDGE, Trevor: Razor: A Low-Power Pipeline Based on circuit-level timing speculation. In: MICRO 36: Proceedings of the 36th annual IEEE / ACM International Symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 2003, p. 7 - ISBN 0-7695-2043-X

[Nowroth u. a. 2008] NOWROTH, Damian; POLIAN, Ilia; BECKER, Bernd: A study of cognitive resilience in a JPEG compressor. In: DSN, IEEE computer Society, 2008, pp. 32-41

[Stefano u. a. 2008] STEFANO, Bonesi; BERTOZZI, Davide; BENINI, Luca; MACII, Enrico: Process variation tolerant pipeline design through a placement-aware multiple voltage island design style. In: DATE '08: Proceedings of the conference on Design, automation and test in Europe. New York, NY, USA: ACM, 2008, pp. 967-972. - ISBN 978-3-9810801-3-1

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited non-patent literature

• - Ernst et al. (2003) [0004]
• - Nowroth et al. (2008) [0005]
• - Stefano et al. (2008) [0006]
• - Nowroth et al. (2008) [0008]
• - [Ernst et al 2003] ERNST, Dan; KIM, Nam S .; THAT, Shidhartha; PANT, Sanjay; RAO, Rajeev; PHAM, Toan; ZIESLER, Conrad; BLAAUW, David; AUSTIN, Todd; FLAUTNER, Krisztian; MUDGE, Trevor: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. In: MICRO 36: Proceedings of the 36th Annual IEEE / ACM International Symposium on Microarchitecture. Washington, DC, USA: IEEE Computer Society, 2003, p. 7 - ISBN 0-7695-2043-X [0012]
• - [Nowroth et al. 2008] NOWROTH, Damian; POLIAN, Ilia; BECKER, Bernd: A study of cognitive resilience in a JPEG compressor. In: DSN, IEEE Computer Society, 2008, pp. 32-41 [0013]
• - [Stefano et al. 2008] STEFANO, Bonesi; BERTOZZI, Davide; BENINI, Luca; MACII, Enrico: Process variation tolerant pipeline design through a placement-aware multiple voltage island design style. In: DATE '08: Proceedings of the conference on Design, automation and test in Europe. New York, NY, USA: ACM, 2008, pp. 967-972. - ISBN 978-3-9810801-3-1 [0014]

Claims (6)

A circuit or part thereof, characterized in that: • It has an error detection. • It has a circuit for error evaluation. • The error evaluation circuit considers errors of varying severity. • The circuit for error evaluation controls the supply voltage. A circuit according to claim 1, wherein in the error evaluation: • One Comparison value by adding up to weighted error is used. • Depending on this comparison value the supply voltage is regulated. A circuit according to claim 2, wherein in the comparison value: • Time-dependent is lowered again, for example by subtracting a constant at fixed time intervals. A circuit according to claim 2 or 3, wherein: • The Control of the supply voltage depends on whether the Comparison value exceeds or exceeds certain thresholds. A circuit according to any one of the preceding claims, in which: • The error evaluation circuit also includes an error correction mechanism can activate. A circuit according to any one of the preceding claims, in which: • The circuit as an integrated circuit is executed.