DE20122578U1 - Page hint indication transfer circuit for page mode memory system, transmits page hint indication during initiated operation - Google Patents

Abstract

Processors (12A,12B) and L2 cache (14), transmit a page hint indication during an initiated operation. The page hint indication indicates whether a page addressed by the operation is to be kept open or closed. Independent claims are also included for the following: (a) Memory controller; (b) Page hint indication transfer system; (c) Recorded medium storing page hint indication transfer program.

Description

Background of the invention

1st area the invention

The The invention relates to the field of memory systems and in particular, the page mode or page mode of storage systems.

2. Description of the state of the technique

Memory Systems typically contain dynamic random access memory (DRAM) of one type or another. DRAM may include asynchronous DRAM, synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), SyncLink DRAM (SLDRAM), Rambus DRAM (RDRAM) etc. In general DRAM memories are built in a matrix of memory locations, which are arranged in rows and columns. To be on a specific Memory location in the DRAM (e.g., for reading or writing), receives the DRAM selects a row address which selects the row in where the location is, and a column address, which selects the column, in which the storage location is located. Each location can to be able to store one or more bits. The series and Column addresses are typically on a set of address lines multiplexed. This way, you can access a DRAM location accessed by transfer the row address on the address lines and then transmitting the column address on the address lines.

Around a shortened one Waiting time or delay to allow ("latency") when multiple memory locations in the same row are accessed sequentially will support Most DRAMs perform page mode or page mode. In page mode is the row address to the DRAM and then the column address of the first Transfer memory location, to be accessed. To more storage locations in the same row, then the column addresses of the transmitted to further storage locations, without retransmitting the row address. This can be up the more memory locations are accessed in a shorter time, than on the initial one Location because the row address does not retransmit every time must become. The memory locations selected by a row address are referred to here as a "page". The Keep the page in the selected one or opened State, so only column addresses are used to accessing other locations in the same page is called Keeping the page open, and deselecting the row, giving a new row address for accessing another one Transfer storage location can be, is called closing the page designates. DRAMs, such as SDRAMs include Benches of Rows and columns. In such DRAMs, the page can be out of a row within a bank. One page was indeed under here Reference to DRAMs described a page may as well refer to memory locations in any memory which is a memory location for one Access dependent selected from a row address and a column address.

Of the However, page mode is not without its disadvantage. The page mode becomes in particular by holding the page within the DRAM in the selected state inhibited. For asynchronous DRAMs, the row is selected by activating a row address strobe signal (RAS) and sending the row address on the address lines. For synchronous DRAMs, an activation command is used together with the Transfer row address to the DRAM. Dependent on from the row address, the DRAM reads the page into a temporary memory location, which is coupled to the DRAM memory (for example, the sense amplifier, the for reading the data in the memory locations or in another clocked one Storage device is used). The page stays that way in the temporary Memory like the page opened is (for example, as long as the address pulse signal RAS in an asynchronous DRAM remains active or sent a command in a synchronous DRAM will close the series). This will, when accessing a memory location in a other side, the access is delayed while the previous page is closed (by a "Deassert" address pulse signal RAS or by sending the command to close the page). The running time while the closed previous page, extends the delay for this Access compared to when the page with the completion the previous access would have been closed.

typically, Memory controllers are configured to enter a page mode allow or to disable, and can be programmed to different strategies for the page mode. However, the existing mechanisms do not allow fine-access control about that, whether a page that corresponds to a specific memory access in open State should be maintained or not. This will become pages regularly closed, even if it is advantageous. would, these in the open Condition, and the pages are regularly kept open, too if it were beneficial to close this.

Summary the invention

The above problems are solved by the majority a system with an agent and a memory controller as described herein. The agent can initiate transactions that are in memory to which the memory controller is coupled (the Memory can e.g. a kind of DRAM). Memory transactions can include a page hint indication. The page hint is during the transaction is submitted by the agent and may contain an indication of whether the one addressed by the transaction Page to be kept open or closed. In other words the indication may be an indication by the agent regarding closing or of keeping the page open. An agent can show that the page should be kept open if an additional Transaction or transactions within the same page of the Memory are likely (e.g., if the agent itself is additional Transmit or transmit transactions within the same page becomes). In such cases the agent can use the page hint indication to indicate that the page in question remains open should. The additional Transactions can cause page mode hint delays Experienced. In other cases the agent can indicate that the page should be closed. additional Transactions or pages can the for the closing the page required delay Do not learn if the page in response to the page hint is closed. This can be due to the more efficient in the system Using the page mode realized a reduction in the total memory delay become.

Of the Memory controller can receive a page hint indication. At the Accessing the memory location (s) in the memory in response on the store transaction, The memory controller may page depending on the page hint indication in the open Maintain or close state. In this way, a fine-access control is provided about that, which pages in open State and which pages are closed. It means that Each agent will decide on a transaction-by-transaction basis can see if certain pages remain open should or should be closed. Because the requesting agent has information can have, whether additional Transactions for this page is likely, and submit a corresponding page hint indication can, can Pages more often open stay if it is beneficial to do so and the pages can be closed more frequently if it is beneficial to do so.

Generally formulated is considered a system that has an agent and a Memory controller includes. The agent is configured to he initiates a first transaction and a page hint indication while the first transaction. The page hint indication indicates whether one by the first transaction addressed page opened should stay or not. The memory controller is to receive the page hint indication coupled and configured so that it fits the page in one of the Memory controller coupled memory depending on the page hint indication keep it open can.

In addition, will an agent described. The agent includes a circuit that is configured to initiate a first transaction and a page hint while the first transaction. The page hint indication indicates whether one by the first transaction addressed page opened should stay or not.

Furthermore Consider a memory controller that has a queue and comprises a circuit coupled thereto. The queue is set up, a first transaction and one corresponding to the first transaction Side Note specification to recieve. The page hint indication indicates whether a through the first transaction addressed page should remain open or not. The circuit is configured to go with one through the first transaction addressed memory communicates with the Circuit is configured to the side in dependence from the page hint indication optionally kept open.

It Furthermore, a device is described, wherein a first transaction and a corresponding page hint indication. The Side Note specification indicates whether a page addressed by the first transaction stay open should or not. The page will be in response to the page hint indication optionally in the open Condition kept.

Short description the drawings

Other Objects and advantages of the invention will become apparent from the following description apparently with reference to the accompanying drawings, in which:

1 Figure 10 is a block diagram of one embodiment of a system.

2 is a block diagram of one embodiment of an address portion of an in 1 shown bus.

3 Figure 12 is a block diagram of one embodiment of a memory controller.

4 FIG. 4 is a flowchart illustrating the operation of one embodiment of an in 3 shown channel control circuit during processing of a transaction.

5 FIG. 10 is a flowchart showing the operation of one embodiment of a DMA agent. FIG.

6 FIG. 10 is a flowchart illustrating the operation of one embodiment of a processor agent. FIG.

7 is a block diagram of one embodiment of an agent.

8th FIG. 10 is a block diagram of one embodiment of a data carrier medium. FIG.

The The present invention may be illustrated in alternative embodiments as well as undergo various modifications, so that special embodiments the invention shown only as an example in the drawings and below will be described in detail. It is self-evident that the drawings and the detailed description are not to serve, the present invention described in this particular embodiments to restrict, but according to the contrary intention, all modifications, equivalents and to cover alternatives that fall under the inventive concept and are within the scope of the present invention, as he is attached by the claims is defined.

Detailed description of the preferred embodiments

Overview of the system

In 1 is a block diagram of one embodiment of a system 10 shown. Other embodiments are possible and contemplated. At the in 1 In the embodiment shown, the system comprises 10 processors 12A - 12B , an L2 cache 14 , a memory controller 16 , a pair of input / output (I / O) bridges 20A - 20B as well as input / output interfaces 22A - 22D , The system 10 can a bus 24 for connecting the various components of the system 10 include. As in 1 shown, the bus can 24 in particular decision lines 28 include, an address bus 30 , Answer lines 32 , a data bus 34 and a time signal line or time signal lines 36 , As in 1 represented is each of the processors 12A - 12B , the L2 cache 14 , the memory controller 16 and the input / output bridges 20A - 20B to the bus 24 coupled. Thereby, in the illustrated embodiment, each of the processors 12A - 12B , the L2 cache 14 , the memory controller 16 and the input / output bridges 20A - 20B an agent on the bus 24 be. In particular, each agent can be connected to the time signal lines) 36 and the wires inside the bus 24 be coupled, which carry the signals that the agent in question scans. and / or drives. The input / output bridge 20A is to the input / output interfaces 22A - 22B coupled and the input / output bridge 20B is to the input / output interfaces 22C - 22D coupled. The L2 cache 14 is to the memory controller 16 coupled, in turn, to a memory 26 is coupled.

Generally speaking, the agents can participate in the transactions on the bus 24 participate. The term "agent" as used herein refers to a device capable of communicating on the bus. The agent may be a requesting agent when the agent is capable of initiating transactions on the bus, and the agent may be a responding agent when the agent is able to respond to transactions made by a requesting agent were initiated. A particular agent may have the ability to be both a requesting agent and a responding agent. Further, a "transaction" represents communication on the bus. The transaction may include an address transfer and optionally a data transfer. Transactions can be both read transactions (transfer of data from the answering agent to the requesting agent) and write transactions (transfer of data from the requesting agent to the answering agent). Transactions may also include different coherency commands, which may or may not involve a transfer of data.

Transactions on the bus. 24 can access memory locations in the memory 26 ("Storage Transactions"). The memory controller 16 is the answering agent for the memory transactions unless the memory transactions are the L2 cache 14 In this case, the L2 cache 14 the answering agent can be. In other embodiments, no L2 cache can also be used 14 be provided and the memory controller 16 can be the answering agent for all storage transactions.

Memory transactions may include a page hint indication. The page hint indication may be transmitted by the requesting agent during the transaction and may indicate whether the page addressed by the transaction is left open or closed. In other words, the page hint indication may be an indication by the requesting agent regarding the closing or keeping open of the page. For example, an agent may indicate that the page should remain open when An additional transaction or transactions within the same page of the store are likely. For example, a requesting agent may perform multiple transactions to access a data block that is larger than the amount of data that is transferable in a transaction, and may soon become the additional. Perform transactions to access the entire data block. A requesting agent may include a queue of outgoing transactions, and the requesting agent may check the queue; to determine if there are any additional queues in the queue that are related to the same page as an already initiated transaction. A requesting agent may be in a state where it is likely that additional transactions will not currently be queued (eg, a processor finds itself in a loop and thereby proximate transactions on subsequent iterations of the loop Addresses are generated). In any of these or other cases, the requesting agent may indicate, through the page hint indication, that the page should remain open: the additional transactions will not experience any page mode delays. In other cases, the agent may indicate that the page should be closed. If the page is closed in response to this alert, additional transactions to other pages will experience a delay to close the page: due to the more efficient use of page mode, the system may 10 realize a reduction of the total memory delay.

The memory controller 16 can receive the page hint indication. When accessing the memory location (s) in response to the memory transaction, the memory controller may 16 close the page in response to the page hint indication or keep it in the open state. In this way, a fine access control is provided which pages to keep open and which pages to close. That is, each requesting agent can indicate, on a transaction-by-transaction basis, whether certain pages should be kept open or closed. Since the requesting agent may have information about whether an additional transaction to the page in question is likely or not and may provide a corresponding page hint indication, pages may be more frequently kept open if it is beneficial to do so, and pages can be kept closed more frequently if it is beneficial to do so.

In one embodiment, the page hint indication may be communicated during the address phase of the transaction. In other embodiments, the page hint indication may be communicated during the data phase or at some other time in the transaction. In one embodiment, the page hint indication may be a signal that can be asserted to indicate the page that is to remain open. The signal may be deasserted to indicate that the page should be closed. In other embodiments, the page hint may be in the command signals on the bus 24 encoded (eg, the command signals transmitted during the address phase) or in any other suitable form from the requesting agent to the memory controller 16 be transmitted.

The bus 24 may be a shared transaction bus, as in the illustrated embodiment. A shared transaction bus separates the address and data portions of each transaction and allows the address portion (related to the address phase and the data portion (related to the data phase) to be independently transmitted In the illustrated embodiment, the address bus becomes 30 and the data bus 34 (using signals on the equalization lines 28 ) processed independently. Each transaction includes both addresses and data, thereby balancing the address bus 30 , an address phase on the address bus 30 , compensation for the data bus 34 , and a data phase on the data bus 34 , Additionally, coherent transactions may have a response phase on the response lines 32 for communicating coherency information after the address phase. Further below, additional details regarding an embodiment of the bus will be provided 24 specified. The bus time signal CLK on the time signal lines 36 defines the time signal cycle for the bus 24 ,

The bus 24 can be designed as a line. The bus 24 can use any suitable signal technique. For example, in one embodiment, the differential signal technique may be used for high speed signal transmission. In other embodiments, a different signal technique may be used (eg, TTL, CMOS, GTL, HSTL, etc.).

The processors 12A - 12B may be designed for any instruction set architecture and execute programs written in instruction sets according to this architecture. Exemplary instruction set architectures may include the MEPS instruction set architecture (including the MIPS-3D and the MIPS MDMX application-specific extensions), the Intel Corp. IA-32 or IA-64 instruction set architectures. developed the PowerPC-In construction set architecture, the Alpha Instruction Set Architecture, the ARM Instruction Set Architecture or any other Instruction Set Architecture.

The L2 cache 14 is a high-speed cache memory. The L2 cache 14 is called "L2" because the processors 12A - 12B Support caches with internal level 1 ("L1"). If ll caches in the processors 12A - 12B not included can be the L2 cache 14 be an L1 cache. Also, if cache levels of different levels in the processors 12A - 12B may contain the L2 cache 14 be a higher level cache than L2. The L2 cache 14 can use any organization, including direct mappings, associative sentences and fully associative organizations. In a particular embodiment, the L2 cache may be 14 be a 512 kbyte 4 way associative sentence cache with 32 Bit cache lines. An associative set cache is a multi-sentence cache, each set having two or more entries. A portion of the address (the "index") is used to select one of these sentences (that is, each coding of the index selects a different sentence). The entries in the selected set are suitable for storing the cache line accessed by the address. Each of the entries within the sentence is referred to as a "way" of the sentence. The portion of the address remaining after the removal of the index (and the offset within the cache line) is referred to as a "tag" and is stored in each entry to identify the cache line in that entry. The stored tags are compared with the corresponding tag portion of the address of a memory transaction to determine if the memory transaction hits or misses the cache, and is used to select the path on which the hit is detected (if a hit is detected).

The memory controller 16 is configured to access the memory 26 in response to the memory transactions that are on the bus 24 be received. The memory controller 16 receives a hit signal from the L2 cache 14 , and if in the L2 cache 14 a hit for a memory transaction is detected, the memory controller responds 16 not on this memory transaction. If through the L2 cache 14 If a misconduct is detected or the memory transaction can not be processed by the cache, the memory controller may 16 on the memory 26 access to perform a read or write operation. The memory controller 16 may be configured to access any of the plurality of memory types. For example, the memory controller 16 be designed for synchronous dynamic random access memory (SDRAM) and in particular for double data rate (DDR) SDRAM. Alternatively, the memory controller may be configured for DRAM, Rambus DRAM (RDRAM), SRAM, or any other suitable memory device.

The input / output bridges 20A - 20B connect one or more input / output interfaces (eg input / output interfaces) 22A - 22B for the input / output bridge 20A and the input / output interfaces 22C - 22D for input / output 20B ) by bus 24 , The input / output bridges 20A - 20B can serve the electric charge on the bus 24 reduce if more than one input / output interface 22A - 22B is bridged by this input / output bridge. Generally, the input / output bridge performs 20A Transactions on the bus 24 for the input / output interfaces 22A - 22B and forwards the to an input / output interface 22C - 22D directed transactions from the bus 24 to the input / output interface 22C - 22D further. In one implementation, the input / output bridge 20A a bridge to a PCI interface (eg, input / output interface 22A) and a "Lightning Data Transport (LTD)" input / output structure developed by Advanced Micro Devices Inc. (eg, the input I / O interface 22B , Other input / output interfaces may be through the input / output bridge 20B be bridged. Other implementations may bridge any combination of input / output interfaces using any combination of input / output bridges. The input / output interfaces 22A - 22D may include one or more serial ports, Personal Memory Computer Card International Association (PCMCIA) interfaces, Ethernet interfaces (eg, Media Access Control Level Interfaces), Peripheral Component Interconnect (PCI) interfaces, LDT interfaces, etc.

It should be noted that the system 10 and in particular the processors 12A - 12B , the L2 cache 14 , the memory controller 16 , the input / output interfaces 22A - 22B , the input / output bridges 20A - 20B and the bus 24 may be integrated into a single integrated circuit, such as a "system on a chip configuration." The memory 26 can also be integrated in another configuration. Alternatively, one or more components may be implemented as separate integrated circuits, or all components may be implemented as separate integrated circuits as needed. Any degree of integration can be used.

It should be noted that although in the dar embodiment, a split transaction bus with separate balance for the address and data bus is used, other embodiments with non-shared transaction buses with a single address and data balance and / or a shared transaction bus may be used, where the data bus is not explicitly balanced. Depending on the design choice, either a central compensation scheme or a distributed compensation scheme can be used. It should be noted that, though 1 Input / output interfaces 22A - 22D represents that over the input / output bridges 20A - 20B to the bus 24 coupled, other embodiments may include one or more input / output interfaces directly to the bus 24 coupled, if desired.

In 2 a block diagram is shown exemplifying signals as they appear on the address bus 30 can lie. Other embodiments are possible and contemplated. In the illustrated embodiment, the address bus includes 30 Address lines that are used to provide the address of the transaction (Addr [39: 5]) and a set of bytes (A_BYEN [31: 0]) allows to indicate which bytes on the data bus 34 are read or written during the transaction, and a command (A_CMD [2: 0]) is used to indicate the transaction to be performed (read, write, etc.), a transaction ID (A_ID [9: 0]) is used to identify the transaction, a set of attributes (A_ATTR [n: 0]) and a page hint signal (A_PAGE_HINT).

The Transaction ID can be used to handle the address and data phases to join the transaction. In particular, the answering one Agent the value supplied on the transaction ID as the transaction ID for the Use data phase. Accordingly, the transaction ID a license plate for to be the transaction. A section of the transaction ID is a Agent identifier that identifies the requesting agent. The agent identifier may be on bits 9: 6 of the transaction ID, for example. Each agent is associated with a different agent identifier.

The set of attributes may include any set of additional attributes to be transmitted in the address phase. For example, the attributes may include a cache capability indicator indicating whether or not the transaction can be processed in a cache within the requesting agent, a coherency indicator indicating whether the transaction is coherent or not, and a Cache capability indicator for the L2 cache 14 , As needed, other embodiments may use more, fewer, or different attributes.

The page hint signal may be used to convey the page hint indication for the transaction. The signal may be "asserted" to indicate that the page should remain open, and the signal may be "deasserted" to indicate that the page is about to be closed, or vice versa. This allows the page-hint signal to be among several with the bus 24 be split coupled agents. A signal is generally defined as asserted when it is at a low voltage level ("active low") or when it is at a high voltage level ("active high"). In the case of different signals, a signal for a difference between different signal pairs can be confirmed or "asserted" and "deasserted" for other differences. As mentioned above, other embodiments may encode the page hint indication into the command signals (A_CMD). Other embodiments may encode the page hint indication into the attributes (A_ATTR).

Memory controller

In 3 FIG. 10 is a block diagram of one embodiment of the memory controller. FIG 16 shown. Other embodiments are possible and contemplated. At the in 3 In the embodiment shown, the memory controller includes 16 a transaction queue 40 and channel control circuits 42A - 42B , The transaction queue 40 is to communicate with the bus 24 and is connected to the channel control circuits 42A - 42B coupled. Each of the channel control circuits 42A - 42B is to the relevant memory channel 44A - 44B coupled. The channel control circuit 42A includes a configuration register 46A and an open-side buffer 48A ("open page buffer"). Accordingly, the channel control circuit includes 42B a configuration register 46B and an open-side buffer 48B ("open page buffer").

The transaction queue 40 contains several entries, each entry being configured to store information corresponding to a transaction. The transaction queue 40 may include a control circuit that has entries to those on the bus 24 initiated memory transactions. The transaction queue 40 takes the transaction information for the memory transactions from the bus 24 in the assigned entries. In 3 For example, there will be multiple fields for the two exemplary entries within the transaction queue 40 shown. The fields include a validity bit, the address of the transaction, the command field, the page hint indication, the transaction i ons-ID of the transaction, the data for the transaction and the data validity bit. Other embodiments may store different, additional, or alternative information for each transaction.

The control circuit in the transaction queue 40 directs the transactions to one of the channel control circuits 42A - 42B for accessing the memory 26 to. In the illustrated embodiment, the memory is 26 divided into two sections, through which different channels 44A - 44B is accessed. Other embodiments may include more or fewer channels. The area of the memory address is mapped to the channels via non-shown configuration registers (and may be mapped to multiple chips selected on a channel, etc.). Based on the address of the transaction, the control circuit can thereby determine which channel control circuit 42A - 42B the transaction has been assigned.

The channel control circuit 42A - 42B receives the transaction interfaces with the memory coupled to the corresponding memory channel and performs the read or write specified by the transaction. In general, the formation of an interface with the memory may include transmitting the row address, transmitting the column address, and transmitting or receiving data. In addition, the channel control circuit 42A - 42B keep the page addressed by the transaction open or close the page. Here, a page is said to be "addressed" by a transaction if the row address of the transaction matches the row address of the corresponding page. The channel control circuit 42A - 42B receives the page hint indication corresponding to the transaction and, based on the page hint indication, can keep the page open or close the page.

In one embodiment, the channel control circuits 42A - 42B with a page mode policy (via the configuration tab 46A - 46B ) be programmable. The available page mode policies include a hint policy that uses the page hint information provided in the transaction to determine if the page should be left open or closed. As required, other page mode policies may be implemented where the page hint indication may or may not be used. For example, in one embodiment, a page-closing policy and a policy for checking the CAS time (column address-pulse-time) may be implemented. The page-closing policy closes the page after each transaction and does not use the page hint. The column address pulse (CAS) CAS time check policy checks the channel control circuitry 42A - 42B the transaction queue 40 at the time that the column address of the transaction is to be transmitted to determine if there is another transaction in queue for the same page. If that is the case, the page can be kept open. Otherwise, the page can be closed. The policy for checking the CAS time can not use the page hint. On the other hand, the CAS time check policy may use the page hint indication to determine that the page should remain open if there are no transactions in the queue for the same page, but the page hint indication indicates that the page should remain open.

In one embodiment, multiple chip selectors may be supported on each memory channel. The chip selectors may be coupled to different memory chips or modules (eg, dual in series with memory modules or DIMMs) and may select the chips or modules in response to a particular memory transaction. The in the configuration registers 46A - 46B programmed page mode policy may include a separate policy for each chip selection so that the policy may vary based on a chip selection (ie, one chip selection may be assigned to a page mode policy, while another chip selection may be one) different page mode policy can be assigned, etc.). In addition, the page mode policies for each channel can be programmed by appropriately programming the appropriate configuration registers 46A - 46B be different. The configuration registers 46A - 46B are basically accessible via software (eg on the processors 12A - 12B executed instructions) so that they can be programmed by software. For example, the configuration registers 46A - 46B to certain addresses within the on the bus 24 available address range and the load and store instructions to these addresses can be used to access the configuration registers 46A - 46B to read and write.

The channel control circuits 42A - 42B can use the open-side buffers 48A - 48B use to locate the pages currently on the corresponding memory channels 44A - 44B are open. The open-side buffers 48A-48B For each memory section, a buffer entry may be included which may simultaneously have an open page (eg, each bank of a chip selection or each chip selection depending on the configuration). Each entry can indicate if one Page is open or not, and can display the page (eg by saving the row address). Before executing an activity corresponding to a transaction on the memory channel 44A - 44B , the channel control circuit 42A - 42B the open-side buffer 48A-48B Check to see if the page is already open. If that is the case, the channel control circuit 42A - 42B continue to transfer the column address of the transaction (eg, with a read or write command in an SDRAM or by asserting the column address strobe (CAS) in an asynchronous DRAM) without transferring the row address of the transaction. If the page is not already open and another page is open in the memory to be accessed (eg in the same bank and chip select for SDRAM or in the same chip select for an asynchronous DRAM), then the channel closes. control circuit 42A - 42B the open page and then proceed to transfer the row address of the transaction. If the page is not already open, but the memory to be accessed does not yet have an open page, then the channel control circuit will move 42A - 42B with transferring the row address of the transaction. When the channel control circuit 42A - 42B keeps the page open after a transaction, then updates the channel control circuit 42A - 42B the open-side buffer 48A with the row address of the transaction.

If, in addition to closing pages in the same memory section, another page is to be opened, the channel control circuits may 42A - 42B also close sides for other reasons. For example, if a refresh of the memory contents or a "refresh" is to be performed in the memory section, the page for this memory section can be closed.

It should be noted that in embodiments having an L2 cache 14 use the transaction queue 40 can be configured to cancel a transaction if an L2 hit signal from the L2 cache 14 during the transaction is confirmed. Some embodiments may use a coherent transaction intervention protocol wherein a coherent agent puts the data on the bus 24 for a transaction when the coherent agent has sufficient control over the data (eg, a modified or exclusive). In such embodiments, the transaction queue 40 be configured to cancel a transaction when a coherency agent is to deliver the data.

4 FIG. 12 is a flowchart illustrating the operation of one embodiment of a channel control circuit. FIG 42A - 42B for determining whether or not a page should remain open during a memory access for a transaction. Other embodiments are possible and contemplated. While the in 4 For ease of understanding, blocks shown in a particular order may also be used, any other suitable order may be used. Further, some blocks may be connected in parallel by combinatorial logic circuits in the channel control circuits 42A - 42B be executed.

The flowchart in 4 Generally, it is the determination of whether a page is open. should stay or not. This determination may be made at any time, for example, some embodiments may make the determination at a time when the column address for memory access is to be transmitted according to the transaction. This timing may be suitable for SDRAM memory because a page may be closed with a self-precharge command as part of the read or write command used to transmit the column address. It is also possible to close pages with an explicit bias command sent independently of a read or write command, as is done when one page is left open and later closed to open another page To refresh the memory contents of the corresponding memory section ("refresh"). For asynchronous DRAMs, the page can be closed by deasserting the RAS signal. Other favorable times during the memory access, which is suitable for determining whether the page should remain open or the page should be closed, may include the beginning of the memory access (if the transaction is to the channel control circuit 42A - 42B is directed) etc.

The channel control circuit 42A - 42B can determine if the page mode policy is in the configuration tab 46A - 46B is the page hint policy, which uses the page hint specified in the transaction to determine if the page should be left open or closed (decision block 50 ). If the page mode policy does not conform to the page hint policy, the channel control circuit may 42A - 42B based on the selected policy (Block 52 ) determine whether the page should remain open or whether the page should be closed.

If the page mode policy matches the page hint policy, the channel control circuit will check 42A - 42B the page hint indication of the appropriate transaction to determine if the page remains open or to be closed (decision block 54 ). If the page hint indication indicates that the page should remain open, the channel control circuit will stop 42A - 42B the page in the opened state (block 56 ). If the page hint indication indicates that the page should be closed, the page will be closed (block 58 ).

In 5 FIG. 3 is a flowchart illustrating the operation of an exemplary agent for determining a page hint indication for a transaction. Specifically, the page hint indication in the illustrated embodiment may be a signal that is asserted to indicate that the page is to remain open and that is deasserted to indicate that the page is being closed should. As noted above, other embodiments may otherwise transfer the page hint indication, with a flowchart similar to that of FIG 5 shown flowchart can be used. The exemplary agent in 5 performs a number of direct memory access (DMA) transactions. The agent may be a DMA engine or, for example, one of the input / output bridges 20A - 20B directing the DMA transactions from a device to an input / output interface 22A - 22D forwards. Other embodiments are possible and contemplated. At the in 5 In the embodiment shown, several blocks are shown in a particular order for ease of understanding. However, any other order may be used. Further, the blocks may be executed in parallel by combinatorial logic circuits within the agent.

If the transaction is the last in a series of transactions addressing a particular page (decision block 60 ), then the agent can transmit the transaction with the "deasserted" page hint signal (block 62 ). In general, a series of transactions in a DMA include consecutive addresses. Therefore, a subset of the series of transactions may address a particular page, followed by another subset of transactions that affect another page. Accordingly, it may be advantageous to close the page if the last transaction addressed to this page has been transmitted to reduce the delay if the newly addressed page is in the same memory section (or the delay for some other transactions to reduce, which concern this memory section). It should be noted that the agent to execute the decision in block 60 has the information about which part of the transaction addresses is used to form the row address. If necessary, in other embodiments, the decision of the block 60 not contain, and thereby the page hint signal for each transaction in the direct memory access (DMA) in the decision block 64 confirm as described below.

If the transaction is the last transaction of direct memory access DMA (decision block 64 ), the agent can transmit the transaction with the "deasserted" page hint signal (block 62 ). Since the transaction is the last transaction, the agent can not have any information as to whether any additional transactions are addressing the same page. Therefore, it may be advantageous to close the page to reduce delay for other transactions involving this memory section.

If the transaction is not the last transaction of direct memory access DMA (and optionally not the last address in the current page), the agent may transmit the transaction with the acknowledged page hint signal (block 66 ). In this case, the agent has the information of additional transactions concerning the same page, and it may therefore be advantageous to keep the page open in order to reduce the delay for these additional transactions.

6 FIG. 12 is a flowchart illustrating the operation of another exemplary agent for determining the page hint indication for a transaction. FIG. In the illustrated embodiment, the page hint indication may be a signal that is asserted to indicate that the page should remain open and be deasserted to indicate that the page should be closed. As mentioned above, other embodiments may convey the page hint indication in other ways, and flowcharts similar to those in FIG 6 shown flow chart used. The in 6 The exemplary agent shown may be a processor agent (eg, processors 12A or 12B in 1 ) be. as needed, other types of agents may use a similar mode of operation. At the in 6 In the illustrated embodiment, several blocks are shown in a particular order for ease of understanding. However, a different order may be used. Further, the blocks may be executed in parallel by a combinatorial logic circuit within the agent.

A processor agent may include a queue for transactions that are on the bus 24 to be transmitted. The processor agent can check the queue to see if there are more transactions in the queue that are addressing the same page (decision block 70 ). If additional transactions are in the queue, the transaction can be confirmed with the transmitted ("asserted") page hint signal (block 72 ). For example, the processor agent may use the results of the check queue, and in the time signal cycle, the processor agent decides to perform the address phase of the transaction to confirm the page hint signal (" assert ") or" deasserts "the page hint signal.

A processor agent may also be configured to determine if a repeating pattern of transactions is likely. For example, a processor agent may discover that it is in a loop of code, which makes additional transactions for the same page (s) as the current transactions more likely than if no loop were executed. When the processor agent detects a repeating pattern of transactions (decision block 74 ), then the processor agent can transmit the transaction with the acknowledged page hint signal (block 72 ) even if there are no other transactions on the same page as the transaction in the queue. In other cases, the processor agent may transmit the transaction with the deasserted page hint signal (Block 76 ).

While the 5 and 6 may represent the use of page hint indication by certain agents, any agent may also use the page hint indication in any other suitable manner.

7 is a block diagram of an exemplary agent 80 , Other embodiments are possible and contemplated. At the in 7 The embodiment includes the agent 80 a transaction queue 82 connected to a bus interface circuit 84 is coupled. The bus interface circuit 84 is in turn to the bus 24 coupled.

The transaction queue 82 can generally store the transactions made by the agent 80 on the bus 24 to initiate. The transaction queue 82 can receive the transactions made by the agent 80 generated internally (eg, a processor agent may generate transactions in response to the execution of load and store instructions), or the transaction queue 82 can receive the transactions from another external source (eg an input / output bridge) 20A - 20B can receive transactions from devices connected to input / output interfaces 22A - 22D ) are connected.

The bus interface circuit 84 includes the circuit for contacting the bus 24 , The bus interface circuit 84 In particular, it may transmit transactions to the bus that involve asserting or declaring ("assertion" or "deasserting") the page hint signal during the address phase of the transactions.

8th shows a block diagram of a carrier medium 300 with a database containing the system 10 represents. Generally speaking, a carrier medium may include storage media such as magnetic or optical media, disk or CD-ROM, volatile or non-volatile storage media such as RAM (eg, SDRAM, RDRAM, SRAM, etc.), ROM etc., as well as transmission media or transmission signals, such as electrical, electromagnetic or digital signals carried over a communication medium, such as a network and / or wireless connection.

In general, the database of the system 10 that are on the carrier medium 300 is a database that can be read by a program and used, directly or indirectly, to fabricate the hardware that makes up the system 10 includes. The database may include, for example, a behavior level description or a register transfer level (RTL) description ("behavioral-level description" or "register-transfer level") of the hardware functionality in a high-level programming language ("high level The description can be read by a synthesis tool that can assemble the description to produce a netlist that contains a list of controls from a The Netlist contains a set of controls that also represents the functionality of the hardware that the system provides 10 includes. The netlist may then be placed and routed to produce a dataset describing the geometric shapes to be applied to the masks. Subsequently, the masks may be used in different steps to fabricate semiconductors to form a semiconductor circuit or semiconductor circuits according to the system 10 to create. As needed, the database can be on the carrier medium 300 alternatively be the netlist (with or without synthesis library).

While the carrier medium 300 a representation of the system 10 As desired, other embodiments may include representation of any portion of the system as needed, including any combination of agent, memory controller, bus, memory, etc.

With the full study of the present disclosure, those skilled in the art will appreciate technology involved numerous variations and modifications. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims (15)

Circuitry that is configured to be initiated a first operation, with the circuit configured is that while the first operation is sent a page hint indication, the page hint indication indicates whether a page addressed by the first operation should remain open or not. The circuit of claim 1, wherein the page hint indication a signal is. Circuit according to claim 1, wherein the circuit is configured so that the page hint indication during a Address phase of the first operation is transmitted. Memory controller that is so coupled, a page hint indication received with a first operation, with the page hint indication indicates whether a page addressed by the first operation remains open should or not, where the storage controller is configured, the page that is coupled to the storage controller, depending on the page hint indication optionally open to hold. A memory controller according to claim 4, comprising a Configuration registers, which is configured to store a page mode policy where the memory controller is configured, the page also depending to be kept open by the page mode policy. The memory controller of claim 5, wherein the page mode policy a first policy in which the optional keep open the Page is determined by the page hint indication, and the page mode policy includes at least a second policy in which the optional keep open the page is not determined by the page hint indication. The memory controller of claim 6, wherein the second Policy is to close the page. The memory controller of claim 7, wherein the second Policy is to keep the page optional depending on from the operations made by the memory controller to one Receive time at which a column address accordingly the first operation is sent to the memory. The memory controller of claim 4, wherein the memory controller is configured to close the page when the page hint indication indicates that the page should be closed. The memory controller of claim 4, wherein the memory controller configured, the page is open to hold when the page hint indication indicates that the page open should stay. System comprising: a circuit after one the claims 1-3; and one A memory controller according to any one of claims 4-10. System according to claim 11 further comprising a second circuit, wherein the circuit is coupled to the page hint indication during the first operation provide, and the second circuit is coupled to the Page hint indication during a second operation initiated by the second circuit provide. Circuit-defining mechanism with one or several databases containing one or more circuits according to a of claims 1-3 or the memory controller according to a the claims 4-10 represent. Circuit-defining mechanism according to claim 13, wherein the one or more databases comprise one or more netlists that represent the circuit or the memory controller. Memory medium that defines the circuit Mechanism according to claim 13 contains.