DE2006565A1 - Plueric advance delay system - Google Patents

Description

Dr. rer. nat. Horst Schüler 2006 565 ₆ Frankfurt / Main, February 12, 1970

PATENT ADVERTISER Niddattraße 52 CH / WK / hÖ

Telephone (0611) 237220 Postscheck-Account: 282420 Frankfurt / M. Bank account: 523/3168 Deutsche Bank AG, Frankfurt / M.

1384-13D-11952

GENERAL ELECTRIC COMPANY

1 River Road
SCHENECTADY, NY / USA

Fluerian advance delay system

The invention relates to servomechanism systems, in particular a lag-lead network in such systems.

Often it is when designing servomechanism systems It is necessary to provide means for dynamic compensation in a control loop system so that it remains stable while remaining Stability allows a higher control gain factor, or a desired response time characteristic for one has variable control input. One such compensation network is a delay-lead circuit which have a lead time constant and a

009836/1423

slightly longer delay time constant is inserted. The network-, werk is connected in series with the system to be controlled and its control elements. The system to be controlled has a delay with a large time constant, then the compensating delay-lead circuit usually has to have a have even greater delay time constants. Since the time constant is defined as the product of a resistance and a capacitance, it is evident that there is a correlation exists between these two sizes. When the resistor producing the time constant is connected in series with the input is, as is usual with the circuits known since then, then there are two possibilities. The first option consists in the use of a large series resistor and a capacitor with a practical size of its volume, which at the same time leads to a loss in the forward gain of the overall control loop. There is a second possibility in choosing the size of the resistor so that the control gain is maintained and an excessively large volume which represents the capacitance needed to produce a large delay time constant.

Are means connected in series for generating the delay reserve function is used and the series resistance of the puncture generator is kept at a relatively low value, Another problem may arise in that the delay hold-in circuit changes the characteristics of the it can affect the feeding control device.

One method of reducing the secondary effect on the feed device is to create a resistance between the output of the feed device and the input of the delay hold-in circuit to switch, which effectively isolates the two from each other. However, if this is a Taken delay-lead circuit in which the time constant is generated in the forward branch, this results in an additional Reduction of the forward gain of the control loop.

009836 / U23

With regard to the above problems in connection with a delay-lead circuit in the forward branch of a control loop It is one of the objects of the invention to provide a delay advance circuit which has large delay time constants can generate without thereby reducing the overall forward gain of the control system.

Another object is to provide a delay lead circuit provide in which the dynamic values can be isolated from the input of the circuit without doing so the forward gain of the control loop in which the circuit is inserted is adversely affected.

The delay-lead circuit according to the invention therefore has, according to the invention, an amplifier with an amplifier connected thereto Input and output on, as well as a positive feedback, which connects the output to the input, where the Feedback branch at least two feedback resistors has, which are connected in series, and a grounded capacitor, which is at a point between the connected to both resistors.

The invention is explained in more detail below on the basis of exemplary embodiments. The drawings show:

in Fig. 1 a typical fluidic amplifier partially shown in section,

in FIG. 2 a schematic representation of the one shown in FIG fluidic amplifier,

in FIG. 3 a circuit diagram of the Fluerian delay-advance circuit according to the invention,

in Fig. ¹ I is an electric circuit diagram of a circuit according to the fluerischen 3 analog electrical scarf Fig. ^tung> 0Q9836 / U23

in Pig. 5 is a block diagram of the circuits according to FIGS. 3 and Ί,

in Fig. 6 is a graph showing the attenuation-frequency characteristic the delay-lead circuit according to the invention shows and

in Fig. 7 is a block diagram of a control system for a method or apparatus in which the Fluerische delay-lead circuit is used according to the invention.

In Fig. 1, a typical single-stage fluidic amplifier is shown, which can be constructed in a known manner. The amplifier comprises a base 10 in which the various passages and cavities described below are formed, and a cover portion 12 which is attached to the base 10 by adhesive, screws or other means to close the passages and cavities of the base 10 and to seal against each other. The lower part 10 comprises an inflow slot 1Ί through which the pressurized, the power delivering fluid medium (motive fluid) flows in, a working nozzle 16, a guide chamber 18 at the outflow opening of the working nozzle 16, control slots 26 and 28, which are slightly downstream of the Working nozzle 16 arranged and directed opposite to each other on the center line of the working ^{nozzle, vent slots 2 1} J and receiver ££) and 22. In the absence of a signal consisting of a pressure difference between the control slots 26 and 28, a flow emerging from the working nozzle is in equal parts recorded by the receivers 20, 22. However, if there is a pressure difference between the two slots 26 and 28, the working current is deflected so that one of the receivers 20, 22 has a greater pressure increase than the other slot, the pressure difference between the receivers 20, 22 being proportional to the pressure difference between the Control slots 26 and 28. In this way, a small pressure difference between the control slots 26 and

009836 / U23

28 can be amplified into a greater pressure difference between the receivers 20 and 22. Devices such as those shown in Fig. 1 can be used solely for such reinforcement purposes or several stages connected in series are used, the pressure difference between the receivers 20, 22 of the one stage forms the input for the control slots 26, 28 of the following stage.

FIG. 2 shows a schematic illustration of the fluidic amplifier according to FIG. 1. The elements of the schematic illustration are provided with the corresponding reference numbers like same physical elements according to FIG. 1. In FIG. 2, the control slots 26 and 28 are shown as resistors, which represent the flow resistance of the actual control slots, the reason for this from the following description becomes clear.

3 shows a fluidic delay-lead circuit according to the invention, which has the fluidic amplifier 11 described above. (Although only a single fluidic amplifier stage is shown in FIG. 3, the amplifier part of the fluidic delay-lead circuit can also have a multi-stage amplifier block which is made up of several of the amplifiers 11 described above in cascade connection.) The circuit also includes input resistors 34 and 36 interposed in input lines 30 and 32, summing junctions 38 and 40 which combine the input flows with the feedback flows from lines 46 and 54, lines 42 and 44 through which the combined input and feedback flows to control slots 26 and 28 of the fluidic amplifier 11 flow, output lines 66 and 68, which are connected to the receivers 20 and 22 of the fluidic amplifier, the previously mentioned feedback lines 46 and 54, feedback resistors 48 and 52, which are connected to the line 46 between

009836/1423

are connected, feedback resistors 56 and 66, which are interposed in the line 54, capacitances or volumes and 58, which are on the one hand in the line 46 between the resistors 48 and 52 and on the other hand in the line 54 between the Resistors 56 and 60 are interposed (an equivalent capacitive connection is / with a lead at one point dead volume connected between resistors 56 and 60), and a trim resistor 62 connecting output line 68 to output line 66. Also are the resistors 62 and 64, which represent the flow resistances of the receivers 20 and 22, are shown schematically.

Resistors 34, 36, 48, 52, 56 and 60 are preferred laminar flow resistances, which have an almost linear pressure drop-flow characteristic exhibit. Each of the resistances can be formed by a long, narrow passageway, such as a capillary tube or a rectangular passage of narrow cross-section through a block of material, which can for example consist of plastic or metal. However, it can also be formed by flow openings Resistors are used.

The size of the resistors 34, 36 depends on various facts fools off. This includes the desired degree of isolation between the output of the delay-lead circuit feeding device and the dynamic components of the circuit itself and, on the other hand, the desired transmission factor.

The resistors 48, 56 are of the same size and somewhat larger compared to the resistance R of the control slots 26, 28 and to the resistance R _{Q of} the resistors 62, 64.

In this way, the size of the positive feedback to the control slots is limited to a smaller amount than that of the inlet flow through the lines 3O ₁ 32 and the outlet

009836/1423

initial flow through the lines 66, 68. The feedback takes place at one branch via the line 46, which is connected at one end to the output line 66 and at its other end via the line 42 to the control slot 46 and in the other branch via the same connecting line 54. The resistors 52, 60 have resistors R- ¹ , which are equal to one another and can be greater or smaller than the resistance R- of the resistors 48 and 56. The capacitors 50, 58 have the same capacities C. These capacitances can can be formed in a simple manner by widening the cross-section in the lines 46, 54.

The resistance R of the variable resistor 62 can, for example formed by a parallel set of fixed resistances with laminar flow and means by which optionally any group or individual of these parallel-connected resistors can be switched on or off. Of the Resistance range of the variable resistor 62 is chosen so that the delay-lead circuit is within certain Limits of the impedance of the output lines 66, 68 connected load can be adjusted. The requirements for such adjustment will be described later.

The operation of the invention will be understood from the description of FIGS. 4-6. Fig. 4 shows an electrical Analog circuit of one side of the Fluerian circuit shown in FIG. 3 (the circuit of FIG. 3 shows a Push-pull circuit, which can be analyzed by analyzing only one side). In Fig. 4 the elements (resistors, Capacitances, summation points and lines) are provided with the reference numerals corresponding to FIG. 3, where in 4, a resistor 74 (denoted by Rj.) Is additionally added which represents the load on the circuit at the output.

009836/1423

The circuit of FIG. ¹ I can radio-ti ons are moderately defined by the in FIG. Block diagram shown in Figure 5, which corresponds to summing the summing point 38, and wherein Q, G and the like. H are defined by:

⁰ I ^{= e} a ^{/ e} i

^G = ^e o ^{/ e} b

^{H = e} a ^{/ e} o

^e a = ^e b

fe With a Laplace's transformation of the parameters the following applies:

G ₁ - (S) = E _a (S) / E. (S)

G (S) = E _o (S) / E _b (S)

• H (S) = E _a (S) / E ₀ (S)

The term H (S) can be referred to as the product of a static term and a transient term, where the static term is the DC gain of the element and the transient term is of the form (1 + T ₁ S) Z (I + T ₃ S) accepts.

fc In Fig. 4, each of terms GjfG and H can be derived by considering the impedances with respect to ground for each input signal e ·, error signal e. and output signal e _Q. The path of the signal e. to ground runs through resistor 3 ¹ * and then through the parallel branches. The parallel branches consist, on the one hand, of resistor 26 and, on the other hand, of resistors 48, 52 and capacitor 50 (point 70 is considered to be grounded for the purpose of analysis with respect to signal e., Inasmuch as R _Q , which is back leads to the guide chamber 18, and the resistance R _T in the real fluidic system are very much smaller than the series resistance R _f ). The way follows the same line of evidence

009836 / U23

for the signal e, to the ground through the amplifier 11, the output resistance R _{0 of} the fluidic amplifier (resistor 70) and the parallel branches, which on the one hand consist of the resistors R ^ and Ry and on the other hand the feedback line consisting of the resistors R «, RJ and the capacitance C, exist. Similarly, the path of the signal e _Q to ground includes the resistors R _Q , Ry and R _L , which are parallel to each other and to the feedback line, which consists of the resistors R |., R _f ^! and the capacitance C exists. If one considers the case that the path formed by the resistor 62 (resistor Ry) is cut off (the puncture and effect of the resistor 62 will be described later), the following expressions can be derived _{for G 1, G and H:}

G ₁ (S) = G (S)

1 +

1 +

H (S)

(R-. + R ") (R. + RJ

■ i »X * L C.

1 +

^R i ^R c

^R f ^f

R _f '

(R _f C)

Equation (4) assumes a real fluidic system in which R- + R '»R or R is _T or R.

IIC L O

In Fig. 5, the expressions ΔP, Δ? _± substituted for their electrical analogies E _Q (S), E ₁ (S).

The expression P / ΔΡ. is determined by the relationship

009836/1423

- ίο -

Λ P,

KS) G (S)

1 - G (S) H (S)

This equation can be created by dividing each of the individual threshing floors into the static factors I-, G and Η_ and the vibration factors Iy, G "and H" are reduced to

¹ D ⁰ D

- ^G D ^H D

V ¹ - ^g d ^h d /

This equation includes delay and lead terms, their Time constants depend on the relationships according to the equation

To illustrate the effect of various R _f / R 'ratios and GH factors, the values of the resistance and capacitance that actually occur in fluidic devices are listed below:

R = 2 »lake = 2 lake
^C 5

_in

(0.251 m) ^J.

2 sec
5 (0.251 m) ⁵

_in

+ R. » = 1000

= 1000

in ¹

(0.25 ¹ I.

^R L = ²

lake

(0.251 m) ⁵

C =

= 0.8

Using these values results in a Bode diagram according to Fig. 6, on whose ordinate the frequency (the reciprocal of the time constant) and on whose abscissa the ratio

009836 / U23

ratio AP _o / AP _i in decibels (1 db = 20 log ₁₀ (4P _Q MP _i )) is plotted. The strongly drawn curve of the frequency response or the damping curve 76 represents the case in which R _f = R _f 'and 1-GH = 0.05. The damping curve 78 applies to the case where R _f / R _f '> 1 and 1 - GH = 0.05 and the damping curves 80, 82 represent the cases R _f / R _f ' = 1 and 1 GH = 0.03 and 0.1 respectively. It can be seen from FIG. 6 that, for a given circuit, the frequency at which the corresponding delay and lead interruptions (break) occur changes by changing the ratio between R- and R- ¹ can be. The frequency range between the delay and the advance interruption can be changed by changing the GH factor. The above equation (2) shows that the GH factor can be changed by changing the gain factor A, as well as by changing the number of fluidic amplifier stages and / or by adding additional resistors in series with resistors 62, 64.

Fig. 7 serves to explain the application of the circuit according to the invention and to facilitate the explanation of its various advantages. This is a schematic representation of the feedback system for regulating a process or a machine. The letter I denotes an input that represents the desired value of a controlled variable (setpoint), the letter 0 denotes the controlled variable (actual value) and E denotes the signal that represents the error in the controlled variable (control deviation). The Elock labeled G, (S) represents the transfer function of the control module and the frequency response of the controlled system for the correction processes and includes the static and settling terms. The large block contains the defined transfer function which is represented by the delay-lead circuit according to the invention. The input transfer _{factor is denoted by K 1} and the feedback factor by H, (S).

009836 / U23

The system to be controlled can have such a characteristic that the product [J}, (S) J jj, (S)] contains transients "", which make it necessary to provide a compensation circuit in order to keep the control loop of the system stable with useful forward gains at low frequencies. In many In some cases, a delay-lead network can be used in series with the rest of the system »like this one is described and claimed in order to obtain the necessary compensation. The delay-lead circuit is also used to increase the gain of the open-loop control ^ to increase at low frequencies, so that the accuracy of the "transmission with closed control loop is improved. If the system to be controlled contains a delay with a large Time constant, then the compensating delay-lead circuit usually has an even larger delay time constant. Since the time constant is defined by a Product of a resistance and a capacitance, it is evident that there is a correlation between these two consists. If the resistor producing a time constant is connected in series with the input, the possible choice is once the use of a large series resistor with a practical volume size or capacity, what at the same time to a decrease in the forward gain of the control loop | leads, or second, the size of the resistance is so too choose that the rain gain is at a sufficiently large Value remains and there is then a very large volume to be used, which has the capacity required to generate a represents a large time constant for the delay. The circuit according to the invention avoids this correlation by generating a time constant in a positive feedback path with a large resistance, without the static transmission factor of the control loop in which the delay-lead circuit is used, can be reduced would. Aif this way is going to use a capacitor with a reasonable volume size.

009836 / U23

An analysis has shown that for comparable types and numbers of components, equivalent circuit impedances, the same time constants and the same relationships between the delay urgs- and the lead time constants, the circuit according to the invention shows an advantage in the capacity volume of 4800: 1. As the above equation (5) additionally shows, the circuit according to the invention can amplify its input signal, while a very large time constant is provided by varying the factors ßr »H _D and Ι ~ (see the above equations 1-3).

Additional advantages in the circuit according to the invention result from the amplification of the input signal according to the element I _D G _D / (1-Gj ₅ H ₀ ). As equation (1) above shows, I _{D is} the inverse function of R., the resistance of the input resistors 3 **, 36. In the design, there is therefore the choice of _{increasing R. at the expense of I Q} and thus at the expense of Gain factor IjjGp / Cl - Gj) H ₀ ) of the delay-lead circuit, so that the device feeding the delay-lead circuit is more effectively isolated from the dynamics and the positive feedback path of the delay-lead circuit. This technique, of course, requires a loss in the gain of the circuit. However, should the loss be detrimental to the operation of the overall system, it can be compensated for by adjusting the gain K ^ according to FIG. 7 or by changing the (1 - GpH) factor, as far as the dynamic behavior of the system allows. In comparison to known delay-lead control loops with equivalent amplification factors and time constants, the circuit according to the invention enables the input resistance R. to be increased by 100: 1.

Equation (2) gives me the purpose and you the effect of the variable resistance 62 «In equation (2) that is

Term Rq / (R _f * RJ) less than 1 _% because in a wirKÜchen 0 9 Ö 4 G '' i 4i 4

System R _{f is} considerably larger than R _Q. For equation (2) is therefore approximate

(6) G (S) = A / (l ₊ R _Q / R _L ).

Depending on the load on the delay-lead circuit according to FIG. 3, the element R. / R. can be significantly less than 1, which leads to a value of G (S) which approximates A. R _Q / R _L could also assume a value equal to or greater than 1, which leads to the result that G (S) assumes a value fc which is significantly smaller than A. As can be seen from equation (5), it could be result in a negative time constant T "/ (l - G _D ^H _D ) when the circuit is on

a burden which is very different from that

en
provided / load, which can lead to an unstable operating behavior of the entire control circuit according to FIG. Since in practice it is not always possible to accurately predict the load impedance in a circuit, or if it is desired to use the circuit on a load for which it is not intended, it is desirable to provide means for the circuit there adapt.

If equation (6) is corrected by inserting the effect of the resistance W stand 52, the result is approximately

I ₊ R ₀₊ R ₀

G (S) =

The circuit can therefore be designed so that it operates at a particular value of R_ / R, which includes a value of the load resistance R _{T which is certainly underestimated.} If it is found that R ,. is higher than estimated, the value vcn G (S) can be adjusted to the load by reducing R ^. Here, K ₀ ZRy increases to one

00333S / U23

Value which is sufficient to correct the error in the estimated R i and to keep the operation of the entire control loop at the estimated value of G (S). So all that is required is a simple adjustment or tuning.

009836 / U23

Claims (7)

- 16 -patent claims 1. Delay / lead circuit, characterized by a functional amplifier (11) with input means (3O ₁ 32, 42, 44, 34, 36) connected to the input of the amplifier and output input In (66, 68), as well as positive feedback means (46, 54) connecting the output means to the input means, these feedback means having at least two series-connected feedback resistors (48, 52, 56, 60) and one connected to ground ^ Capacitor (50, 58) have one side connected at a point between the two resistors. 2. A circuit according to claim 1, characterized in that the functional amplifier is a fluidic amplifier (11) with at least one amplifier stage, the input means from two input lines (30, 42, 32, 44) exist, each of which is connected to a control slot (26, 28) of the amplifier (11) and which are adapted for connection to an external source of fluid, the output means comprising two lines (66, 68), each of which is sent to a recipient (20, 22) "of the amplifier is connected and the one to be connected to an outer layer (74) are formed and wherein the feedback means comprises a feedback line (46, 54) which connects each output means (66, 68) to the corresponding input means (42, 44) and a forms positive feedback, each feedback line (46, 54) having the series-connected resistors (48, 52, 56, 60) and the grounded capacitor (50, 58) which is connected to a point between the two resistors. 009836 / U23 3. A circuit according to claim 2, characterized in that the capacitor connected to ground (50, 58) two equal dead volumes and one of each of the volumes with only one of the feedback lines (5 **, 46) connecting Having line, the line in the feedback line between the resistors (48, 52, 56, 60) flows out. 4. A circuit according to claim 3, characterized in that the grounded capacitor (50, 58) consists of two equal volumes, each of the feedback lines (46, 54) having one of these volumes between the feedback resistors (* I8, 52, 56, 60). 5. Circuit according to claim 4, characterized that the input means consists of a fluidic input resistance (34, 36) in each of the input lines (30, 32), which is connected to the input line before the feedback line (46, 54), wherein the resistors (34, 36) have the same flow resistance. 6. Circuit according to claim 5, characterized that the input resistors (34, 36) and the feedback resistors (48, 52, 5β, 60) of devices be formed with laminar flow. 7. A circuit according to claim 6, characterized in that a variable trimming resistor (62) is connected between the output lines (66, 68). 003336 / U 2 3