DE20019477U1 - Semiconductor chip for optoelectronics - Google Patents

Description

The invention relates to a semiconductor chip for optoelectronics with an active layer which has a photon-emitting zone and which is attached to a carrier body on a fastening side.

Such semiconductor chips produced using thin-film technology are known from EP 0 905 797 A2. To produce the known semiconductor chip, an active layer is usually applied to a substrate using an epitaxy process. A carrier body is then attached to the top of the active layer and the substrate is removed. A metallic reflection layer is advantageously located between the carrier body and the active layer so that no light is absorbed by the carrier body. The known semiconductor chips are particularly suitable for applications in which high optical performance is required.

A disadvantage of the known semiconductor chips produced using thin-film technology is that the metallic reflection layer arranged between the carrier body and the active layer generally does not have satisfactory reflectivity at short wavelengths. In particular, at a wavelength of less than 600 nm, gold is the only material that can be used for the metallic reflection layer.

In addition, large areas such as the metallic reflective layer are difficult to bond. Bonding and alloying of the metallic contact layer also generally impairs the quality of the metallic reflective layer.

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Furthermore, from DE 198 07 758 Al a truncated pyramid-shaped semiconductor chip is known which has an active, light-emitting

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zone between an upper window layer and a lower window layer. The alignment of the side walls means that light striking the side walls is totally reflected and strikes the surface of the semiconductor element at almost a right angle. As a result, part of the light emitted by the active zone hits the surface within the exit cone of the semiconductor element. In order to lead to a significant increase in the light output, this concept requires a minimum thickness for the upper and lower window layers. In the known truncated pyramid-shaped semiconductor element, the thickness of the upper and lower window layers is at least 50.8 μηη.

Based on this prior art, the invention is based on the object of creating a semiconductor chip that can be produced using thin-film technology and has improved light extraction.

This object is achieved according to the invention in that the active zone is interrupted by a recess made in the active layer from the fastening side, the cross-sectional area of which decreases with increasing depth.

The recesses allow the fastening side of the semiconductor chip to be made significantly smaller, so that the active layer can be bonded to the carrier body without any problems. The recesses also create side surfaces on which some of the photons emitted by the active zone are reflected in such a way that the photons within the exit cone impinge on the exit surface of the active layer opposite the fastening surface. In the semiconductor chip according to the invention, the reflection on the continuous reflection layer is, to a certain extent, replaced by the reflection on the side surfaces of the recesses.

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In a preferred embodiment of the invention, elevations are formed on a connecting layer of the active layer by the recesses.

Such elevations act as collimators that align the trajectories of the photons emitted from the active zone almost at right angles to the exit surface of the semiconductor chip. As a result, a large proportion of the emitted photons hit the exit surface within the exit cone and can leave the semiconductor chip.

In a further preferred embodiment, the connecting layer is designed such that at least one trajectory of the photons emitted by the active zone leads from the respective elevation to one of the neighboring elevations.

Due to the optical coupling of the elevations, photons that have not been reflected on one of the side surfaces of the original elevation can reach one of the neighboring elevations and be reflected there on the side surfaces of the respective elevation in such a way that they hit the exit surface within the exit cone.

Furthermore, in an advantageous embodiment of the invention, the elevations are equipped with concave side surfaces.

Through these measures, photons that are initially reflected at the exit surface are increasingly aligned with each subsequent reflection on the side surface of the elevations, so that they finally hit the exit surface within the exit cone.

In a further preferred embodiment, the elevations are covered with a reflective layer.

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This measure directs all light rays hitting the side surface of the elevations towards the exit side of the semiconductor chip.

Further advantageous embodiments are the subject of the dependent claims.

The invention is explained in detail below with reference to the accompanying drawings. They show:

Figure 1 shows a cross section through a semiconductor chip according to the invention;

Figure 2 shows a cross section through a further embodiment of a semiconductor chip according to the invention,

in which the active zone is arranged within truncated pyramid-shaped elevations;

Figure 3 shows a cross section through a semiconductor chip according to the invention, which is equipped with elevations,

which have concave side surfaces; and

Figure 4 is a diagram showing the increase in light output of the semiconductor chip according to the invention compared to conventional semiconductor chips.

The semiconductor chip shown in Figure 1 has a carrier body 1 on which the active layer 2 is applied. For the sake of clarity, the thickness of the active layer 2 is exaggerated in relation to the thickness of the carrier body 1 in Figure 1. The active layer 2 has a photon-emitting, active zone 3, which is formed in elevations 4 at a medium height. The elevations 4 can be truncated pyramid-shaped or truncated cone-shaped.

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The elevations 4 are arranged on a connecting layer 5, which has a central front-side contact point 7 on a flat front side 6, which is formed by a metallization layer. The rear elevations 4, formed by recesses 8, are covered with a reflection layer, which consists of a dielectric insulating layer 9 and a metallization layer 10 applied thereto. The insulating layer 9 is interrupted along a base area 11 of the elevations 4 by vias 12, which are formed by metallized sections.

To produce the semiconductor chip shown in Figure 1, the active layer 2 is first grown epitaxially on a base substrate. The active layer 2 can be produced, for example, on the basis of InGaAlP. The connecting layer 5 is first formed on the base substrate and then doped with a concentration above 10 ¹⁸ cm" ³ in order to ensure good conductivity of the connecting layer 5. Good conductivity of the connecting layer 5 is a prerequisite for a central contact point 7 on the front side 6 to be sufficient to supply the active zone 3 with current. In addition, the composition of the connecting layer 5 is selected such that it is transparent to the photons generated in the active zone. This can usually be achieved by adjusting the band gap through the composition of the material of the connecting layer 5.

Then a further layer is applied to the connecting layer 5, into which the elevations 4 are introduced using suitable wet or dry chemical etching processes. Such etching processes are known and are not the subject of the application. The elevations 4 are preferably formed in the areas intended for the semiconductor chips. These are areas with typical external dimensions of 400 x 400 μm ² . The elevations 4 have external dimensions that are in the range of the layer thickness of the active layer 2. The

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The external dimensions of the elevations 4 are therefore in the range of 10 μm.

In a further process step, the insulating layer 9 is deposited on the elevations 4 and the vias 12 are formed. The metallization layer 10 is then applied.

The active layer 3 is then separated according to the intended number of semiconductor chips. This is done, for example, by wet etching.

Then the isolated active layers are attached to the carrier body 1, for example by eutectic bonding, and the base substrate is removed by wet etching. Finally, the contact points 7 are formed on the exposed front side of the active layer 2 and the semiconductor chips are isolated by separating the carrier body 1.

The semiconductor chip shown in Figure 1 has the advantage that the photons generated by the active zone 3 do not hit components of the semiconductor chip, which absorb them. This is because the metallization layer 10 keeps the photons away from the carrier body 1.

A further advantage is that in the semiconductor chip of Figure 1, a large proportion of the photons emitted by the active zone 3 are totally reflected at the side surfaces 13 of the elevations 4. The photons totally reflected at the side surfaces 13 strike the front side 6 at a large angle. In particular, a portion of the photons that would be totally reflected at the front without reflection at the side surfaces 13 strike the front side 6 within the exit cone and can therefore leave the semiconductor chip. In the semiconductor chip according to Figure 1, the reflection at the continuous base surface known from the prior art is therefore at least partially compensated for by the total reflection at the

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side surfaces 13. Therefore, the semiconductor chip from Figure 1 has a light yield that is increased by a factor of almost 2 compared to conventional semiconductor chips without recesses 8.
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The described effect will be explained in detail below using the further embodiments shown in Figures 2 and 3.

Consider a series of light rays, whereby the term light rays should not be understood as a restriction to a specific wavelength, but as a reference to the methods of geometric optics, independent of the wavelength.

In the embodiment shown in Figure 2, the elevations 4 are truncated pyramid-shaped and are only attached to the base surface 11 of the elevations 4 via a contact layer 14 on the carrier body 1. The active zone 3 is supplied with current through the contact layer 14.

Due to the large difference between the refractive indices of semiconductors and casting resin, from 3.5 to values between 1.5 and 2, only light rays that hit the interface within an exit cone with an opening angle of about 16° can be coupled out of the semiconductor at the interface between semiconductor and casting resin. If the light rays are distributed evenly in terms of angle, this corresponds to about 2% of the light rays incident on a unit area.

The elevations 4 direct the light rays emanating from the active layer 2 in the direction of the front side 6. The elevations 4 therefore act as collimators, in whose focal surface the active zone 3 is located. The elevations 4 cause the light rays impinging on the side surfaces 13 to be directed in the direction of the front side 6.

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and hit within the exit cone so that they can leave the semiconductor chip. The light output can be optimized by a suitable choice of the dimensions of the base area 11, the angle of inclination of the side area 13 and the height of the elevations 4 as well as the position of the active zone 3.

Figure 2 shows a light beam 15 that is initially totally reflected at the side surface 13 and from there directed to the front side 6. On the front side 6, the light beam 15 hits the interface within the exit cone and can therefore leave the semiconductor chip. Without the total reflection at the side surface 13, the light beam 15 would have been totally reflected at the front side 6 and directed back to one of the reflection layers known from the prior art, where it would have been reflected again. In this respect, in the embodiment shown in Figure 2, the reflection at the conventional continuous reflection layer is replaced by the reflection at the side surfaces 13.

This also applies to a light beam 16 that is first reflected at the base surface 11 and then at the side surface 13. The light beam 16 is also directed to the front side 6 after the second reflection, where it impinges within the exit cone. Without the reflection at the side surface 13, the light beam 16 would also have been totally reflected at the front side 6 and directed back to a rear reflective layer.

It is also advantageous that the elevations 4 are optically coupled via the connecting layer 5. In this context, optical coupling is to be understood as meaning that at least one of the light beams emanating from the active layer 2 can pass over a center line 17 from the area of one of the elevations 4 into the area of one of the neighboring elevations 4. This is because the optical coupling with the aid of the connecting layer 5 enables a light beam 18,

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which does not strike one of the side surfaces 13 of the respective elevations 4, strike one of the side surfaces 13 of one of the adjacent elevations 4 and are directed there to the front side 6, where it strikes within the exit cone. The light yield is therefore further increased by the optical coupling via the connecting layer 5.

Finally, Figure 3 shows a cross-section through a modified embodiment of the semiconductor chip, in which the elevations 4 are truncated cone-shaped with concave side surfaces 13. The design of the side surfaces 13 means that a light beam 18 reflected back and forth between the front side 6 and the side surface 13 is increasingly aligned as it approaches the center line 17 until it strikes the front side 6 within the exit cone. The same applies to light beams 9, which initially pass from one elevation 4 to the neighboring elevation 4 via the connecting layer 5 and are brought there at a large angle to the front side 6.

Finally, Figure 4 shows a diagram in which a measurement curve 20 shows the dependence of the light output in relative units on the operating current in pulsed operation for a conventional light-emitting diode produced using thin-film technology. A further measurement curve 21 illustrates the dependence of the light output in relative units on the operating current for a light-emitting diode according to the embodiment shown in Figure 3. It can be seen from Figure 4 that the light output in the embodiment shown in Figure 3 is approximately twice the light output of conventional semiconductor chips without recesses 8.

Claims (13)

1. Semiconductor chip for optoelectronics with an active layer ( 2 ) which has a photon-emitting zone ( 3 ) and which is attached to a carrier body on a fastening side ( 11 ), characterized in that the active zone ( 3 ) is interrupted by a recess ( 8 ) made in the active layer ( 2 ) from the fastening side ( 11 ), the cross-sectional area of which decreases with increasing depth. 2. Semiconductor chip according to claim 1, characterized in that elevations ( 4 ) are formed on a connecting layer ( 5 ) of the active layer ( 2 ) by a plurality of recesses ( 8 ). 3. Semiconductor chip according to claim 2, characterized in that at least one trajectory ( 18 ) of the photons emitted by the active zone ( 3 ) leads from the respective elevation ( 4 ) to one of the adjacent elevations ( 4 ). 4. Semiconductor chip according to claim 2 or 3, characterized in that the elevations ( 4 ) taper towards the carrier body. 5. Semiconductor chip according to claim 4, characterized in that the elevations ( 4 ) have concave side surfaces ( 13 ). 6. Semiconductor chip according to one of claims 2 to 5, characterized in that the elevations ( 4 ) are truncated pyramid-shaped. 7. Semiconductor chip according to one of claims 2 to 6, characterized in that the active zone ( 2 ) is arranged at a medium height in the elevations ( 4 ). 8. Semiconductor chip according to one of claims 2 to 7, characterized in that the connecting layer ( 5 ) is transparent to the photons emitted by the active zone ( 3 ). 9. Semiconductor chip according to one of claims 2 to 8, characterized in that the connecting layer ( 5 ) is highly doped. 10. Semiconductor chip according to one of claims 2 to 9, characterized in that the elevations ( 4 ) are covered with a reflection layer ( 9 , 10 ). 11. Semiconductor chip according to claim 10, characterized in that the reflection layer has a metallization layer ( 10 ) underlaid with an insulating layer ( 9 ). 12. Semiconductor chip according to one of claims 1 to 11, characterized in that the active layer ( 2 ) has a thickness of less than 50 µm. 13. Semiconductor chip according to claim 12, characterized in that the active layer ( 2 ) has a thickness of less than 30 µm.