DE19961228A1 - Switch-mode converter power supply, uses resonant elements with element voltage being compared with threshold during pre-switching zero-voltage phase, to assess inductive or capacitive load connection - Google Patents

Abstract

The inventive circuitry includes an assembly (5), outputting voltage (U2) to load, and containing resonant elements (Cr, Lr), used for processing DC voltage (U3), derived by chopping input voltage (U1) with resonant circuit elements (S1, S2), which have alternating switch-on phases. In order to monitor a connected load, before elements (S1,S2) are switched on, applied voltages (US1) or (US2) are compared during a zero-voltage phase with a threshold, to determine whether a connected load is inductive or capacitive. In an alternative embodiment, the differentials of voltages (US1,US2) are compared with a predetermined value to assess whether the load is inductive or capacitive.

Description

The invention relates to a converter with switching elements for chopping an equal voltage, with the switching phases of the switching elements alternating, and with one processing the chopped DC voltage and for supplying one Output voltage serving circuit structures with resonant circuit elements.

Such load-resonant converters are preferably switched-mode power supplies that are used for DC voltage supply for a load connected to the output of the switching power supply serve. In the case of switching power supplies of this type, there is first a contact on the input side AC voltage rectified to obtain a converter input DC voltage. However, the invention is also intended to relate to converters on the input side of which one DC voltage is supplied directly from a DC voltage source. Is also a Use of such a converter for the operation of gas discharge lamps possible. The DC input voltage is generated by means of a switching element Bridge circuit chopped. The chopped DC voltage becomes a circuit structure with resonance circuit elements, d. H. with inductive and capacitive Reactive resistance components fed so that in the circuit structure when operating in an approximately sinusoidal alternating current flows in the vicinity of the resonance frequency. At least one inductive and at least one capacitive resonant circuit element must be to be available. Output side of the circuit structure and thus the output side of the A load can be connected to the converter. By adjusting the switching frequency will adapt to load changes and input voltage fluctuations performed. Converter with resonant circuit elements, d. H. resonant converter, enable operation with high switching frequencies of the switching elements and thus the Realization of relatively small volume and compared to the possible power output light devices. When using resonant converters, in particular, a So-called ZVS operation (Zero Voltage Switching) with little switching effort enables. ZVS operation here means switching on the switching elements (transfer to the conductive state) with the smallest possible switching element voltage, preferably in  Close range of zero volts. In ZVS operation, the circuit structure with the Resonance circuit elements one viewed from the side of the switching elements inductive Input impedance. In the case of ZVS operation, MOSFET Transistors used as switching elements. In the case of converters implemented in this way, the Avoid operation with capacitive load. Such a converter operation leads to increased Switching losses and can even destroy the converter switching elements. It is therefore known to use means for determining such load-resonant converters the type of converter load (inductive or capacitive).

EP 0 430 358 A1 describes a converter circuit arrangement for gas discharge known lamps in which such a determination of the type of converter load is provided is. The circuit arrangement contains a half bridge with switching elements for Chopping a DC voltage. At the exit side of the half bridge is a Circuitry arranged with resonant circuit elements, for power supply serves as a discharge lamp. Operation with capacitive converter loading is also intended here be avoided. To do this, the phase difference between that of the circuit structure supplied voltage and the current flowing into the circuit structure indirectly monitored by monitoring the current flowing into the circuit structure.

The invention is based on the object in the converter mentioned at the beginning others with as little switching effort and as little measurement loss as possible propose the type of converter load monitoring to be implemented.

The object is achieved in that the is provided during a dead time phase Derive the voltage applied to a switching element, and with the help the determined derivation to determine whether an inductive or capacitive converter load is present.

Alternatively, it is also possible to use a time average for the amount of the derivative to determine the voltage applied to a switching element and this for comparison to use. In this way, complex phase difference measurements are avoided. No loss of current measurements are required. The  Measurement / evaluation of the derivation of a voltage is by means of integrated circuits easy to implement. If necessary, with an undesired type of converter load For example, normal converter operation was aborted and a new start sequence be initiated.

In one embodiment of the invention it is provided that the derivation is evaluated the voltage applied to a switching element is provided for each dead time phase and the comparison with the threshold value before switching on one of the switching elements done, d. H. it becomes cycle-by-cycle monitoring of the type of converter load carried out. The period of time until the detection of an unwanted The converter operating state is kept as small as possible in this way.

The invention also relates to a correspondingly designed control unit, in particular an integrated circuit for controlling at least one of the Converter switching elements.

Exemplary embodiments of the invention are described in more detail below with reference to the drawings explained. Show it:

Fig. 1 is a block diagram for a circuit arrangement including a resonant converter,

Fig. 2 shows the circuit structure of a resonant converter according to the invention,

Fig. 3 a time chart for an inductive load,

Fig. 4 time curves for a capacitive load,

Fig. 5 is a block diagram of a control circuit for controlling the switching element,

Fig. 6 shows a transfer function as a function of frequency for a constant load resistance and

Fig. 7 is a flow chart for explaining a converter operation according to the invention.

The block diagram shown in FIG. 1 shows a load-resonant converter - here a switched-mode power supply - with a circuit block 1 for converting a DC input voltage U1 into an output voltage U2 - here a DC voltage - which is used to supply a load represented by a block 3 . The input voltage U1 is generated here in the manner customary for switched-mode power supplies by rectifying an AC voltage of an AC voltage network.

FIG. 2 shows the essential elements of the converter according to FIG. 1 in a more detailed manner . The input DC voltage U1 is applied here to a half bridge of switching elements S1 and S2 connected in series, which chop the DC voltage U1. In the present case, the switching elements S1 and S2 are MOSFET transistors which have so-called body diodes D1 and D2, which are each shown as a diode lying antiparallel to the corresponding switching element S1 or S2. The switching elements S1 and S2 are controlled by a control unit 4 , which for this purpose also measures and evaluates the voltages U _S1 and U _S2 dropping at the switching elements S1 and S2. The control unit 4 contains a separate control circuit for each switching element, a first control circuit 10 serving to control the switching element S1 and a second control circuit 10 'serving to control the switching element S2. The control unit 4 can be implemented, for example, together with the control circuits 10 and 10 'on a single integrated circuit (IC). In particular, it is also possible to implement the control circuits 10 and 10 ′ by means of a single control circuit and then by multiplexing the voltages U _S1 or U _S2 control circuit parts (in particular the function blocks 11 , 12 , 14 , 15 , 16 and 17 in FIG. 5 ) to be used twice. The control circuits 10 and 10 'can also be implemented by means of separate ICs. With the help of the control unit 4 or the control circuits 10 and 10 ', an automatic adaptation of the length of dead time phases is ensured, which will be explained in more detail below.

In parallel with the switching element S2, a capacitance Cp is shown, at which a chopped DC voltage U3 drops during operation of the converter 1 . The capacitance Cp summarizes in particular the parasitic capacitances of the switching elements S1 and S2 when they are implemented as MOSFET transistors, as in the present exemplary embodiment. The capacitance Cp can also detect other additional capacitors. The zer chopped DC voltage U3 is supplied to a circuit structure 5 which contains resonance circuit elements and generates an output DC voltage U2. As a resonant circuit elements, the circuit structure 5 in the present case contains a capacitance Cr and an inductance Lr, which are connected in series. Between the series connection of the capacitance Cr and the inductance Lr and the capacitance Cp there is a rectifier arrangement G in the direction of the converter output, which rectifies a current I flowing through the resonance circuit elements Cr and Lr and, as usual, supplies a smoothing capacitance C arranged on the output side to which the output DC voltage U2 can be tapped. In FIG. 2, the DC output voltage U2 is applied to a load R, which is shown here as an ohmic resistance. In principle, the converter 1 could also be used to supply an AC voltage instead of a DC voltage. In such a case, rectification by means of a rectifier arrangement and a smoothing capacitor would not be required and the output voltage would be equal to the alternating voltage dropping across the rectifier arrangement 6 in the embodiment according to FIG. 2.

The DC input voltage U1 is switched on alternately (transfer to the conductive state) and switching off (converting into the blocking state) of the Switching elements S1 and S2 implemented in the chopped DC voltage U3. Is the switch S1 switched on, switch S2 is switched off. If switch S2 is switched on, then switch S1 turned off. Between the end of a switch-on phase of switch S1 and the start of a switch-on phase of S2 is a dead time phase in which both Switching elements S1 and S2 are switched off. Between the end of a switch-on phase of the switching element S2 and the beginning of the subsequent switch-on phase of the switching element S1 is also such a dead time phase. By providing such dead time phases, ZVS operation (ZeroVoltage Switching) is made possible. By adjusting the Switching frequency becomes a constant output voltage even with load fluctuations and Fluctuations in the input voltage ensured.

The upper of the three diagrams shown in FIG. 3 represents the difference | U _G1 | - | U _G2 | represents the amount of the control voltage U01 applied to the switching element S1 and the amount of the control voltage U _G2 applied to the switching element S2, in the present exemplary embodiment for the case that only positive control voltages U _G1 and U _G2 are present. The control voltages serving as the control signal for controlling the switching elements S1 and S2 represent corresponding gate voltages of the MOSFET transistors. If the applied difference in the amounts of the control voltages is equal to zero, there is a dead time phase, which is denoted in each case by T _tot . If, by applying a suitable control voltage U _G1 to the control input of the switching element S1, the switching element is switched to its switched-on state, the time periods denoted by T _on (S1) are present. In these periods, the control voltage U _G2 is zero and thus the switching element S2 is switched off. The periods in which the switching element S2 is switched on and the switching element S1 is in the switched-off state are denoted by T _on (S2). During these periods, the control input of the switching element S2 is supplied with a control voltage U _G2 which is different from zero and which causes the switching element S2 to be switched on. Within these periods, the control voltage U _G1 is zero. The middle diagram in FIG. 3 shows the time profile of the current flowing through the resonance circuit elements Cr and Lr. Finally, the time curve of the voltage U3 present at the parasitic capacitance Gp is shown in the lower diagram in FIG. 3. The time axes of the three diagrams with the plotted time t all have the same scale.

In the following, the change between the on and off states of the switching elements S1 and S2 is explained as an example, on which the processes during the change between the individual switching cycles are illustrated. At time t0, the control voltage U _G2 is set to zero in order to cause the switching element S2 to be switched off. This leads to a discharge process at the gate electrode of the MOSFET transistor used to implement the switching element S1. However, until this discharge process is complete, the switching element S2 is still conductive, so that the current I, which is negative at this point in time, still flows through the switching element S2. From time t1, switching element S2 is finally switched off, so that current can no longer flow through it. The current I, which continues to flow due to the energy stored in the inductance Lr, now causes the capacitance Cp to be charged from the time t1 and thus the voltage U3 to rise. At time t2, the voltage U3 has finally reached the value of the input DC voltage U1, so that the diode D1 begins to conduct. From this point on, switching-on of the switching element S1 is ensured under a switching element voltage U _S1 of almost 0 volts (ZVS at the diode forward voltage). Before switching on the switching element S1, two criteria must be met: on the one hand, the predetermined threshold value U _th must have been exceeded at the beginning of the dead time phase (ie, the load must be inductive) and, on the other hand, the dead time T _dead must have elapsed.

A short time after the time t2 - at the time t4 - the switching element S1 is switched on by applying a corresponding control voltage U _G2 . A period T _on (S1) is thus initiated with switching element S1 switched on and switching element S2 switched off.

At time t5, the end of this period T _on (S1) is initiated by setting the control voltage U _G1 to zero. This in turn leads to a discharge process at the gate electrode of the MOSFET transistor used to implement the switching element S1. At the time t6, this discharge process is completed to such an extent that the shah element S1 begins to lock, that is to say changes to the switched-off state, so that the current I positive at this time leads to the discharge of the capacitance Cp and thus to a drop in the voltage U3. At time t7, the voltage U3 has reached the value zero, so that from this point in time the diode D2 begins to conduct and the switching element S2 can be switched on under a switch voltage U _S2 of almost 0 volts (at the diode forward voltage), a short time later the application of a corresponding control voltage U _G2 at time t9 also happens. From this point in time, a period T _on (S2) begins in which the switching element S2 is switched on and the switching element S1 is switched off.

Both between the times t0 and t4 and between the times t5 and t9 there is a so-called _dead time phase T _tot , during which both the control voltage U _G1 and the control voltage U _{G2 are} equal to zero and thus control voltages acting as switch-off control signals are present . The _{dead time} phases T _tot are set here so that ZVS operation is possible. In the I (t) diagram, the hatched areas represent a measure of the energy available for reloading the capacitance Cp. In the case shown in FIG. 3, the energy available is available to a sufficient extent.

The operating state shown with the time profiles shown in FIG. 3 represents, for example, an inductive load case, ie the current I lags behind the first harmonic of the voltage U3. In such an operating state, ZVS operation (zero voltage switching) of converter 1 is possible.

In contrast, FIG. 4 shows, by way of example, corresponding time profiles for a capacitive load case. In such an operating state, the current I leads the first harmonic of the voltage U3. In the capacitive load case, ZVS operation of converter 1 is no longer possible. Switching element S2 is switched off at time t0 in FIG. 4. The current I is positive, so that a gradual charging of the capacitance Cp up to the voltage U1 (as in the case according to FIG. 3 between the times t1 and t2) by the current I continuously driven by the energy stored in the inductor Lr not possible. In this case, the voltage U3 is abruptly increased from the value zero to the value U1 at the time t4 at which the switching element S1 is switched on, ie when S1 is switched on, the full voltage of U1 is still present at this switching element. Correspondingly, the switching element S2 is not switched on without voltage in the capacitive load case, because at time t9, at which the switching element S2 is switched on, the voltage U3 still has the value U1 and is abruptly reduced to the value zero. Since, in the capacitive load case, high switching losses (correspondingly large values for the product of the current I and the switching element voltages U _S1 and U _S2 at times t4 and t9) occur in the switching elements S1 and S2, which are designed here as MOSFET transistors, and are even used for This operating state must be avoided if the switching elements can be destroyed. How this is done will be explained in more detail later with reference to FIG. 7.

Fig. 5 shows the basic structure of the components used to control the switching element S1 control circuit 10 as a block diagram. The control circuit 10 has circuit parts combined by a function block 14 , which determines the difference quotient (ie, the derivative) of the switching element voltage U _S1 present during the _{dead time} phases T _tot immediately preceding the switch- _on phases T _on (S1) and feeds it to a comparison device 15 which supplies the difference quotient dU _S1 / dt with a threshold value U _th . When the threshold value U _th is reached, a set signal corresponding to a logic "one" is sent to the OR gate 13 .

In addition, the control circuit 10 also contains a time prayer 16 , which starts at the beginning of a _{dead time} phase T _tot , which immediately precedes a switch- _on phase T _on (S1), and sends a corresponding time signal to a comparison device 17 , which supplies this supplied time signal with a predefinable dead time phase length T _dead , compares. When this _{dead time} phase length T _{tot is reached} , the comparison device 17 supplies a set signal corresponding to a logic “one” to the OR gate 13 .

If the output of the OR gate 13 supplies a logic "one", this causes the initiation of a switch- _on phase T _on (S1) or the end of the corresponding preceding _{dead time} phase T _tot . If a logic "one" is present at the output of the OR gate 13 , the timer 16 is reset and circuit means combined by a function block 18 cause a control signal U _G1 acting as a switch-on signal to be delivered to the control input of the switching element for a switch-on time T _on (S1) S1. Furthermore, the function block 18 summarizes circuit means which, after the end of a switch-on phase T _on (S2), activates the measuring and evaluation devices in the function block 14 and the timer 16 . A corresponding activation signal, which serves as an enable signal for the measuring and evaluation devices of the function block 14 and as a trigger signal of the timer 16 , is at this time given by the function block 18 to the function blocks 14 and 16, respectively. This happens at the time at which the end of a switch-on time T _on (S2) to the function block 18, a signal is supplied to 19, constructed from a as the control circuit 10 the second control circuit 10 ', which serves to control the switching element S2 is generated. Accordingly, the function block 18 or the control circuit 10 also generates a corresponding signal 20 at the end of a switch-on phase T _on (S1) to the corresponding second control circuit 10 '.

Fig. 6 shows a transfer function A (f) which shows the course of the quotient U2 / U3 in function of the frequency f. The transfer function A (f) has its maximum at the resonance frequency f _{r of} the converter 1 , which is essentially determined by the capacitance Cr and the inductance Lr. The capacitive load case exists at frequencies f less than f _r (range I). Frequencies greater than f _r (area II), on the other hand, correspond to converter operating states with inductive converter loading. Accordingly, the converter is to be operated at frequencies f above the resonance frequency f _r . From FIG. 6 it can be seen that the capacitive mode of operation (area I) should also be avoided because the control mechanisms normally used for regulating the converter output voltage U2 no longer apply. Because in area I, in contrast to area II, the value of A (f) decreases with decreasing frequency, so that instead of negative feedback as in area I (increasing values of A (f) with decreasing frequency f), there is a positive feedback, which is a Regulation of the output voltage U2 prevented.

The flowchart shown in FIG. 7 shows how the control unit 4 monitors (by means of circuit arrangements not shown in more detail) whether there is an inductive load case or a capacitive load case when converter 1 is operating. Monitoring is preferably carried out cycle by cycle in order to ensure that the monitoring is as complete as possible. Block 30 represents one of the successive switch-on phases (T _on (S1) or T _on (S2)) of the switching elements S1 and S2. During a _dead time phase T _dead represented by a block 31 , the derivative (differential quotient) of the voltage applied to a switching element becomes determined, in particular for each dead time phase and accordingly before each switching on of one of the switching elements S1 or S2. It can be seen from FIGS. 3 and 4 that with inductive loading ( FIG. 3) the course of this derivative from the course with capacitive loading ( FIG. 4) during the periods in the dead time phases in which both switching elements S1 and S2 are in the non-conductive state are different (ie here in the periods from t0 to t4 and from t5 to t9). This is used to determine whether there is an inductive or a capacitive load. The threshold value U _th is correspondingly set to a value from the range between the expected values for the derivation of the switching element voltages for inductive or capacitive loading during these periods.

In particular, the significant drop or rise in the voltage U3 present in the capacitive load case ( FIG. 4) in the periods between t0 and t1 or between t5 and t6 (and the corresponding preceding and subsequent periods). This leads to a very quick detection of the type of load case. Another possibility is to evaluate the marked rise or fall of the voltage U3 in the inductive load case ( FIG. 3) in the periods between t1 and t2 or between t6 and t7 (and the corresponding preceding and subsequent periods).

Wrong measurement results due to high-frequency voltage components to counteract, the measured derivative is in particular also low-pass filtered, the time constant of the filter being small compared to the length of the dead time phase should.

Alternatively, instead of directly comparing the derivation of switching element voltages with a threshold value U _th, a comparison of a threshold value U _th with a time average of the amount of the respective switching element voltage could also take place in dead time phase periods. The formation of an average over time is associated with signal smoothing. In particular, the mean value for the periods between t1 and t2 or between t6 and t7 (and the corresponding preceding and subsequent periods) is evaluated. However, the average could also be formed for sections from these periods.

In the converter 1 shown in FIG. 2, both switch voltages U _S1 and U _S2 (= U3) are evaluated. The switch voltage U _S1 could also be determined indirectly from the voltage U1 and the voltage U _S2 = U3 as the difference U1-U3.

If it is determined in the step represented by block 32 that the mean value determined in each case is greater than the threshold value U _th (branch Y), the converter operation is continued with the next switch-on phase T _on (block 30 ). However, if it is determined in this step that the corresponding mean value is smaller than the threshold value U _th (branch N), which corresponds to the capacitive load case, the converter normal operation is terminated and in particular a new converter start sequence is carried out in the usual way (block 33 ).

Claims (5)

1. Converter with switching elements (S1, S2) for chopping a DC voltage (U1), with switching phases of the switching elements (S1, S2) alternating with one another, and with one processing the chopped DC voltage (U3) and serving to supply an output voltage (U2) Circuit structure ( 5 ) with resonance circuit elements (Cr, Lr), characterized in that it is provided that during a dead time phase (T _tot ) the derivative (dU _S1 / dt) of the voltage (U _S1 ) applied to a switching element is determined, and with the help the determined derivative (dU _S1 / dt) to determine whether there is an inductive or capacitive converter load. 2. Converter according to claim 1, characterized in that it is provided to compare the determined derivative (dU _S1 / dt) with a threshold value (Ufft) by means of a comparator ( 15 ) and to determine from the comparison result whether an inductive or capacitive converter load is present. 3. Converter according to claim 1, characterized in that it is provided during a dead time phase (Ttot) to determine a time average for the amount of derivative (dU _S1 / dt) of the voltage (U _S1 ) applied to a switching element and with a threshold value (U _th ) by means of a comparator ( 15 ) and determine from the comparison result whether there is an inductive or capacitive converter load. 4. Converter according to claim 2 or 3, characterized in that the comparison with the threshold value (U _th ) takes place each time before switching on one of the switching elements (S1 or S2). 5. Control unit ( 4 ), in particular an integrated circuit, for controlling at least one of the switching elements (S1, S2) of a converter ( 1 ) used for chopping a DC voltage (U1), in the switching phases of the switching elements (S1, S2) alternating and which has a circuit structure ( 5 ) which processes the chopped DC voltage (U3) and serves to supply an output voltage (U2), with resonant circuit elements (Cr, Lr), characterized in that the control unit ( 4 ) is provided for during a dead time phase (Dead) to determine the derivative (dU _S1 / dt) of the voltage (U _S1 ) applied to a switching element, and to use the determined derivative (dU _S1 / dt) to determine whether there is an inductive or capacitive converter load.