DE19961124A1 - interface - Google Patents

Abstract

The invention relates to an interface between a first device that writes data in a second device or reads data from a second device and the second device. The invention is characterized in that said interface buffers at least partly the data and signals exchanged between the first and second devices when the first device is reading data from the second device or writes data in said second device and forwards them immediately or later on to the corresponding point of destination.

Description

The present invention relates to a device according to the Preamble of claim 1, d. H. an interface enroll between data in a second facility the first or data read from the second device Facility and the second facility.

Interfaces between institutions that communicate with each other have to cooperate or cooperate for many years innumerable embodiments known. They serve in particular the institutions connected to each other to fit. Such interfaces are, for example serial or parallel interfaces of programm controlled units such as microprocessors, microcontrollers, Signal processors etc., via which these with memory devices for storing data are to be connected or can be connected.

Reading data from a storage device and that Data must be written into a storage device in the generally go very quickly. Preferably he follow the reading of data from a storage device and writing data into a storage device still in the clock period in which the device, the Read data from the storage device or data has to write into the memory device, the readout or ordered registered mail.

Attempts are being made to store storage devices with great effort develop who are able to do this. On the other hand, takes but also the speed of work of the facilities that Have to write data into storage devices or Read more and more data from storage devices to.  

Therefore, and because of the facilities, the data in memory have to enroll facilities or data from memory devices to be read out by the storage device to initiate and carry out a writing or Read process expected or required data and signals sometimes only relatively late in the cycle period, in which carries out the reading or writing of data outputs to the storage device, it comes again and again that the storage facilities do that to them commanded reading or writing of data not or not reliably free from errors in the clock period in which they can issue the appropriate instruction have received.

To correct this problem, the Clock frequency with which the reading or writing of data initiating device and the storage device tion to reduce until the memory device is able to read and store to perform data in the clock period in which it was caused. However, this reduces the work speed of setup, the data in the memory device has to be registered or data from the memory has to be read out, and is consequently a considerable one Disadvantage.

A possible alternative to this is that in the Device, the data in the storage device has to write or data from the storage device has read, so-called wait states are inserted. This but also reduces the speed of work.

Another way to fix the addressed Problem is setting up the data in the Storage device has to be registered or data from the Has to read out the storage device, and the storage device  to adapt to each other in the design of the same sen or interconnect that the problem is not at all occurs. However, this is generally an immense one Development effort connected and also often not at all possible.

The present invention is therefore based on the object to find a way by which to establish has to write the data into a storage device or Read data from the storage establishment, among all Circumstances, d. H. especially when the memory facility is unable under normal circumstances to the commanded reading or writing of data still in the cycle period in which you ordered this was able to be put in position with little effort without Reduction of the clock frequency and without long pauses in data Read out from the storage device and / or data in the To be able to register the storage device.

According to the invention, this object is characterized by the solved the part of claim 1 claimed features.

Accordingly, it is provided that the interface and the data Signals representing the first device and the second device output to each other when the first device out of the two Read out data in the third facility or into the second facility Want to register data, at least partially between saves and immediately or later to the respective Forwarding destination.

Such an interface can be used to individual phases of the read and write processes independently extend, shorten and / or ver push.

By a suitable choice of the times at which data or Signals transferred to and from the interface  forwarded, it can be ensured that the Enroll data in the second facility and the off read data from the second device reliably can be done without errors.

Under particularly unfavorable circumstances, in Be bought that read or write by the second device no longer in the cycle period can be completed in which they are through the first Establishment, but it is by a like claimed trained interface possible that only completely certain phases of read and write access extended and / or be moved, creating the interface for this can ensure that the delays mentioned when reading and enrolling data in number and duration be reduced to a minimum. The first facility can be there by working significantly faster on average than it is at a reduction in the clock frequency or the insertion of Wait States is possible.

Advantageous developments of the invention are the sub claims, the following description and the figures ent acceptable.

The invention is based on an embodiment exemplified with reference to the figures. Show it

Fig. 1 shows schematically the structure of the arrangement described in more detail below, and

Fig. 2 used by the arrangement of FIG. 1 clock signals.

The facilities that are described in more detail below The interface to be written must be considered  example, a signal processor and a memory rack device (for example a RAM) for storing data.

At this point, however, it should be pointed out that there is no restriction. Instead of the signal processor can also be any other facility ten, which has to read out data from a storage device or has to write to a storage device; instead of the storage device can also be a storage device device containing device can be used.

In the example considered, the interface is a separate one Component. As a result, it can be used on both Signal processor as well as to the storage device optimal be adjusted. In principle, the interface can also Part of the signal processor or the memory device his.

The basic structure of the present arrangement is shown in Fig. 1. The signal processor is designated by the reference symbol 1 , the memory device by the reference symbol 2 , and the interface connecting the signal processor 1 by the memory device 2 by the reference symbol 3 .

The interface 3 under consideration is characterized in that it outputs the data and signals which the signal processor (or another first device) and the memory device (or another second device) output to one another when the signal processor wishes to read data from the memory device or in the storage device wishes to write data, at least partially caches them and forwards them to the respective destination immediately or later.

The interface 3 can thus be set as a pipeline stage and used to lengthen, shorten and / or shift the individual phases of the read and write processes independently of one another.

The data and signals temporarily stored and forwarded by the interface 3 include in the example considered

• - In the event that the signal processor 1 wants to read data from the memory device 2 ,
  • a read signal by which the signal processor 1 signals the memory device 2 that it wants to read data from,
  • a read address by means of which the signal processor 1 signals the memory device 2 from which location within the memory device 2 it wants to read data, and
  • - The data that the memory device 2 outputs on a read request from the signal processor 1 , and
  • - In the event that the signal processor 1 wants to write data into the memory device 2 ,
  • a write signal, by means of which the signal processor 1 signals the memory device 2 that it wants to write data,
  • Address data, by means of which the signal processor 1 signals the storage device 2 to which location within the storage device 2 it wishes to write data, and
  • - The data which the signal processor 1 wants to write to the storage device 2 .

The signal processor 1 , the memory device 2 and the interface 3 generate or receive a common (system) clock SYSCLK. The interface 3 generates or receives additional clock signals PHI1 and PHI2, which have the same period as the system clock SYSCLK, but a different phase position and / or a different duty cycle than the system clock SYSCLK. In the example considered, the additional clock signals PHI1 and PHI2 are generated by the signal processor 1 and fed to the interface 2 by the latter.

As will be explained in more detail, the additional clock signals PHI1 and PHI2 serve to define the times at which the interface 3 takes over signals and data (caches) and forwards them. The clock signals are thus interface control signals using which the interface 3 can be controlled by the signal processor 1 . The interface 3 can thus be regarded as an external pipe line stage of the signal processor 1 .

The clock signals PHI1 and PHI2 or further or other interface control signals can at least partially also be generated by the memory device 2 and supplied to the interface 3 .

The clocks SYSCLK, PHI1, and PHI2 are illustrated in FIG. 2; the clock periods of the system clock SYSCLK are P1, P2. , , designated.

It is now assumed that the signal processor 1 wants to read out data from the memory device 2 . In this case, it outputs the read signal already mentioned and the read address also mentioned above. These signals and data are fed to the interface 3 , which, after they are valid, temporarily stores them.

In the example under consideration, the read signal and the read address are output from the signal processor 1 during the system clock period P1 and are still adopted in the same system clock period, more precisely with the rising edge of the clock signal PHI2 in the interface 3 and buffered there. Since the clock signal PHI2 is generated by the signal processor 1 in the example under consideration, the interface 3 can assume without its own checking that the read signal and the read address are valid at the time of the said transfer.

The interface 3 forwards the read signal and the read address immediately or later to the memory device 2 , which then begins reading out the requested data and outputs the read data.

The data output by the memory device 2 are fed to the interface 3 , which it takes over and temporarily stores in the system clock period P2 following the system clock period P1 with the rising edge of the clock signal PHI2.

The interface 3 preferably forwards this data immediately to the signal processor 1 , with which the reading process can still be completed in the system clock period P2.

Reading data from the storage device can also Reliably error-free at very high system clock frequencies be carried out because the storage device for this - unlike arrangements without the cut described position - almost a full system cycle period (increasing PHI2 Edge to rising PHI2 edge) is available.

However, the signal processor 1 no longer receives the data requested by it in the system clock period P1 in which it requested it, but only in the subsequent system clock period P2. In the example considered, a reading process therefore takes two system clock periods.

Because a read cannot be performed in a single system clock period, the signal processor cannot operate as fast as would theoretically be possible. However, the reduction in operating speed is, on average, very small compared to a system clock frequency reduction or an insertion of wait states. In practice it happens relatively rarely that the signal processor only needs the data that is stored under the read address; Signal processors, but also other program-controlled units such as microprocessors and microcontrollers often work in read access in the so-called burst mode, in which use is made of the ability of certain storage devices to not only store the data stored under the read address after the creation of a read address, but - without a new read access - then automatically output the data which are stored at the addresses following the read address, as a result of which a large amount of data can be obtained by a single read request from the signal processor. Since the storage devices, which can be operated in burst mode, output the data which they output on a read access in the system clock, and since the interface 3 is able to keep up with the data output by the storage device as described (in System clock) from the storage device and forward it to the signal processor, the read access takes a total of only a single system clock period longer than a read access, in which requested data can still be obtained in the clock period, regardless of the amount of data that the storage device outputs which they were requested. This is particularly when the memory device outputs a larger amount of data per read access, a relatively small delay, which can be easily tolerated in most applications.

If the signal processor 1 wants to write data into the memory device 2 , it outputs the write signal, the write address, and the data to be written. These signals and data are fed to the interface 3 , which, after they are valid, temporarily stores them.

In the example under consideration, the write signal and the write address are output from the signal processor 1 during the system clock period P1 and are still transferred to the interface 3 in the same system clock period, more precisely with the rising edge of the clock signal PHI1, and buffered there. Since the clock signal PHI1 is generated in the example under consideration by the signal processor 1 , the interface 3 can assume without own verification that the write signal and the write address are valid at the above-mentioned takeover time.

The data to be written into the memory device are also output during the system clock period P1 from the signal processor 1 , but - because the output time in the example considered is shortly before the end of the system clock period P1 - only in the subsequent system clock period P2, more precisely with the rising edge of the system clock SYSCLK in interface 3 and buffered there.

Subsequently, that is, at the beginning of the system clock period P2, the interface 3 forwards the write signal, the write address, and the data to be written to the memory device 2 , which then carries out the required write-in within the system clock period P2.

The writing of the supplied to the storage device Data in the storage device can also be very high  System clock frequencies reliably performed without errors the because of the storage device for this - unlike in Arrangements without the described interface - almost one whole system cycle period (the system cycle period P2) for ver is standing.

However, the data is no longer registered in the system clock period P1, in which the signal processor does this has initiated, but only in the subsequent system clock period P2. A write process lasts in the considered Example two system clock periods.

If the signal processor is not immediately after a Write access another write access or a Read access, he can after issuing the Write signal, the write address and the to be written Data continues to work without any delay; he must - different with a reading process - do not wait for the Writing process is finished.

If the signal processor has to store a larger amount of data in the memory device, it may not be able to work as quickly as it would theoretically be possible. However, this only applies in the event that the larger amount of data is stored by a correspondingly large number of successive memory accesses, and occurs relatively rarely in practice. Signal processors, but also on program-controlled units such as microprocessors and microcontrollers, often also work in write access in the already mentioned burst mode, in which use is made of the ability of certain memory devices to ensure that these do not only contain the data they are supplied with during write access store the write address supplied to them, but also store further data which are subsequently supplied to them by the signal processor under the addresses which follow the write address initially supplied to them. Since the interface 3 is able to take over the data sequence to be stored in the memory device in the manner described above from the signal processor in the system cycle and to forward it to the memory device, and since the memory device is able to transmit from the interface 3 , In other words, to receive and store data supplied at the very start of a system cycle period in the system cycle, the write access takes as long as the corresponding write access in an arrangement, regardless of the amount of data that the memory device has to be stored , in which data to be stored in the memory device can still be stored in the clock period in which this was caused by the signal processor. The signal processor is therefore generally not braked by writing larger amounts of data into the memory device; it can continue to work before, during and after data has been written into the storage device at undiminished speed and without pauses.

A writing of data into the Storage device only reduces the working speed, if a write access is another write access follows (if larger amounts of data are not in burst mode be written) or if a write access Read access follows, which is relatively rare in practice comes and can be easily avoided.

The interface described transfers the over it with the Storage device connected signal processor so in the Location, without reducing the clock frequency and without longer Read data from the memory device and / or pauses To be able to write data into the memory device.

Claims (17)

1. Interface between a data device that writes data into a second device ( 2 ) or reads data from the second device ( 1 ) and the second device, characterized in that the interface ( 3 ) contains the data and signals that the first device ( 1 ) and the second device ( 2 ) to each other if the first device reads data from the second device or writes data into the second device, at least partially buffers and immediately or later forwards it to the respective destination. 2. Interface according to claim 1, characterized in that the interface ( 3 ) is a separate module. 3. Interface according to one of the preceding claims, characterized in that the interface ( 3 ) is able to lengthen, shorten and / or move the individual phases of the read and write operations. 4. Interface according to one of the preceding claims, characterized in that the takeover and / or the forwarding of the data and signals through the interface ( 3 ) take place at times which at least partially define interface control signals (PHI1, PHI2) supplied by the interface become. 5. Interface according to claim 4, characterized in that the interface control signals (PHI1, PHI2) are clock signals which have the same period as a system clock signal (SYSCLK), depending on which of the first and / or the second device ( 1 , 2 ) work, but different duty cycles and / or phase positions. 6. Interface according to claim 5, characterized in that the times of the takeover and / or the forwarding of the data and signals in the event that the first device ( 1 ) wants to read data from the second device ( 2 ), and the times of the takeover and / or the forwarding of the data and signals in the event that the first device wishes to write data into the second device can be defined by various clock signals (PHI1, PHI2). 7. Interface according to claim 5 or 6, characterized in that the interface control signals (PHI1, PHI2) are generated in the first device ( 1 ). 8. Interface according to one of the preceding claims, characterized in that the data and signals temporarily stored and forwarded by the interface ( 3 ) in the event that the first device ( 1 ) from the second device ( 2 ) wants to read data from, a read signal comprise, by which the first device signals the second device that it wants to read out data. 9. Interface according to one of the preceding claims, characterized in that the data and signals temporarily stored and forwarded by the interface ( 3 ) include address data in the event that the first device ( 1 ) from the second device ( 2 ) wishes to read data , through which the first device signals to the second device from which location within the second device it wants to read out data. 10. Interface according to one of the preceding claims, characterized in that the data and signals temporarily stored and forwarded by the interface ( 3 ) in the event that the first device ( 1 ) from the second device ( 2 ) wants to read data from, the data comprise which the second device outputs on a read request from the first device. 11. Interface according to one of the preceding claims, characterized in that the data and signals temporarily stored and forwarded by the interface ( 3 ) in the event that the first device ( 1 ) in the second device ( 2 ) wants to write data, a write signal comprise, by which the first device signals the second device that it wants to write data. 12. Interface according to one of the preceding claims, characterized in that the data and signals temporarily stored and forwarded by the interface ( 3 ) in the event that the first device ( 1 ) in the second device ( 2 ) wants to write data, include address data , through which the first device signals the second device to which location within the second device it wants to write data. 13. Interface according to one of the preceding claims, characterized in that the data and signals temporarily stored and forwarded by the interface ( 3 ) in the event that the first device ( 1 ) in the second device ( 2 ) wants to write data, the data include who wants to enroll the first facility in the second facility. 14. Interface according to one of the preceding claims, characterized in that the times at which the interface ( 3 ) from the first device ( 1 ) temporarily stores data output, and / or the times at which the interface stores the temporarily stored data at the second Device ( 2 ) forwards, depend on whether the first device wants to read data from the second device or wants to write data into the second device. 15. Interface according to one of the preceding claims, characterized in that the first device ( 1 ) is a program-controlled unit. 16. Interface according to one of the preceding claims, characterized in that the first device ( 1 ) is a signal processor. 17. Interface according to one of the preceding claims, characterized in that the second device ( 2 ) is a memory device or a device containing a memory device.