DE19951046A1 - Memory component for a multi-processor computer system has a DRAM memory block connected via an internal bus to controllers with integral SRAM cache with 1 controller for each processor so that memory access is speeded - Google Patents

Abstract

Memory component (SPB) comprises a number of controllers (CO1...COm) corresponding to the number of processors connected via an internal bus to a DRAM memory bank (DSB). Each controller is connected to an interface to the processors and has its own SRAM cache memory. Each controller can be programmed according to the access characteristics of the processors and the internal memory component bus operates according to a store-through cache protocol.

Description

The invention relates to a memory chip for a Multi-processor system, in which several processors over connect a processor bus to the interface of the module are cash.

The invention also relates to a multiprocessor system with a memory chip.

In multi-processor systems, multiple microprocessors are said to be via a common bus to a common memory access. DRAMs are usually used, i. s. dynamic ram memory that is suitable for large storage capacity suitable, but have an access time of approx. 60 ns. For microprocessors that are clocked at high frequency, System performance is largely dependent on memory access time and the previously mentioned access time of 60 ns for DRAMS has a significant share in the median memory access time. According to the prior art as Spei cher so-called "Synchronous DRAMS" used, and so achievable access speed in the sizes mentioned order is accepted. The individual processes have sensors to access the memory, chaches and an own chache coherence protocol ensures that the cha che coherence is maintained. Through elaborate cache Coherence protocols can determine the actual access time Utilization of known reference locations relatively be kept low. However, it is disadvantageous that in addition the actual data transfer between memory and Pro cessors also a complex coherence protocol on the bus system must run, which ultimately also the loss line performance of a block increased. The problem of cache coherence along with a much used coherence protocol  MESI protocol, for example, explained in: Wolfgang K. Gi loi, "Computer Architecture", Springer-Verlag 1993, pages 111 until 116.

In addition to DRAMS, there are also so-called SRAMS (static RAMS) knows that with an average latency of 10 ns work much faster than DRAMS, but from theirs Area are much larger. For storing one In an SRAM, bits or bytes is about 4 times the area necessary, which is required with a DRAM. This means but that the use of an SRAM as memory is essential This would result in shorter access times, but from the cost side is out of the question.

It is now an object of the invention to provide a memory chip to create which has a much shorter access time offers, without the basic use of a DRAMS is going off.

This task is started with a memory chip mentioned type according to the invention solved in that a an internal bus with multiple controllers connected to DRAM Memory bank is provided, the controller which on the other hand connected to the interface, each with one RAM cache are equipped and configurable.

The invention de facto shifts the chaches from the processes sensors in the memory chip since the SRAMS are now small in size e.g. B. 1024 bits in the control assigned to the memory bank learn to represent a kind of cache. It won't insignificant effort for an elaborate cache coherence protocol for the processor chaches and its operation the.

A memory chip according to the invention can also be easily can be adapted to the respective application, with a Reference blocks connected memory blocks already in the  Main memory can be cached and transferred to the processors can be done concurrently. The invention is particularly advantageous for embedded systems, since there the Memory access behavior of the processors known and im Process is deterministic. Therefore, the storage system for optimal caching and pre-fetching can be configured to to minimize the mean memory access time.

Another object of the invention is to achieve more to create processor system which has a main memory used at least one memory chip and which one access times at low cost.

This task is solved with a multiprocessor system, which a memory chip of the type according to the invention contains and in which the number m of controllers at least is equal to the number n of processors and for each process sor at least one controller is provided.

Such a multiprocessor system already offers the ge called advantages. Due to the spatial proximity of the controller their caches to the memory bank can be easily realized traceable coherence protocol, which is based on the internal bus of the memory module expires.

It is also an advantage if you assign a processor ter controller taking into account the access characteristics stik of the processor is programmable. This allows an optimal adaptation of the prefetch strategy to the system achieve conditions. It is also for certain cases recommended if on the internal bus of the memory construction a cache coherence protocol is running.

The invention together with further advantages is based on the following examples with the aid of the drawing explained in more detail. In this shows the only figure in one  Block diagram of a multiprocessor system with a memory Building block according to the invention.

As can be seen from the figure, contains a multiprocessor system essentially a number n of processors PR1, PR2. . . PRn, a memory chip SPB, an input / output unit I / O and a processor bus PBU. All processors PR1. . . PRn can access the common via the processor bus PBU Access memory SPB. Such multiprocessor systems are known and described for example in: W. Oberschelp / G. Bossen, "Computing structure and computer structures", 7th edition, R. Oldenburg Verlag, 1998, ISBN 3-486-24288-1, chapter 13, p. 415 ff. As already mentioned at the beginning of such known structures the cache memory at or in each Processor important for accessing the memory.

In contrast, the path taken by the invention now provides that the memory chip SPB is not just one DRAM memory bank contains DSB, but also several Control ler CO1. . . COm, e.g. B. 16 pieces, each a RAM cache RAC included and via an internal bus IBU with the DRAM memory cherband DSB can communicate. This memory bank DSB can have a size of 256 KB, 1 MB or 4 MByte, the RAM caches RAC, however, have a ge rings size of z. B. only one kbyte, with example wise cache lines of 32 bytes. The controllers CO1. . . COm are available via an IFA interface, here symbolically indicated, in connection with the processor bus PBU.

In addition to this structure, it is essential that the controller CI1. . . COm are configurable, with each processor PR1. . . PRn a controller CO1. . . COm can be programmed so that it has the (main) memory access, i. H. access to controls the DRAM memory bank DSB of the respective processor. Of course, this requires PR1 for each processor. . . PRn at least a controller CO1. . . COm can be provided, but can also other configurations may be appropriate. For example  if there are four processors, the first processor eight of the sixteen controllers are assigned to the second Processor six of the controller and the third and fourth Processor a single controller depending on the Task area and the performance of the individual processors.

Each of the controllers CO1. . . COm becomes the access character stik of the assigned processor PR1. . . PRn communicated with one can generally provide the following characteristics.

"Sequential" Sequential access with ascending / descending addresses.

"Blocked" access to known memory blocks size

"Random" access to the memory without reference template.

Depending on the type of memory access, memory content is asyn chron to the current requirements in a RAM cache RAC the controller CO1. . . COm transfers, namely:

"Sequential Access": With a 2-bit predictor, the Access direction - namely up or descending - determined and from one be agreed, e.g. B. the third access is a prefetching of the following Cache line ("Chacheline") passed through leads. The predictor logs the Direction of access with regard to or descending addresses to order at a re-access to predict whether the Cacheline with descending or ascending Addresses should be filled.  

"Blocked Access": In a register field of a controller CO1. . . COm is used for every storage area rich, e.g. B. 4 MB, the block size, typically in the range of 64 to 1024 bytes, saved. When z. B. third access to a block the entire block in the RAM cache RAC transferred.

"Random Access": In this case, a completely irregular one Access is not prefetched carried out.

The invention thus enables quasi-parallel access of the processors PR1. . . PRn to the DRAM memory bank SPB, yes is a processor's direct access to the memory bank not possible. At this point it should be mentioned that the singular "memory bank" used here is not physically too see and should not rule out the possibility of several Memory banks or several memory modules in one system available.

Claims (5)

1. Memory module (SPB) for a multiprocessor system in which a plurality of processors (PR1... PRn) can be connected to the interface (IFA) of the module via a processor bus (PBU), characterized in that
that a DRAM memory bank (DSB) connected to several control learners (CO1... COm) is provided via an internal bus (IBU),
the controllers, which are connected to the interface (IFA), are each equipped with a RAM cache (RAC) and are configurable. 2. Multiprocessor system with a memory chip (SPB) after Claim 1 characterized in that the number m of Con troller (CO1... COm) at least equal to the number n of processes sensors (PR1 ... PRn) and at least one for each processor Controller is provided. 3. microprocessor system according to claim 2, characterized in that a processor (PR1... PRn) assigned controller (CO1... COm) under consideration view of the access characteristics of the processor program can be mated. 4. Microprocessor system according to one of claims 2 or 3, characterized in that on the internal bus (IBU) of the memory chip (SPB) a cache coherence protocol expires. 5. Microprocessor system according to one of claims 2 to 4, characterized in that the cache coherence pro tokoll includes a "store-through" strategy.