DE19945900A1 - Configuration of trace interface in SoC-ASIC - Google Patents

Abstract

Non-reactive tracing of data and its state uses a semiconductor substrate based circuit arranged as a module. The circuit comprises a number of components and is connected at least to one system bus. The circuit further includes an arrangement of configuration registers for drawing the trace data out of the module via the trace interface. The registers are written in and read via a standard JTAG interface arranged on the integrated circuit. Several registers can be configured simultaneously.

Description

The subject of the application relates to an order, a procedure and the use of a standardized JTAG inter face's for retroactive tracking of data in a system-on-chip arrangement.

With System on Chip (SoC) architectures, different com components, e.g. B. microprocessors, RAMs and complex HW Control Logic arranged on a chip. To test a SoC design, it is essential to be able to "look" into the chip, d. H. record internal data streams. The selection of the on data to be recorded (data / address buses, control signals), and setting filters and trigger points for the Da Reduction is necessary to send the trace data to the test operator adapt requirements. The configuration of the tracer is allowed does not affect the real-time behavior of the system in any way because the systems are redundant in certain applications be set and thus a clock cycle accurate behavior require. Furthermore, the stability requirements prohibit every intervention in the real-time behavior.

It is necessary to send diagnostic data from registers to the outside and to give as feedback to the tracer (Regressi ves testing). The real-time behavior of the system in are not influenced in any way (without retroactive effect). Diagnosis data are a. Statistics and error information.

So far, the configuration / setting of the tracer was done not possible or only directly after system reset and under Be influencing real-time behavior. Reading the diagnosis So far sedate was only possible in the real-time behavior was disturbed.  

The subject of the application is based on the problem, a ver drive to track data in a SoC ASIC ben that the specified requirements while avoiding the given disadvantages.

The problem is defined by those defined in claims 1, 2 and 3 resolved objects.

The subject of registration takes advantage of that with the JTAG standard dinterface register can be written and read.

The configuration of the Trace interface's asynchronous / parallel by writing the configuration register via a standardized JTAG In interface.

Since JTAG uses its own clock TCK, the writing is and Reading the registers regardless of the system flow, the real time behavior is not disturbed. The registration tracer is just an observer and therefore passive. The interface at the An the object of the report is via a control interface, e.g. B. PC card can be operated interactively. The operator can be lukewarm system at the customer's connection to the JTAG interface plug in and trace internal data streams and thus analysis ren. In addition, he can and read out error information and draw conclusions from it draw further configurations of the tracer (regressive Te most).

Advantageous further developments of the object of registration are specified in the subclaims.

The subject of registration is hereinafter referred to as execution example to the extent necessary for understanding hand explained in more detail by figures. Show:

Fig. 1 shows a system-on-chip arrangement with an arrangement according to the JTAG standard and

Fig. 2 shows a trace access point on a system bus.

In the figures, the same designations denote the same elements ment.

Fig. 1 shows a JTAG arrangement having the configuration and diagnostic registers. JTAG is controlled by a PC (personal computer) with a plug-in card.

Registers can be written using the JTAG standard interface and be read. Since JTAG uses its own clock TCK, is the writing and reading of the registers from the system flow dependent, the real-time behavior is not disturbed.

The standard JTAG is used to configure the tracer Describe the configuration registers used.

The following information can be stored in the configuration registers:

• a) Trace access point select (selection of data record point)
• b) filter register
• c) Trigger mode register

Each trace access point is assigned a bit, the trace access Point-Select, selected.

The filter registers contain address, data, control and status values which are compared with the current values at the observation point (data recording point). The comparison result is evaluated by the trigger controller TR_CTRL. The values are:
Address value: Address on the address bus
Data value: data value on the data bus, bit field in the ATM cell or sensor value (automotive application)
Control value: bus control, e.g. B. Read, write, burst
Status value: state of the finite state machine, error codes

Each storage location in the filter register can have three values men: 0, 1 or don't care to mask areas.

The trigger mode registers store how the ver the same result is to be interpreted, d. H. whether the informa tion of the trace access point is passed on if the Comparison result <, <or equal. In addition, ge saves whether the result of the comparison result Trace starts or stops at the trace access point.

Also for reading long-term data from the diagnosis regions a JTAG configuration is used. Long-term data are information from SoC components such as Status, error and statistical information. You will be dated System written in diagnostic register.

The diagnostic information is:
Status information: utilization of the system buses, utilization of the buffers etc.
Error information: Errors such as B. synchronization errors, clock failures at interfaces, overflow of buffers
Statistics information: frequency of errors.

The JTAG interface can be interactively controlled interface, e.g. B. PC (Personal Computer) card operated who the. The operator can run the system in the customer's system Connect to the JTAG interface and internal data trace and analyze currents. In addition, he can the statistical and error information during operation read.

The software on the PC (personal computer) is expanded bar that the PC reads the diagnostic register and if necessary independently configures the tracer so that it specifically targets Da  ten to confirm the diagnosis (Regressive Te most).

As already mentioned, the JTAG arrangement shown in FIG. 1 is controlled by a PC (personal computer) with a plug-in card.

The data recording point control TAP_CTRL (for: trace Access point controller) recognizes the command that the conf gurationsregister K_REG should be loaded. She enters Signal to the configuration control K_CTRL, which the confi guration information from the shift register SR_K into the con configuration register K_REG writes.

In a preferred embodiment, the configurations onsregister all described at the same time. That has the intent partly that no complex coding is necessary.

The data recording point controller TAP_CTRL recognizes the Command that the content of the diagnostic register D_REG in the Shift register SR_D should be saved. She enters Signal to the diagnostic control D_CTRL, which contains the content of the Writes diagnostic register to the shift register SR_D.

Application examples for configuration

An SoC ASIC (Application Specific Integrated Circuit) has generally one or more processors, memory, emp catcher and transmitter part. The components are about sy Stembusse, address bus A_BUS, data bus D_BUS connected.

Fig. 2 shows an example of a trace access point TAP of a system bus.

The TAP forms a trigger start signal TR_ST and a trig ger stop signal TR_SP for filtering out a desired one Information.  

Whenever the address range between the lower and upper Address range, the bus information (address and Da ten) written out of the SoC ASIC.

The operating mode is in the trigger mode register TM_REG saves. The two address values are in one configuration each tion register K_REG1, K_REG2 stored. If the bus address is in the address area, the trigger controller TR_CTRL the trigger start signal TR_ST. At the same time, the Bus information stored in the trace register. Is that If the address is not in the address area, the signal is triggered stop TR_SP activated.

Another example is the configuration of the tracer on Receiving part.

In a receiving section for signaling via ATM (Asynchronous Transfer Mode) between telecommunications Agencies can, for. B. the filter the virtual channel Compare number or cell information and then the tracer trigger.

With a SoC design in automotive applications, e.g. B. on the Content of a sensor signal can be filtered.

The filter on the transmitter part for signaling via ATM can e.g. B. compare the virtual channel number or cell information and trigger the tracer based on the result.

With a SoC design in embedded application, e.g. B. Reg filter settings.

It is state of the art that processors have their program counter ter and status (EJTAG standard) to the Pro to follow the gram flow. Filters can also be used here  who compare the program counter and because of the Trigger the comparison result.

Claims (4)

1. Arrangement for non-retroactive tracking of data and their status at the

• - A circuit realized on a semiconductor substrate is arranged in a module
• - The circuit is formed with several components that are connected via at least one system bus
• - The circuit has a plurality of configuration registers-sending device for leading out tracking information via a tracking interface from the module
• - The configuration registers can be written via a standardized JTAG interface arranged on the integrated circuit.

2. Procedure for non-retroactive tracking of data and their states in a system-on-chip arrangement follow the interface for tracking the data (trace Interface) via a standardized JTAG interface can be generated. 3. The method according to claim 2 characterized in that several through the data tracking interface (Trace interface) controllable configuration registers the same can be configured in time. 4. Use of a known JTAG interface for Configuration of a tracking interface (trace-in interface) in a system-on-chip arrangement.