DE19938513C2 - Device and method for synchronizing fast analog electronics - Google Patents

Abstract

The invention relates to a device for synchronizing fast analog electronics, which has an input for an analog signal of a digitally controlled sensor, which is operated with a clock CLK '. The device contains an output (3) for a digital signal, an analog processing stage (5) and an A / D converter (7) which receives the output signal of the analog processing stage (5) and is controlled by an internal clock CLK, to generate the digital signal. The device contains a digital circuit (19) which measures and adjusts the clock differences between the clock CLK 'for the sensor (13) and the clock CLK for the A / D converter (7). The invention also relates to a method for digitally measuring and adjusting the phase relationship of two clock cycles, one clock cycle being used to control a digitally controlled sensor and the other clock cycle being used to control an A / D converter (7) to which the output signal of the sensor ( 13) is fed after an analog processing.

Description

The invention relates to an apparatus and a method for Synchronization of fast analog electronics. Insbesonde re the invention relates to an apparatus and a method to the analog output signal of a digitally controlled sensor next to be processed analogously and then after an Ana output log / digital conversion (A / D conversion) synchronized.

Sensors are often controlled digitally. The sensor signal is then preprocessed analog and an analog / digital conversion un trained to be digitally processed later. Step Example le for this are a CCD sensor (charge coupled device) or a Echo sounder.

With the CCD sensor, control is carried out with the pixel clock. The Output signal is preprocessed analog to process the signal strengthen and shape the signal path. Then there is an Ana log / digital conversion, and the A / D converted signal becomes Wei terverarbeitung, such as given on a computer.

With an echo sounder, the trigger signal for the transmission takes place of the sound pulse digital. The response signal is echoed Analogue amplified and shaped receiver. The timing is done digital. In addition, there is often digital processing of the dates desired.

In the above applications, there is a problem that due to the anologic signal processing an unknown at first Pass-through delay time is introduced. For example, lies  the delay time alone against a signal processing chain often in the range of 10 to 100 nanoseconds when five ver Strength levels are cascaded in series.

If the signal is now digital before the analog processing chain is triggered and digitally evaluated at the end of the chain then the usual event sequence sequences of the order of 10 MHz or more the problem that the digital controller at the end of the analog chain must decide which of the events it triggered, et wa which video pixel or which sound pulse, the present processed signal corresponds.

There is also the problem that if the clock that the A / D Controls the converter, is not synchronized with the sensor signal, the A / D converter the analog input signal between two events nits, or on the flank of an event, abta continuously, that is, the data transient process is recorded.

A similar problem occurs when designing fast modems. The aim here is for the data sender to be as accurate as possible on the sampling clock of the digital telephone transmission link synchronized. Only then can the maximum data rate be transmitted become. With the 56 k modems, such as those used in the time font C't 1997 issue 1, page 90 by Herwig Feichtinger: "Un same sisters,. , , 56 k modems "are described first transmit digital computer signal as an analog signal and then at the junction with the digital phone line A / D-converted. It is desirable that the clock of ur original digital computer signal and the clock of digital scanned phone line are in phase with each other.

Up to now, a digital circuit has been provided for this purpose  Clock signal for controlling the sensor and a clock signal for Generate control of the A / D converter. These two clock signals had the same frequency and were phase locked to each other connected. A phase shift was introduced between them represents exactly the throughput delay time of the analog scarf matched. However, this phase relationship was set hung difficult. With the phase difference set once de the circuit then operated.

By scattering the characteristics of the individual components the analog circuit due to temperature fluctuations and / or However, fluctuations in the supply voltages are also subject to Pass-through delay fluctuations. This lead to the circuits with a fixed phase relationship are very high Requirements for the ambient temperature, the supply voltage and the selection of components.

An improved embodiment provided that the clock signal for the A / D converter goes through a processing chain that the Ana log processing chain was replicated. Here was however problematic that not all analog circuits, such as Maximum detectors or pulse shapers, suitable for digital signals.

Ultimately, the prior art was subject to at least one of the following three parameters:

• - reliability;
• - Permissible component tolerances, temperature and operation tension;
• - Achievable speed (frequency).

From the document US 5 914 991 A are circuits to measure and for setting an internal clock of an A / D Known converter with the clock of an external controller. With Using a digital PLL circuit becomes dependent on the clock the clock of the A / D converter is adapted to the external control. The document [2] can therefore only be seen that the document ment [1] analog version of the PLL circuit also as digi tale PLL circuit can be performed.

In document DE 693 16 043 T2 there is a scan generator for described a digital demodulator. From this document is known the internal clock frequency of an analog-digital Converter for converting analog signals into digital signals adapt. However, this document does not contain knows how to synchronize between the internal clock of the analog-to-digital converter and an analog signal digitally controlled sensor can take place.

Document EP 0 756 417 A2 describes a device for Video signal processing with an automatic phase position of the sampling times known. A special image signal that contains only two selected gray values becomes automa table phase setting used. But like a re-measurement and adjusting the clock difference between the internal clock of the A / D converter and the clock for controlling the sensor any analog signal of a digitally controlled Sensor can be done is not known.

From document DE 197 14 142 C1 is a phase detector for a phase locked loop (PLL circuit) is known. With the help of Phase locked loop is entered a second clock frequency applies that the second bar to a first bar even then has a fixed phase relationship when the two bars ver have different frequencies. From this document [5] is ever not known how a variable phase relationship between two equal frequency cycles can be adjusted.  

From the summary of document JP 60-208174 A is an input circuit for analog video signals known with the help of the line clock (HSync) a pixel clock, the so-called pixel clock. This pixel clock is used for the Analog-digital in the input circuit Change needed. This input circuit contains one Input for an analog signal, an output for a digital signal, an analog processing stage, an A / D converter, to receive an output signal of the analog processing is switched and controlled with an internal clock ert, as well as an analog circuit, the clock difference between the internal clock of the analog-digital converter and measures and adjusts a second bar, which from the Vi deo signal is determined. The video signal source is not digitally controlled. The analog circuit is a well known Phase controller (PLL), which is used for frequency multiplication and not for readjusting drifting phase shifts analog amplifier circuits can be used. The Clock signal (CLK) of the analog-digital converter can therefore not with the clock signal of a digitally controlled sensor and be synchronized reliably. There is also no possibility known when synchronizing one through the analog Signal processing caused variable phase shift too consider.

The invention has the task of a safe and reliable To ensure synchronization of the fast analog electronics Afford.  

According to the invention, the object is achieved by a device according to the Features of claim 1 and by a method with the Merk paint the claim 10 solved. The dependent claims concern further advantageous aspects of the invention.

The device for synchronization faster analog electronics contains an input for an analog signal a digitally controlled sensor, an output for a Digi tal signal, an analog processing stage, an A / D converter, that for receiving an output signal of the analog processing stage is switched and controlled with an internal clock. The device is characterized in that it furthermore a digital circuit that contains the clock difference between the clock for controlling the sensor and the clock for the A / D Converter measures and adjusts.

The digitally controlled sensor can be an echo sounder, a CCD sensor or be a modem.

Monitored according to an advantageous aspect of the invention the digital circuitry the output values of the A / D converter and regi shows the number of cases in which two successive digital values by more than a predetermined amount divorce. The digital circuit is designed to this number to minimize. This embodiment is in particular together associated with CCD sensors advantageous, in which the output usually do not value two consecutive pixels distinguish clearly. Repeated occurrence of large differences de two consecutive digital values indicates that the A / D sensor does not sample the correct value of the signal, but that the sampling time of the A / D converter on the edge of the signal sits.  

According to a further advantageous aspect of the invention the digital circuit monitors the digital values that the A / D Sensor outputs and maximizes them. In different areas the electronics uses pulse amplitude modulation (PAM). If such a signal after analog preprocessing A / D- is converted, the sampling time of the A / D converter in the Im pulse maximum. Again, it is advantageous if on do not overly distinguish successive digital values.

The phase relationship between the clock for the sensor and the clock of the A / D converter can be set using a counter circuit be operated with a much faster clock. Alternatively, the phase relationship can be established using a threshold value and a ramp signal can be set. For this points the digital circuit is a circuit for generating a ramp gnals and a comparator circuit. The beat for the A / D Conversion is triggered when the ramp signal hits the threshold exceeds. The time can be changed by changing the threshold value to trigger the A / D clock.

The analog processing stage of the device according to the invention can be from a variety of individual processing stages, such as Ver amplifiers, signal formers, Maximus detectors, etc. continue to exist.

According to the synchronization method according to the invention faster electronics an input signal is prepared that the Output signal of a digitally controlled sensor is. The entrance besignal is processed analog and then one Analog-to-digital conversion in an A / D converter subjected by is controlled by an internal clock signal. The invention The method is characterized in that the phase relationship of the two clock signals for the sensor and the analog-digital converter  is constantly digitally measured and adjusted.

In the following, the invention is described in detail with reference to a preferred embodiment with reference to the accompanying Described drawings in which:

Fig. 1 is a block diagram of an apparatus according to the invention;

Figure 2 shows a first part of a flowchart for explaining the operation of the device according to the invention.

FIG. 3 shows another part of the flow chart from FIG. 2.

The apparatus of Fig. 1 comprises a sensor 13, such as a CCD sensor. This is connected to an analog processing stage 5 with several sub-processing stages. The output signal of the CCD sensor 13 is fed to the A / D converter 7 after the analog processing by the processing stage 5 . The A / D converter 7 outputs a digital signal which represents digital image data and can be further processed, for example, by a computer (not shown). In the embodiment shown, the device further comprises an oscillator 17 which generates a first clock signal CLK '. The first clock signal CLK 'is input to the CCD sensor 13 and controls the output of this sensor. With each rising or falling edge of the clock signal CLK ', the CCD sensor 13 outputs a voltage signal for a pixel.

The clock signal CLK 'is further fed to a digital circuit 19 . The digital circuit 19 also receives the output signal of the A / D converter 7 . The output signal of the digital circuit 19 is fed to the A / D converter 7 and serves the latter as an internal clock signal CLK.

The digital circuit 19 , which can contain a microprocessor, carries out a control algorithm in order to match the clock of the A / D converter 7 to the analog processed sensor signal. This internal clock signal CLK output by the digital circuit 19 has the same frequency as the clock signal CLK 'of the oscillator 17 . Compared to this clock signal CLK ', the internal clock signal CLK is out of phase by dp.

The digital circuit 19 determined on the basis of the output signal of the A / D converter 7 dp the correct value of the phase shift.

To determine the correct phase relationship dp between the at Different approaches are possible for the clock signals CLK 'and CLK. For example, a so-called "sparkle" detection can be used become.

If, at the time of sampling when the A / D converter 7 samples an ana signal 7 at its input, the analog signal to be converted changes too quickly, then the conversion becomes uncertain. There are digital output words that fall out noticeably from the temporal course of the neighboring digital signals. These signal points "Sparkle" flash in pictures, so to speak.

The appearance of such "sparkles" is a clear sign for that the A / D converter is overwhelmed (for example by the rate of change of the analog signal too high). Is the Sampling time due to undesirable influences from the design time window, so is the occurrence of this To calculate Sprakles codes.

Especially if it is known from the sensor data that between two consecutive values, no large changes  this procedure can be used. On An example of this is the reproduction of image information. The An image is scanned by means of a CCD sensor moderately so that narrow periodic patterns (picket ne) do not lead to moiree effects. You avoid this effect through spatial frequency low-pass filters, a kind of soft focus that is too fei blur pictorial details before the picture is strictly on the periodically divided optoelectronic converter arrives. at the video can correctly measure such a low pass signal from sharp object edges from one pixel to the next only change by a maximum of approx. 30% of the value range.

The digital output signal of the A / D converter is monitored over a predetermined number of successive clock cycles. A counter is incremented each time the change in two consecutive digital output signals exceeds 30% of the value range. The digital circuit 19 now controls the phase difference between the two clock signals CLK 'and CLK so that the number of these events is minimized. For this purpose, the digital circuit 19 changes the phase difference dp by a small amount in one direction and checks whether the frequency of the events has increased or decreased. If it has increased, the change was made in the wrong direction. If it has decreased, the change has been made in the right direction. In the subsequent step, the phase difference between the two clock signals CLK 'and CLK is accordingly changed again in the opposite or in the same direction, and the number of events is again monitored. The phase difference is now constantly changing in the same direction until the frequency of events has become minimal. At this minimum value, the phase difference is set. The checking of the correct phase relationship of the two clock signals CLK 'and CLK is advantageously repeated periodically.

Another approach shown in Figs. 2 and 3 aims to maximize the digital values of the output signal. Pulse amplitude modulation (PAM) is used in various areas of electronics. The video signal from a CCD sensor is used as an example.

If such a signal is converted after analog preprocessing A / D, the sampling time of the A / D converter must be at the pulse maximum. If this is not the case, the A / D converter 7 can get on the pulse edge and the scanning result becomes uncertain. In addition, the linearity of the signals among one another is lost during a scan on the signal edge. In addition, even slight jitter has a very strong influence on the scanning result.

An example of this maximum detection is shown in the flow chart shown in FIGS . 2 and 3. In this example, the clock CLK for the A / D conversion is shifted by one tenth of the clock period in ten successive pixel lines of a CCD sensor 13 . Successive lines are used here only to reduce the amount of memory. The result would be more accurate if the same line was used ten times.

The step is started in step 0 from FIG. 2 (switch-on normalization).

In step 1 , the delay dp is set to a minimum value, for example 0.

In step 2 , the initial value for the line number Z1 is set to 1, the pixel P to 1 and the maximum gray value M (Z) is also set to 0.

With steps 3 to 6 , the highest pixel gray value is looked up from the respective line, namely the line with the number Z, and stored under M (Z). In detail, step 3 waits for the beginning of the line with the number Z, namely for the horizontal synchronization signal HSYNC. In step 4 , the current pixel gray value GW (P) is compared with the maximum gray value of line M (Z). If necessary, the maximum gray value M (Z) is updated in step 4 a. In step S it is then checked whether the end of the line has been reached. Otherwise, step 6 continues with the next pixel.

In the subsequent step 7 , the delay d (Z) associated with M (Z) is stored and then dp is increased by an amount i, where i in the selected example is one tenth of the clock period. The line number is also advanced, the pixel counter being set to the beginning of the line and the maximum gray value of the line being set to 0.

Now, if determined in step 8 that not all 10 lines have been processed, then the next line is taken to step 3 in attack and ran off with the steps 3 to 6 the next maximum gray value and stored.

In the example shown, 10 maximum gray values for each of the scanned lines are stored in corresponding memory locations M1 to M10 in this way.

In the subsequent steps 9 to 14 , the largest is selected from the line maximum gray values M1 to M10 and the associated value dp of the delay is stored. This deferrers dp delay can henceforth the digital circuit 19 operate.

The sequence of the flow chart from FIGS . 2 and 3 is preferably used as the initial setting in the test field after the completion of the product. If a drift in the throughput delay must be expected due to temperature fluctuations or fluctuations in the supply voltage, the digital circuit 19 will preferably correct the used dp values at regular intervals. For this purpose, the value dp can be changed experimentally by one tenth to three tenths of the cycle period, and a check can be carried out to determine whether a new maximum can be found.

Although the invention has been described using a preferred embodiment, it is not limited to this. Instead of the CCD sensor 13 shown , the input signal can also come from a computer modem, an echo sounder or another digitally controlled sensor.

The setting of the change in the phase relationship between the clocks CLK and CLK 'can be done by means of a counter in the digital circuit 19 , which is operated with a much higher clock be.

Another possibility is the setting via a ramp signal and a threshold, as it is e.g. B. by an AD9500 from Analog Devices is performed.

Claims (10)

1. Device for synchronizing fast analog electronics with:
an input ( 1 ) for an analog signal from a digitally controlled sensor ( 13 ),
an output ( 3 ) for a digital signal,
an analog processing stage ( 5 ),
an A / D converter ( 7 ), which is connected to receive an output signal of the analog processing stage ( 5 ) and is controlled with an internal clock signal (CLK), characterized in that a second clock signal (CLK ') signals the sensor ( 13 ) controls, and that the device further includes a digital circuit ( 19 ), the clock difference (dp) between the internal clock signal (CLK) of the A / D converter ( 7 ) and the second clock signal (CLK ') for control of the sensor ( 13 ) measures and adjusts, the digital circuit ( 19 ) being supplied with the second clock signal (CLK '). 2. Device according to claim 1, characterized in that the analog signal is the output signal of an echo sounder. 3. Device according to claim 1, characterized in that the analog signal is the output signal of a CCD sensor. 4. The device according to claim 1, characterized in that the analog signal is the output signal of a modem. 5. The device according to claim 1, characterized in that the digital circuit ( 19 ) controls the phase relationship of the two clocks (CLK, CLK ') so that the number of changes in the digita len output value over a predetermined number of consecutive samples are greater than a predetermined limit value is minimized. 6. The device according to claim 1, characterized in that the digital circuit ( 19 ) controls the phase relationship of the two clocks (CLK, CLK ') so that the value of the sampling of the A / D converter ( 7 ) is maximized. 7. The device according to claim 1, characterized in that the digital circuit ( 19 ) controls the phase relationship of the two clocks (CLK, CLK ') by means of a digital counter circuit which is operated with a much faster clock. 8. The device according to claim 1, characterized in that the digital circuit ( 19 ) controls the phase relationship of the two clocks by changing a reference voltage, the Digi tal circuit ( 19 ) includes a ramp signal generating circuit and a comparator circuit, and wherein the internal clock for the A / D converter ( 7 ) is triggered when the ramp signal exceeds the reference voltage. 9. The device according to claim 1, characterized in that the analog processing stage ( 5 ) has a plurality of sub-stages ( 5 ). 10. Procedure for synchronizing fast analog electronics with the steps:
Preparing an analog input signal of a digitally controlled sensor ( 13 ),
analog processing of the input signal, and
Converting the processed input signal into a digital signal with an A / D converter ( 7 ) which is controlled by an internal clock signal (CLK),
characterized in that
the signal output of the sensor ( 13 ) is controlled using a second clock signal (CLK '), and that
the phase relationship of the internal clock signal (CLK) for the A / D converter ( 7 ) and the second clock signal (CLK ') for the control of the digitally controlled sensor ( 13 ) is measured and readjusted with the aid of a digital circuit ( 19 ), whereby the digital circuit ( 19 ) the second clock signal (CLK ') is supplied.