DE19936939A1 - Data processing device and method for its operation to prevent differential power consumption analysis - Google Patents

Abstract

The invention relates to a data processing device (100) and to a method for operating the data processing device, notably a chip card. Said device comprises an integrated circuit which in accordance with a clock pulse carries out calculating operations, especially cryptographic operations, data inputs and outputs and data transfers from and to registers of the integrated circuit. To this end the integrated circuit (10) is controlled such that the calculating operations, on the one hand, and the input/output of data and data transfer from register to register or between registers, on the other hand, are carried out time-parallel.

Description

Technical field

The invention relates to a method for operating data processing processing device, in particular a chip card, with an integrated Circuit which, depending on a clock signal, computing operation NEN, especially cryptographic operations, data input or expenditure as well as a data transfer between registers of the integrated Circuit performs, according to the preamble of claim 1. The Erfin dung also relates to a data processing device, in particular Chip card, in particular for executing the method, with an inte ized circuit, which is a function of a clock signal Re performs operations, in particular cryptographic operations, wherein the integrated circuit is an arithmetic unit with an associated first Has registers and data inputs and outputs, according to the preamble of claim 3.

State of the art

In many data processing devices with integrated circuit serve at for example cryptographic operations to protect the company This device or to protect data transported in the device. The necessary arithmetic operations are carried out by Stan dard calculators as well as dedicated crypto calculators carried out. A typical example of the latter are chip cards or IC cards. Cards. For data used in this context or intermediate The results are usually safety-related  Information such as cryptographic keys or opes run out.

In arithmetic operations performed by the integrated circuit, for example, to calculate cryptographic algorithms, who the logical links between operands and intermediate results nits carried out. Depending on the technology used perform these operations, especially loading empty or previously deleted memory areas or registers with data, to an increased power consumption of data processing equipment. With complementary Logic, such as CMOS technology, causes an increased current consumption use up when the value of a bit memory cell is changed, d. H. its value changes from "0" to "1" or from "1" to "0". The heightened Consumption depends on the number of ge in memory or register changed bit positions. In other words, loading one leaves before deleted register a power consumption proportional to Hamming weight of the operand written in the empty register (= number of Bits with the value "1") increase. Through an appropriate analysis the This current change could make it possible to obtain information about the be expected operations to extract, making successful crypto analysis of secret operands, such as cryptographic ones Keys, is possible. By performing several current measurements on the data processing device, for example, with very small Si Changes in the signal allow sufficient extraction of the information become light. On the other hand, several current measurements could enable required difference formation. This type of cryptanalysis is also referred to as "differential power analysis", by means of which a Outsider by simply observing changes in the current consumption of the data processing device may be unauthorized Cryptanalysis of cryptographic operations, algorithms, operans  which data can successfully execute. The "Differential Power Analy sis "thus enables additional in addition to pure functionality to be able to obtain internal information from an integrated circuit.

From US 5 297 201 it is known to emit a high frequency To combine computers with a device, which is also a Radio frequency similar to that of the computer emits. This is it is no longer possible for an unauthorized third party to decode radiation from the computer. A cryptanalysis by a third party who has direct access to the computer, the However, do not prevent this system.

WO 90/15489 describes a secure communication system, at the dummy traffic or transmissions are generated to cryptogra to complicate physical analyzes. A third party cryptanalysis, this system can, however, have direct access to the computer cannot be prevented either.

Presentation of the invention, task, solution, advantages

It is an object of the present invention to provide an improved method and an improved data processing device of the above To provide type that have the disadvantages mentioned above effective protection against a "differential power analy sis ".

This task is accomplished by a method of the above. Kind with the in claim 1 characterized features and by a data processing direction of the above Kind with the features characterized in claim 3 solved.  

For this it is in the process of the above. Provided according to the invention, that the integrated circuit is controlled such that the execution of arithmetic operations on the one hand and the data input / output as well as the Data transfer from register to register or between registers and others on the other hand is carried out in parallel.

This has the advantage of being indicative of a "differential power analysis" There are no points for when an arithmetic operation ends or when Reading / writing of registers or when a data input / output occurs because time ranges of both the actual calculations as well the data input and output are obscured. The "differential Power Analysis "is thus made considerably more difficult since it is no longer possible from the outside it can be determined whether a real calculation or an input / Issue takes place.

In an advantageous further development of the method, further Obfuscate computing operations and data input / output immediately cash before, during and / or immediately after the data transfer between the registers of the integrated circuit dummy calculations from one Calculator of the integrated circuit, which is random or edit predetermined data, with no data in register of inte circuit can be written.

In a data processing device of the above-mentioned. It is kind of fiction provided that a second one connected to the first register A register is provided which has the data inputs and outputs, wherein a control unit is also connected to the integrated circuit which is designed in such a way that it operates simultaneously in time the register for data input / output and data transfer between the  Registers on the one hand and arithmetic operations of the arithmetic unit of others controls.

This has the advantage of being indicative of a "differential power analysis" There are no points for when an arithmetic operation ends or when Reading / writing of registers or when a data input / output occurs because time ranges of both the actual calculations as well the data input and output are obscured. By the second Register is an input / output of data possible while computing factory is active and possibly writes data to the first register or writes data out the first register. The "Differential Power Analysis" is thus considerably more difficult because from the outside with suitable control of the two ten registers can no longer be determined whether a real loading invoice or an input / output takes place.

In an advantageous further development of the data processing device The first register is an operand register of the arithmetic unit and / or the second register is an operand register of the data input / -output.

Brief description of the drawings

The invention will now be described with reference to the accompanying drawings explained in more detail. These show in

Fig. 1 is a block diagram of a preferred embodiment of a data processing device according to the invention,

Fig. 2 is a block diagram of an integrated circuit of the movement of such data processing device of Fig. 1,

Fig. 3 is a graphical illustration of the activity of the inventive data processing device over time according to the prior art and

Fig. 4 is a graphical illustration of the activity of the inventive data processing device over time according to the invention.

Best way to carry out the invention

Fig. 1 shows a preferred embodiment of a data processing device 100 according to the invention with an integrated circuit 10, a register 12 with access program 14, and a control unit 16. The control unit 16 and the integrated circuit receive a clock signal 20 shown in FIGS. 3 and 4 via line 18 . Via control lines 22 , the control unit 16 controls the integrated circuit 10 which has data inputs 24 and data outputs 26 .

A Re is as shown in FIG. 2, the integrated circuit 10 chenwerk 28, a calculating unit 28 the associated first operand register 30 and connected to the first operand register 30 first operand register 32. The data inputs 24 and data outputs 26 are arranged on the second operand register 32 . The clock signal 20 ( FIGS. 3 and 4) is forwarded via line 18 both to the arithmetic logic unit 28 and to the two operand registers 30 and 32 . When calculations or operations are carried out by arithmetic unit 28 , it reads data from first register 30 or writes a result of a calculation into first register 30 . A corresponding data exchange or a mutual data transfer takes place between the registers 30 and 32 , hereinafter referred to as R2-1 if data is transferred from the second register 32 to the first register 30 , or referred to as R1-2 if data from the first register 30 are passed to the second register 32 . One of the control lines 22 coming from the control unit 16 is connected to the second register 32 for its control, while another control line 22 is connected to the first register 30 for its control.

A "Differential Power Analysis" published by Paul Köcher on the Internet at http://www.cryptography.com/dpa has the approach that in addition to the input / output signals, a current consumption I _a or voltage drops ΔU _{a of} a supply voltage U _a integrated circuit are analyzed. The success of this analysis method depends on whether one has a number N _A of analog (I _a (t) or ΔU _a (t)) signals S (k, t) over time with k = {1,. . ., N _A } can accommodate different operands in such a way that a summation of the form

with the coefficients p (i, k) with i = {0, 1, 2,. . .} is possible. If one considers different signal profiles S (k ₁ , t ₁ ), S (k ₂ , t ₁ ), S (k ₃ , t ₁ ). . . at the same time t = t ₁ , a "differential power analysis" can only work if the integrated circuit at this moment has the same computing operation with different operands k = {1,. . ., N _A } executes, ie the signal curves S (k, t) must be able to be superimposed exactly. This applies not only to the calculation itself, but also to the input and output of data.

The invention obscures both the time ranges, the actual calculation and the time ranges of the data input and output. When the second register 32 is activated appropriately, it can no longer be determined from the outside when an actual calculation or an input / output takes place. The "differential power analysis" is thus made considerably more difficult. The integrated circuit 10 is equipped according to the invention with the two operand registers 30 and 32 . These allow data to be input and output via the second operand register 32 with its data inputs 24 and data outputs 26 even while the arithmetic unit 28 is active using the first operand register 30 and executes calculations or operations.

Fig. 4 illustrates an operation of the data processing device according to the invention 100 with a time axis 34, the Taktsi gnal 20 and an operating state of the processing unit or Operandenregi star indicated. Here, 36 denotes an operating state in which the arithmetic unit carries out a calculation. 38 denotes an operating state in which data is input or output, 40 denotes an operating state in which data transfer R1-2 takes place and 42 denotes an operating state in which data transfer R2-1 takes place.

Fig. 3 illustrates in an analogous to Fig. 3 representation for comparison, an operation of a conventional data processing device. Here, the input and output phases 38 of the actual calculation 36 are connected upstream or downstream. In "differential power analysis", the phases of the calculations 36 and the input / output 38 can be easily identified, in particular which inputs 38 are used in a calculation 40 and which outputs 38 are the result.

Shown at in FIG. 4, operation of the present invention by means of the control unit 16, the calculations 36, and the data input / expenditure 38, 40, 42 obscured by the fact that the data flow of the two operand registers 30, 32 in time ge parallel to the calculator 36 controls becomes. Calculations 36 always take place. However, whether a calculation 40 depends on the input 38 or provides an output 38 is determined by the copy actions R1-2 40 and R2-1 42 . The calculations before R2-1 42 and after R1-2 40 are, for example, dummy calculations. Dummy arithmetic operations are arithmetic operations which process predetermined or randomly selected input data, the result being rejected and not being included in the results or input data of the actual arithmetic operations. Additional Dum myein - / - editions are also optionally provided. Both the dummy calculations and the dummy inputs / outputs generate current and voltage changes which are very similar to those of the actual calculations and inputs / outputs.

The present invention ge to protect the integrated circuit components 10 gen "Differential Power Analysis" provided control unit 16 aims spe essential to the input / output phases 38, 40, 42 of a digital in the integrated circuit elements 10 by means of electronic signal processing calculations 36 to be carried out from, since I / O could also be analyzed based on power consumption using the "differential power analysis". Accordingly, in "differential power analysis" it is of interest when a calculation 36 begins or ends. Precisely this information is suppressed by the method according to the invention or in the device according to the invention in the power consumption signal.

Reference list

100

Data processing device

10th

integrated circuit

12th

register

14

Program access

16

Control unit

18th

management

20th

Clock signal

22

Control lines

24th

Data inputs

26

Data outputs

28

Calculator

30th

first operand register R1

32

second operand register R2

34

Timeline

36

calculation

38

Data input or output

40

Data transfer R1-2

42

Data transfer R2-1

Claims (4)

1. Method for operating a data processing device ( 100 ), in particular a chip card, with an integrated circuit device ( 10 ) which, depending on a clock signal, computing operations, in particular cryptographic operations, data inputs and outputs ( 38 ) and data transfer ( 40 ) from or to registers of the integrated circuit ( 10 ), characterized in that the integrated circuit ( 10 ) is controlled such that the execution of arithmetic operations on the one hand and the data input / output ( 38 ) and the data transfer ( 40 ) from register to register or between registers ( 30 , 32 ) on the other hand is carried out in parallel. 2. The method according to claim 1, characterized in that immediately before, during and / or immediately after the data transfer from register to register or between the registers ( 30 , 32 ) of the integrated circuit dummy calculations by egg arithmetic unit ( 28 ) of the integrated Circuit ( 10 ) are executed, which process random or predetermined data, where no data are written in registers ( 30 , 32 ) of the integrated circuit. 3. Data processing device ( 100 ), in particular chip card, in particular for executing a method according to at least one of the preceding claims, with an integrated circuit device ( 10 ) which, depending on a clock signal ( 20 ), performs computing operations, in particular cryptographic operations wherein the integrated circuit (10) an arithmetic unit (28) with an associated first register (30) and data inputs and outputs (24, 26), characterized in that one end connected to the first register (30) second register (32 ) is provided, which has the data inputs and outputs ( 24 , 26 ), a control unit ( 16 ) also being connected to the integrated circuit ( 10 ), which is designed such that it operates the registers ( 30 , 32 ) for data input / output ( 38 ) and data transfer ( 40 ) from register to register or between registers ( 30 , 32 ) on the one hand and re che Operations ( 40 ) of the computing unit ( 28 ) controls on the other hand. 4. Data processing device ( 100 ) according to claim 3, characterized in that the first register ( 30 ) is an operand register of the arithmetic unit ( 28 ) and / or the second register ( 32 ) is an operand register of the data input / output ( 38 ).