DE19936676A1 - Interpolating memory circuit arrangement e.g. for computer graphics - Google Patents

Abstract

A memory/storage circuit arrangement has an address input (1) and s data output (2), as well as a memory/storage circuit (3) with a number of addressable memory cells. Also included in the circuit arrangement is an interpolation circuit (4) with at least one data input (5,6) for the data to be interpolated, a coefficient input (7) for input of weighting coefficients for the interpolation, and a results output. The address input (1) comprises lines (8) for addressing the memory cells as well as lines (9) connected to the coefficients input (7), and the results output of the interpolation circuit is connected to the data output (2). The memory/storage circuit (3) is specifically a dual-port-RAM.

Description

The present invention relates to a memory circuit order with an address input and a data output as well a memory circuit that has a plurality of addressable Includes memory cells.

In various technical fields of application, one becomes faster Access to interpolated values from stored data is required such as computer graphics or di gital mobile communications. Especially with digital mobile radio This problem occurs when evaluating an emp catch signal only a limited number of samples of the Received signal can be obtained, each determined Correspond to sampling times in later processing but values are needed, the times between the ab correspond to tactile times.

One way to get such intermediate values for a quick Providing access is by interpolation calculate and sample values and interpolated values of their time order in a memory filing circuit. Access to a saved value is done by addressing one at the respective time speaking memory cell.

It is obvious that the memory requirement for a sol Chen solution proportional to the fineness of the required In terpolation increases. In addition, the Interpo is won lation values associated with a considerable computational effort, which is in vain in many applications, since only one small percentage of the calculated interpolation values did is actually read.

The object of the present invention is a storage scarf arrangement of the type defined at the outset, which allows quick access to interpolated data because with a low memory requirement and the computing effort keeps low for interpolation.

The object is achieved in that the memory circuit arrangement is equipped with an interpolation circuit, the at least one data input for data to be interpolated a coefficient input for entering weighting coefficients of interpolation and a result output has, the address input of the memory circuit arrangement cables used to address the memory cells NEN, as well as lines connected to the coefficient input are connected, and being the result output of Interpola tion circuit with the data output of the memory circuit an order is connected.

The lines connected to the coefficient input preferably correspond to address bits with low significance. In this way it is possible, for example, if there are two lines connected to the coefficient input, by entering addresses 0, 4, 8 (which do not differ in their two lowest bits) at the address input of the memory circuit arrangement to address successive addresses of the memory circuit , and by entering addresses 1 , 5 , 9,. , .; 2, 6, 10 and 3, 7, 11 respectively. , , to address the same memory cells and at the same time to specify weighting factors ¼, ½, ¾ for the interpolation circuit on the two low-order lines.

Since at least two output values are required for an interpolation Tigt and this as quickly as possible, preferably immediately should be available in time, is preferably used as Memory element uses a dual-port RAM that is the same timely query of two memory locations allowed.  

The required address of the second memory location is used moderately generated by an incrementing circuit that is on the lines used to address the memory cells is connected to a transmitted on the lines Increment address value. This incremented address value is used to address the second address input of the dual-port RAMs used.

Further features and advantages of the invention result from the following description of exemplary embodiments with Reference to the figures.

Show it:

Fig. 1 is a block diagram of a memory circuit arrangement according to the invention; and

Fig. 2 shows the result obtained when reading data from the memory circuit arrangement in relation to a reception signal, by the scanning of which the data stored in the memory circuit arrangement have been obtained.

The memory circuit arrangement shown in FIG. 1 as a block diagram has an address input 1 with a width of n bits. Two coefficient lines 9 are connected to the bits with the lowest value of the address input 1 , the higher-order bits are connected via address lines 8 to a first address input 11 of a dual-port RAM 3 . A second address input 12 of the dual-port RAM 3 is connected to the address lines 8 via an incrementing circuit, via which it always receives an address value that is 1 greater than the value simultaneously applied to the first address input 11 .

Two data outputs of the dual-port RAM 3 are connected to data inputs 5 , 6 of an interpolation circuit 4 and deliver the values stored in the memory cells addressed via the address inputs 11 , 12 at the same time.

The interpolation circuit carries out a linear interpolation of the values present at its data inputs 5 , 6 , wherein it uses the two least significant bits of the address entered into the circuit arrangement for the weighting of the values at its coefficient input 7 via the coefficient line 9 .

The result output of the interpolation circuit 4 simultaneously forms the data output 2 of the circuit arrangement. To use the circuit arrangement, it is sufficient to enter the measurement data to be interpolated in their chronological order in the dual-port RAM. The behavior of the circuit is then indistinguishable from the outside from that of a four times larger memory circuit in which the same measurement data with interposed, previously calculated interpolation data are stored.

Fig. 2 shows as a solid curve 20 the course of a function or a measurement signal, by the Abst stung at two successive times x1 and x2, a pair of samples, shown by the arrows 21 , 22 , obtained in the dual-port RAM 3rd are stored at consecutive addresses. By entering the address of the sample value 21 on the n-2 high-order bits of the address input 1 , both sample values are addressed and appear at the data inputs 5 , 6 of the interpolation circuit. If the two least significant bits at the address input are 0, this corresponds to the exact addressing of the sample value 21 . The interpolation circuit 4 therefore evaluates the sample value 22 with the value 0 encoded on the coefficient line and the value 21 with its complement 1 , so that the value 21 appears as an output at data output 2 . If the value on the coefficient line is a value m other than 0, then the value 22 is weighted with m / 4 and that of the value 21 with the complement, and a correctly interpolated intermediate value, corresponding to one of the arrows 23 shown in broken lines, is used received at data output 2 .

Depending on the required resolution or interpolation, the circuit arrangement according to the invention can also have only a single coefficient line 9 or more than two.

Of course, the invention is not limited to linear interpolation. In order to carry out higher order interpolation with more than two output values, it is sufficient to increase the number of incrementing circuits and the inputs and outputs of the memory 3 and to use a corresponding interpolation circuit. It is also conceivable, for example for an interpolation with four output values, to use the same dual-port RAM as in the circuit arrangement of FIG. 1 and to read out and, if necessary, buffer the required output values for the interpolation in two successive accesses.

Claims (5)

1. Memory circuit arrangement with an address input ( 1 ) and a data output ( 2 ) and a memory circuit ( 3 ) with a plurality of addressable memory cells, characterized in that it has an interpolation circuit ( 4 ) with at least one data input ( 5 , 6 ) for interpo data, a coefficient input ( 7 ) for entering weighting coefficients of the interpolation and a result output, the address input ( 1 ) comprising lines ( 8 ) which are used to address the memory cells and lines ( 9 ) which are connected to the coefficient input ( 7 ) are connected, and the result output of the interpolation circuit is connected to the data output ( 2 ). 2. Memory circuit arrangement according to claim 1, characterized in that the lines connected to the coefficient input ( 7 ) ( 9 ) correspond to address bits with a low value. 3. Memory circuit arrangement according to one of the preceding claims, characterized in that the storage circuit ( 3 ) is a dual-port RAM. 4. Memory circuit arrangement according to one of the preceding claims, characterized by an incrementing circuit ( 10 ) which is connected to the lines ( 8 ) used for addressing the memory cells in order to increment an address value transmitted on the lines ( 8 ). 5. A memory circuit arrangement according to claim 3 and claim 4, characterized in that the dual-port RAM ( 3 ) has a first address input ( 11 ) which is directly connected to the lines ( 8 ) serving to address the memory cells, and one with the incrementing circuit ( 10 ) verbun which has second address input ( 12 ).