DE19928544A1 - Clock divider circuit arrangement especially for DECT - Google Patents

Abstract

The circuit arrangement includes a counter (4) to which an input clock signal (fT) is fed. A comparator (3) compares the count of the counter (CNT) with a determined dividing factor (X). The comparator drives the counter so that the count of the counter is incremented according to the input clock signal if the current count does not correspond to the stored dividing factor. A reset unit (19-24) resets the count of the counter if the current count corresponds with the dividing factor.

Description

The present invention relates to a clock divider Circuit arrangement for dividing a clock, in particular a clock divider circuit arrangement for dividing down a clock according to a freely programmable divider factor.

Clock dividers are required in different applications, around from an available high frequency scarf to derive a low-frequency clock. This is required, because often parts of an integrating circuit with a different clock than the rest of the scarf work.

Known clock dividers are integrated in terms of hardware th circuits designed, the divider factor and so with the clock ratios fixed by the hardware and are not variable.

EP 0 606 912 A2 describes a multi-phase Clock generator circuit disclosed which consists of an on gang clock signal several output clock signals, each with un different phase positions. This multiphase Clock generator circuit includes for each output clock signal an in the form of a CMOS inverter circuit gang drivers, the output drivers over delay links are coupled together and via logic circuits get a certain input clock. The logic circuits ensure that the p- and n-channel field effect transistors of the CMOS inverter circuits are not simultaneously conductive can be switched to during the switching operations of the CMOS Inverter to prevent through currents and thus the current minimize consumption and noise. This well-known Mehrpha Sen clock generator circuit is capable of from one single input clock signal several different off  Generate gang clock signals, but on the one hand this Output clock signals always the same clock frequency, namely the Clock frequency of the input clock signal, and only under have different phases and on the other hand again the generation of the output clock signals by the circuit is fixed.

The present invention is therefore based on the object to provide clock divider circuitry which the generation of an output clock depending on one predefined input clock with a variable divider factor enables.

This object is achieved according to the present invention by ei ne clock divider circuit arrangement with the features of the An Proverb 1 solved. The subclaims each define be preferred and advantageous embodiments of the present Invention.

According to the invention, the clock divider circuit arrangement comprises egg ne counting device and a comparison device which the current counter reading of the counter with a freely selectable divider factor and compares this increment if the current meter reading does not match the predefined divider factor. On the other hand an output clock pulse generated by the comparison device and at the same time the counter reading by a reset device the counter is reset if the eyes visible counter reading corresponds to the divider factor.

A particularly small circuit arrangement with minimal space The need arises when the reset function direction at the same time perceived by the comparison device will, d. H. in this case the comparison device generates an output clock pulse and at the same time sets the counter reading the counting device to an initial counter reading, in particular  re to the value 1, if the current counter stood with the divisor factor.

The output clock pulse generated by the comparison device is preferably a bistable multivibrator, i.e. H. one Flip-flop circuit, supplied and from this for another Processing provided to ensure a spike-free finish to ensure gang clock signal.

The freely selectable divider factor with which the input clock by the clock divider circuit arrangement according to the invention can be divided in a freely programmable Re gister be stored so that within a correspond the integrated circuit, for example via a data bus different values written in the register and thus different output clocks can be generated.

A particularly advantageous application is Use of the present invention in a cell phone chip nes mobile radio transmitter, because in this case the frequency with which Data or communication information via a mobile radio channel can be transmitted by appropriate choice of the plate factor or the clock ratio between that of the clock divider circuit arrangement generated output clock and the predetermined input clock can be selected variably. On this way, only a cell phone chip has to be manufactured, with the appropriate programming of the divider factor in different mobile networks can be used.

The present invention generally enables the variable Generation of an output clock according to a freely selectable Divider factor. This can ensure, for example, that different parts of an integrated circuit each after software programming the divider factor with respect to the rest of the circuit with different clock ratio can work.

The invention is described below with reference to the attached drawing based on preferred embodiments nä ago explained.

Fig. 1 shows a simplified block diagram illustrating the basic structure of a clock divider circuit arrangement according to one embodiment of the invention,

Fig. 2 shows a circuit implementation of a clock divider circuit arrangement according to another embodiment of the present invention, and

Fig. 3 shows a possible circuitry structure egg nes shown in Fig. 2 accumulator.

First, the principle on which the invention is based will be explained with reference to FIG. 1.

The clock divider circuit arrangement shown in FIG. 1 comprises a comparator 3 and a counter 4 as essential elements. In addition, a register 2 is provided on the input side and a flip-flop 5 is provided on the output side.

Register 2 is freely programmable and can be programmed, for example, over a data bus 1 with a certain divider factor value X. This divider factor X represents the clock ratio between a predetermined high-frequency input clock f _T and the never derfrequency output clock f to be generated by the clock divider, ie f = f _T / X.

The counter 4 runs in accordance with the input clock f _T continuously from 1 to X. As soon as the counter status CNT = X has been reached, the counter 4 is reset to the counter status CNT = 1 and at the same time an output clock pulse f is generated and via the Flip flop 5 issued. Likewise, the counter 4 is reset if it has reached a certain maximum counter reading. For example, if the counter 4 (as shown in FIG. 2 and explained in more detail below) is equipped with five flip-flops for temporarily storing the current counter reading, the counter 4 can count to a maximum of 2 ⁵ -1 = 31, so that the counter 4 must be reset when this maximum possible counter reading is reached.

For this purpose, the comparator 3 continuously compares the current counter reading CNT of the counter 4 with the divisor factor X stored in the register 2. If the counter reading CNT has not yet reached the value X or the maximum possible counter reading, the comparator 3 performs the increment of the meter reading according to CNT = CNT +1. If, on the other hand, the value X or the maximum possible counter status has already been reached, the comparator 3 generates an output clock pulse f and at the same time the counter status of the counter 4 is reset to the initial value CNT = 1 and the process described above is repeated.

The procedure described above with regard to the functionality of the comparator 3 has the advantage that the comparison with the programmed divider factor value X is used twice, namely on the one hand to generate the low-frequency output clock f and on the other hand also to determine the last counter status CNT before the counter 4 must start again with the counter reading CNT = 1. However, this double use is not absolutely necessary. Rather, different circuit means can of course also be provided for carrying out two comparisons on different count values, but this would enlarge the circuit.

As has already been mentioned, an output clock pulse f is generated by the comparator 3 if the current counter reading of the counter 4 matches the programmed divider factor value X. This output clock pulse f has the length 1 / T if it is assumed that the counter 4 is operated at the clock rate f _T = 1 / T to be divided. The flip-flop 5 , which receives the output clock pulses of the comparator 3 , is operated with the input clock f _{T to be divided} . In this way it is achieved that the flip-flop 5 for X input clock pulses of length T outputs a single output clock pulse of length 2T, so that the clock ratio f: f _T = 1: X is realized. In particular, the flip-flop 5 ensures that the output clock signal f generated by the clock divider is spike-free, ie there are small and possibly disruptive output pulses which are generated as a result of intermediate states which occur when the flip-flops 4 present in the counter are not switched simultaneously can occur reliably prevented.

In Fig. 2 a possible circuit implementation of the clock divider circuit arrangement shown in Fig. 1 is Darge.

With the help of a divider factor input signal X_IN, for example, a specific divider factor value is written into register 1 via an 8 bit data bus. In addition, the register 2 is also controlled by additional control signals. A reset signal RESET supplied via a driver 6 (buffer) is used for initialization and for resetting the register 2 in an initial state. The entire circuit arrangement can be activated via a release signal SLAVE. Since several such clock divider circuit arrangements can be provided in egg ner integrated circuit, a selective enable signal is also provided, by means of which the clock divider circuit arrangements can be activated and released individually. The divider factor value stored in register 2 can be read out at any time via a clock divider output signal X_OUT and, for example, fed to a central (and not shown) microcontroller.

The function of the counter 4 shown in FIG. 1 is performed according to FIG. 2 by flip-flops 26-30 in combination with an accumulator 25 , in which the value 1 is constantly present at an input in order to be able to continuously increment the counter reading by 1 .

The function of the comparator 3 shown in FIG. 1 for comparing the current counter reading with the divider factor value stored in the register 2 is carried out by a logic circuit which connects the NAND gates 7 and 8 , XOR gate 9 , which are interconnected according to FIG. 2 -12 , NOR gates 14-17 and an NXOR gate 13 and an AND gate 18 . To reset the counter value of the counter 4 shown in FIG. 1 to the predefined initial value, a further logic circuit is provided, which according to FIG. 2 is connected and comprises logic gates coupled to each of the flip-flops 26-30 . In particular, the flip-flop 26 is an AND gate 19 on the input side, the flip-flop 27 is an AND gate 20 with an inverted input, the flip-flop 28 is an AND gate 21 with an inverted input, and the flip-flop 29 is an OR gate 22 with an upstream AND gate and with the flip-flop 30 an AND gate 24 with an inverted input and an upstream and the function of an inverter exercising NAND gate 23 coupled.

In Fig. 2, the starting flip-flop 5 already shown in Fig. 1 is shown. In the exemplary embodiment shown in FIG. 2, the output of this flip-flop 5 is also coupled to a further logic circuit which comprises NAND gates or inverters 31 and 32 , a NOR gate 33 and a multiplexer 34 . This logic circuit is used to bridge the previously explained counter and comparison logic when programming the divider factor values 0 or 1, so that not the divided output clock signal f, but the original input clock signal f _{T is} output. For this purpose, the individual bits of the divider factor value stored in the register 2 are evaluated by the NOR gate 33 and a control signal for the multiplexer 34 is generated as a function thereof. If the divider factor value 1 or 0 is stored in the register 2 , a control signal with the logic value '1' is generated by the NOR gate 33 , so that the multiplexer 34 selects the input clock f _{T present} at its '1' input and switches it on turns on its output. In any other case, however, a control signal with the logic value '0' is generated by the NOR gate 33 and the multiplexer 34 thus selects the divided clock signal supplied by the flip-flop 5 and connects it to the output. Of course, however, it is also conceivable to provide a clock division for the divisor values 0 and 1.

In Fig. 3, a possible realization of the accumulator 25 shown in Fig. 2 is also shown, which essentially comprises several half-adders 35-37 connected according to Fig. 3. In addition, a NAND gate 38 functioning as an inverter and an XOR gate 39 are provided. The individual half adders 35-37 and the XOR gate 39 , as shown in FIG. 3, become the individual bits A0. , , A4 of the current counter reading and the individual bits SUM0 on the output side. , , 4 of the totalized counter reading.

The previously described function of the counter 4 could also be implemented in the form of a correspondingly configured state machine (Finite State Machine, FSM), since the five flip-flops 26-30 shown in FIG. 2 can be understood not only as counting registers, but also for Description of a total of 2 ⁵ = 32 different states can be used. In this case, the divider factor value X stored in the register 2 would correspond to one of these 32 states, and starting from an initial state, the state machine would change to a next state with each clock pulse f _T until the state corresponding to the divider factor value X is reached.

The present invention can be used particularly advantageously in the field of mobile radio. Thus, the freely programmable and freely scalable clock divider according to the invention can be used in the high-frequency interface of mobile radio chips to determine the transmission frequency. In chips in accordance with the European DECT mobile radio standard (Digital European Cordless Telephone), for a corresponding input clock frequency f _T , the value X = 1 can be set, for example, as a division factor and thus the DECT protocol can be observed, while for the American mobile radio market with respect to Applicant newly developed WDCT (Worldwide Digital Cordless Telephone) mobile radio method the divider factor can be set to the value X = 2. For other standards, other clock ratios can easily be set according to the respective requirements without changing the hardware and the input clock f _T by programming the divider factor X accordingly.

Reference list

1

Data bus

2nd

register

3rd

Comparator

4

counter

5

Flip flop

6

driver

7

NAND gate

8th

NAND gate

9

XOR gate

10th

XOR gate

11

XOR gate

12th

XOR gate

13

XNOR gate

14

NOR gate

15

NOR gate

16

NOR gate

17th

NOR gate

18th

AND gate

19th

AND gate

20th

AND gate

21

AND gate

22

OR gate

23

NAND gate (inverter)

24th

AND gate

25th

accumulator

26

Flip flop

27

Flip flop

28

Flip flop

29

Flip flop

30th

Flip flop

31

NAND gate (inverter)

32

NAND gate (inverter)

33

NOR gate

34

multiplexer

35

Half adder

36

Half adder

37

Half adder

38

NAND gate (inverter)

39

XOR gate
f _T

Switching cycle
f divided clock
X divisor factor
X_IN divider factor input signal
X_OUT divider factor output signal
RESET reset signal
SEL Selective enable signal
SLAVE enable signal
A input bit of the accumulator
SUM output bit of the accumulator

Claims (12)

1. clock divider circuit arrangement which receives an input clock signal of a specific frequency (f _T ) and divides it according to a specific divider factor (X) and provides it as an output clock signal (f), characterized by

• a counting device ( 4 ) to which the input clock signal (f _T ) is applied,
• - A comparison device ( 3 ) for comparing the counter status (CNT) of the counting device ( 4 ) with the determined part (X) and for controlling the counting device ( 4 ) in such a way that their counter reading (CNT) according to the input clock signal (f _T ) is incremented if the current counter reading (CNT) does not match the stored divider factor (X) and that an output clock pulse (f) is generated if the current counter reading (CNT) matches the divider factor (X), and
• - A reset device ( 19-24 ) for resetting the count (CNT) of the counting device ( 4 ) if the current count (CNT) of the counting device ( 4 ) matches the divider factor (X).

2. clock divider circuit arrangement according to claim 1, characterized in that with the comparison device ( 3 ) storage means ( 2 ) for storing the determined divider factor (X) are connected. 3. clock divider circuit arrangement according to claim 2, characterized in that the memory means ( 2 ) are freely programmable with the divider factor (X) per. 4. clock divider circuit arrangement according to one of the preceding claims, characterized in that the reset device ( 19-24 ) and the counting device ( 4 ) are designed such that the counter reading (CNT) of the counting device ( 4 ) is reset to the value 1 , if the current counter reading (CNT) matches the divisor factor (X). 5. clock divider circuit arrangement according to one of the preceding claims, characterized in that the comparison device ( 3 ) and the counting device ( 4 ) are designed such that the counter reading (CNT) of the counting device is incremented by the value 1 if the au current meter reading (CNT) does not match the stored divisor factor (X). 6. clock divider circuit arrangement according to claim 4 and 5, characterized in
that the reset device ( 19-24 ) and the counter device ( 4 ) are designed such that the counter reading (CNT) of the counter device ( 4 ) is reset to the value 1 if the current counter reading (CNT) matches a maximum counter reading, and
that the comparison device ( 3 ) and the counting device ( 4 ) are designed such that the counter reading (CNT) of the counting device is incremented by the value 1 if the current meter reading (CNT) is not with the stored divider factor (X) or maximum counter reading matches. 7. clock divider circuit arrangement according to one of the preceding claims, characterized in that with the comparison device ( 3 ) a bistable Kippstu fenschaltung ( 5 ) is connected, the input of which is supplied from the output clock pulse (f). 8. clock divider circuit arrangement according to claim 7, characterized in that to the bistable flip-flop circuit ( 5 ), the input clock signal (f _T ) is applied, so that the bistable flip-flop circuit ( 5 ) is operated according to the input clock signal (f _T ). 9. clock divider circuit arrangement according to claim 7 or 8, characterized in
that the output of the bistable multivibrator circuit ( 5 ) is connected to an input of a selection logic circuit ( 31-34 ) which receives the determined divider factor (X) at another input,
the selection logic circuit ( 31-34 ) being designed in such a way that it suppresses the output of the output clock signal (f) of the bi-stable flip-flop circuit ( 5 ) if the part detector (X) corresponds to the value 0 or 1. 10. clock divider circuit arrangement according to claim 9, characterized in
that the selection logic circuit ( 31-34 ) comprises a multiplexer which receives the output clock signal (f) of the bi-stable flip-flop circuit ( 5 ) at one input and the input clock signal (f _T ) at another input, and
that the selection logic circuit ( 31-34 ) comprises a logic circuit ( 33 ), the logic circuit ( 33 ) evaluating the individual bits of the determined divider factor (X) and, depending on this, a control signal for the multiplexer ( 34 ) for connecting either the one input of the multiplexer ( 34 ) at the output clock signal (f) or the input clock signal (f _T ) at the other input of the multiplexer ( 34 ). 11. clock divider circuit arrangement according to one of the preceding claims, characterized in that the reset device ( 19-24 ) is integrated in the comparison device ( 3 ). 12. Use of a clock divider circuit arrangement according to egg nem of the preceding claims in a mobile radio system, characterized, that the transmission fre sequence for the transmission of communication information via a mobile radio channel of the mobile radio system is set.