DE19910113C1 - Charge pump for electrical phase-locked loop (PLL) - Google Patents

Abstract

A charge pump circuit for stable latching in of a PLL requires a zero net charge transfer from the charge pump (CP) into the low-pass loop filter (LF) during a reference cycle, in order to set a stable control voltage (V tune) for the voltage controlled oscillator (VCO). The charge pump discharge transistor (N disch) in the source- branch based on four PMOS-transistors, is now arranged with its drain-terminal in the current path-circuit nodes (B) between the two output transistors (MP1,MP2) and with its source-terminal in the current path circuit-nodes (A) between the two output transistors (MN1,MN2). The two discharge transistors (Ndisch,Pdisch) are now operated as a transfer gate, with both circuit nodes (A,B) mutually discharged, and not discharged to the (VSS) and (VDD) potentials of the supply voltage.

Description

The invention relates to a charge pump circuit (Charge Pump) according to the preamble of claim 1.

Phase locked loops, also known as PLL (Phased Locked Loop) can be used with the help of egg ner highly accurate reference frequency another highly accurate and generate stable frequency by the reference frequency can deviate. In digital phase locked loops, ge usually after the phase or phase-frequency de tector used a charge pump circuit.

The function of such a circuit is explained below with reference to FIG. 1, in which a block diagram of a digital phase locked loop is shown.

With the embodiment shown in FIG. 1, the digital phase-locked loop is designed with support from a highly accurate reference frequency F _ref, a highly accurate and stable frequency F _VCO generated that not equal to the reference frequency F _ref may be, wherein the generated frequency F _VCO is an integer multiple of the Refe rence frequency F _ref represents. A frequency F _Q that can be obtained from a quartz-stabilized oscillator Q is divided down with a reference divider R down to the required reference frequency F _ref . At the same time, the output frequency F _{VCO of} a voltage controlled oscillator (Voltage Controlled Oscilla tor) VCO is divided down into a further frequency divider N.

The two alternating currents divided with respect to their frequencies or their relative phase positions are compared with one another in a so-called phase (frequency) detector PD. The phase detector PD generates two pulse-width-modulated pulse trains UP and DOWN at its output, which are in a fixed relationship to the phase difference of the two alternating currents at its two inputs. If the divided frequency F _VCO / N is too high compared to the reference frequency F _ref , or if the phase of the alternating current with the frequency F _VCO / N leads that of the alternating current with the frequency F _ref , the phase detector PD becomes its for the pulse train DOWN responsible output longer compared to its output responsible for the pulse sequence UP. The reverse applies to correspondingly different phase positions.

With exactly the same phase position of the two input changes currents at the phase detector PD are its two outputs for switched on for a short time of exactly the same length. This before gang is known as an anti-backlash pulse (ABL). The one Adding such an anti-backlash pulse is from dynami view more favorable than neither of the two exits of the Phase detector PD to turn on because of very small phases deviations due to the inertia of the circuits otherwise under Under certain circumstances, no defined current pulses can be delivered and there could be dead times in the regulation.

The pulse sequences UP and DOWN control a charge pump CP, a low-pass loop filter LF is connected to its output which acts as an integrator of the charge pump current and generates a control voltage V_tune. An impulse on the Pulse train UP transmitting line causes the charge pump CP into it a current of a defined strength into the Low pass loop filter LF to "source", so that the Control voltage V_tune at the output of the low-pass loop filter LF by the amount of charge transported in this filter LF increases over the duration of the pulse. An impulse on the The pulse train DOWN transmitting line draws a current the loop filter LF out ("sink"), so that the tax voltage V_tune tends to last for the duration of the pulse falls. The mean voltage at the loop filter LF is thus for currents of the same size solely from the relative  Duration of the pulses of the pulse sequences UP and DOWN to each other Right.

With exactly the same phases of the input AC currents divided with respect to their frequency at the phase detector PD, i.e. when the anti-backlash pulse occurs, the control voltage V_tune ideally does not change at the output of the loop filter LF, since the net current into the loop filter LF is then zero and also none Net charge quantity is transported in or from the loop filter LF. The resulting on the loop filter LF output voltage V_tune now serves as a control voltage for the voltage controlled oscillator VCO, whose frequency F _VCO or phase is thus coupled to the phase of the crystal-stabilized oscillator Q by the phase control loop.

By changing the ratio to be set in the frequency divider N, the frequency F _{VCO of} the voltage-controlled oscillator VCO can be set within wide ranges. However, the control voltage V_tune of the voltage-controlled oscillator VCO must also be able to vary widely in order to be able to keep the voltage-controlled oscillator VCO at the desired frequency.

The usable voltage range of the control voltage V_tune should ideally approach the zero potential and the supply voltage. This is particularly important in portable applications, since there the supply clamping voltages are in the 3 V range and tend to go in the direction of 2, 7 V.

It is for the stable locking of a phase locked loop mandatory that during a reference cycle the from the charge pump CP to the low-pass loop filter LF transported net load is zero, because only then in the Means a stable control voltage V_tune for the voltage controlled oscillator VCO can adjust.  

Due to the always existing non-idealities in the circuit arrangement of the charge pump CP, the transient course of the current flow into the loop filter LF will nevertheless deviate from the ideal zero line even when the phase-locked loop is engaged. The control voltage V_tune of the voltage-controlled oscillator VCO is consequently superimposed on a frequency spectrum with a fundamental frequency and multiples thereof corresponding to the reference frequency F _ref , which frequency-modulates the voltage-controlled oscillator VCO and therefore in the form of spurious peaks in the spectrum of the voltage-controlled oscillator VCO both sides of the carrier frequency F _VCO can be seen.

Fig. 2, such a frequency spectrum P [dBm] = f (F) shows an example of the voltage controlled oscillator VCO, the _VCO center frequency F 1.628 GHz and the reference frequency F _ref is 200 kHz. With 1 , 2 and 3 in Fig. 2, the most three spurious peaks besides the center frequency F _VCO on the one side of the spectrum (P [dBm] = absolute level, F = frequency).

DE 42 16 712 A1 discloses a current source circuit wrote that as the output stage of a phase detector Phase locked loop is used. The power source circuit contains a source branch with four PMOS transistors and one Sink branch with four NMOS transistors. In each of the branches two of the transistors are connected in series and form the output path connected to the output connector. The transistor on the output terminal side forms a current mirror with another transistor, in which a reference current is fed into. The supply chip transistor on the voltage pole side of the output branch is supplied by a Switching signal activated. With the one in the input branch of the stream mirrored transistor is another transistor in Series connected, with the other the supplier voltage voltage poles is connected.  

In EP 0 627 820 A2 there is a similar current source scarf tion in a charge pump for a phase locked loop shows. It contains min. For each of the source and sink branches at least four transistors. The respective in the entrance path of the Current mirror ge with the current mirror transistor in series switched further transistor is from an enable signal switched.

Fig. 3 shows a compared to that shown in DE 42 16 712 A1 slightly modified charge pump circuit in CMOS technology, which is to be used in various integrated PLL circuit devices.

The source branch consisting of four PMOS transistors MP1, MP2, MP3 and MP4 represents a switched current mirror which multiplies a reference current I _refSOURCE with a specific mirror ratio from the voltage supply VDD into an output connection CP _out via the upper one in FIG. 2 Route marked in bold conducts as soon as a control signal applied to a control input UPN has a logical LOW potential. The inverted pulse sequence UP from the first output of the phase detector PD shown in FIG. 1 is applied to the control input UPN. The current multiplication factor specifying the mirror ratio is 12 in the example shown in FIG. 2.

A corresponding function for the sink branch of the charge pump circuit shown in Fig. 2 have four NMOS transistors MN1, MN2, MN3 and MN4, which ensure that during a logical HIGH potential of the pulse sequence to be fed to the control input DOWN the with the Mirror _ratio (here also 12) multiplied current I _refSINK from the output connection CP _out via the lower path shown in bold in FIG. 2 is directed towards ground VSS. At the control input DOWN, the pulse sequence DOWN is applied from the second output of the phase detector PD shown in FIG. 1.

In the charge pump circuit according to FIG. 3, transistors C_SOURCE and C_SINK also provided in CMOS technology serve to accelerate the switch-on process of the source or sink pump branch due to their capacitance function. The anti-backlash pulse can therefore be kept short (∼ 2.. .6 ns), whereby with locked phase locked loop no minell only effects on the control voltage V_tune can arise during this time, since only then the power sources are switched on.

In real circuit arrangements, however, there are sub differ on this ideal behavior. To do this, the cargo distributions in the output stage during the ABL pulse and be considered after its decay. For simplification In the following only the conditions for the sink branch the charge pump. The processes in the source Branch must be viewed accordingly, but on the supplier voltage potential VDD related.

During the anti-backlash pulse, the NMOS transistor MN2 is switched on, pulls a circuit node A between the NMOS transistors MN1 and MN2 to a low potential of ∼ 0 V and thus enables a sinking current through the NMOS transistor MN1 absolute size is set by the bias _potential on line I _refSINK . At the end of the anti-backlash pulse, the switching node A is again disconnected from the voltage potential VSS (= ground).

The node A would now charge itself via the output transistor MN1 and thus draw a current from the loop filter LF connected to the output CP _out (shown in FIG. 1) until the potential difference between the nodes I _refSINK and A to the _{threshold voltage} V _TN has subsided from MN1. At very low reference frequencies, node A would even charge up to the voltage at CP _out , since MN1 can conduct a finite current even in the subthreshold range. The output transistor MN1 then blocks, apart from the subthreshold range, and stops the discharge process of the loop filter LF.

Since the transistors MN1 and MN2 have a very large width can have is the parasitic capacitance at the circuit knot A very large and this process can take a relatively long time last for. This effect also occurs in the source branch of the Charge pump on between the two PMOS transistors MP1 and MP2 lie on circuit node B. Even by one nominal matching of parasitic capacitances at node A and B the effects are not for all possible Compensate the operating states of the charge pump with each other. In addition, these are not in most CMOS processors subject to correlated technological fluctuations.

So in every reference cycle after the anti-backlash Pulse net a certain amount of charge in the loop filter LF implemented. This must go through the phase locked loop Warping of the anti-backlash pulse, d. H. by extending compensate for either the source or sink duration. This creates a total of transients in the control chip V_tune, which acts as a spurious peak in the  Frequency spectrum of the output signal of the voltage controlled VCO oscillators can be seen.

To avoid this effect, it is known to provide additional discharge transistors N_DISCH and P_DISCH in the manner shown in FIG. 3 in the charge pump circuits. In the sink branch of the charge pump, the discharge transistor P_DISCH is a PMOS transistor and in the source branch the discharge transistor N_DISCH is an NMOS transistor. In the case of the sink branch, when the sink is not active, ie when the transistor MN2 is in the non-conducting state, the circuit node A is quickly charged to the supply voltage potential VDD.

This also becomes the gate-source voltage of the output transistor MN1 quickly negative, causing this transistor then also blocks very quickly and only for very short ones Time after the anti-backlash pulse a fault current from the Loop filter LF pulls. This results in the middle Voltage range of the control voltage V_tune a considerable Reduction of the spurious peaks.

In the charge pump circuit shown in FIG. 3, the discharge transistors N_DISCH and P_DISCH, however, have a negative effect on the usable voltage range of the control voltage V_tune at CP _out . The explanation describing the occurrence of this disadvantage is given below as representative of the sink branch of the charge pump:

If the control voltage V_tune is at such a low potential that the output node of the charge pump is lower than the gate bias _potential V _refSINK by approximately the threshold voltage V _{TN of} the NMOS transistor MN1 used, its drain and source connections exchange the role and the output transistor MN1 begins to conduct in the opposite direction. Since the discharge transistor P_DISGH also conducts between the anti-backlash pulses, a continuous current can flow into the loop filter LF during this time. The sink branch of the charge pump then acts as a source.

The charge pump must compensate for this amount of charge again during the anti-backlash pulse. This may even be impossible and the phase locked loop no longer remains in the lock state. In any case, an alternating component is superimposed on the control voltage V_tune in the outer regions, which causes the secondary wave peaks (side lines) to increase considerably at integral intervals between the reference frequency F _{ref and} the carrier frequency F _{VCO of} the voltage-controlled oscillator VCO.

Since the output transistors generally have very large gate widths, this effect does not only occur when the control voltage V_tune has dropped to the voltage _value V _refSINK -V _TN , but also earlier if the subthreshold effect already has significant effects. For this reason, the usable range of the control voltage V_tune is limited to voltages that are only up to about 0.7 V to the supply voltages when charge pumps are used. At provided low supply voltages, z. B. 2.7 V, then the tuning range for the voltage controlled oscillator VCO is too small.

The object of the invention is to provide a charge pump circuit for a digital phase locked loop with simple means like that train that equally the problems of slow Ab switch, the disturbing spurious peaks in frequency spectrum of the voltage controlled oscillator leads, and the unacceptable reduction in the tuning range of this Oscillator can be solved.

This task is carried out in a generic charge pump circuit by the in the characterizing part of the patent solved 1 specified characteristics.  

According to claims 2 and 3, the activation and the interconnection of the discharge transistors can advantageously be carried out in two different ways. Here, the discharge transistors themselves ( Fig. 4) are connected in a CMOS transfer gate structure between nodes A and B.

According to the first variant, the gate connection of the im Source branch of the charge pump lying discharge transistor immediately from the inverted first pulse sequence UPN of the Phase detector and the gate connection of the in the sink branch of the Discharge transistor lying directly from the charge pump second pulse sequence DOWN of the phase detector. The Discharge transistors are therefore complementary because of respective combination of NMOS and PMOS transistor to the Sink or source branches of the charge pump switched on.

According to the second variant, the gate connection of the discharge transistor located in the source branch of the charge pump and the gate connection of the lie in the sink branch of the charge pump ing discharge transistor both from the first inverted pulse sequence UPN as well as from the second Pulse train DOWN of the phase detector via a common one combinatorial logic circuit driven from the State of the two pulse trains the inactive state of the Charge pump recognizes and upon detection of this condition the Discharge transistors by appropriate control of the gate Connections of the two discharge transistors at the same time switches on. The discharge transistors are thus at this Variant switched on as soon as both the sink and the source branch of the charge pump also becomes inactive.

Since the circuit nodes in the current path between the two output transistors of the source and sink branches during the active pumping time, for. B. during the anti-backlash pulse, almost at the upper or lower supply voltage potential, for the first time, after the charge pump parts according to the first variant or the entire charge pump is switched off according to the second variant, almost the same relationships as in the proposed arrangement of the discharge transistors described with reference to FIG. 3.

This means that the output transistors are switched off very quickly by very quickly pulling away their respective source potentials, which discharge the nodes A and B against one another, so that an average voltage is established on them. At the edge regions of the control voltage of the voltage-controlled oscillator, the same thing as in the proposed circuit described with reference to FIG. 3 now occurs. This means that the source branch draws charge from the loop filter or the sink branch pumps charge into the loop filter.

The difference of the charge pump circuit according to the invention and their advantage is that when inactive Charge pump even in the peripheral areas of the control voltage V_tune of the voltage controlled oscillator no continuous current can flow into the loop filter, but only overall the amount of charge that after the active state of the Charge pump parts or the entire charge pump in the parasitic capacitances of the circuit nodes mentioned in the Current path between the two output transistors of the source or sink branch is stored. This finite Total charge of the fault can be the charge pump by pulling the Compensate anti-backlash impulse again, so that Always keep the locked phase locked loop can.

Further advantageous and expedient further developments of the Er invention are given in claims 4 to 9.

As an alternative, there is in principle the possibility of _reducing the bias _potential of the reference _current I _refSINK for the sink branch and _increasing the bias _potential of the reference _current I _refSOURCE for the source branch to _{solve the problem} . However, this results in a further increase in the output transistors at the same nominal output current, which firstly also increases the parasitic effects and secondly the area required for the pump and the like. U. the circuits for their control is additionally increased.

In principle, this would also reduce the fault current nern that the discharge transistors are designed very weak the so that the fault current through this and no longer through the output transistors is determined. However, meet the discharge transistors then also serve their actual purpose the quick shutdown in the middle of the tax voltage of the voltage controlled oscillator no longer so effectively.

The invention is explained with reference to drawings. It shows gene:

Fig. 1 shows the block diagram already described a übli chen digital phase locked loop (PLL),

Fig. 2, the example also already described spec- trum of a Fre that occurs at the output of the voltage controlled Os zillators known digital phase locked loops,

Fig. 3 shows the circuit of a proposed and already be signed charge pump,

Fig. 4 shows the circuit of a charge pump according to the invention, and

Fig. 5 is a combinational logic circuit for implementing the second embodiment of a charge pump circuit according to the invention.

The charge pump circuit shown in FIG. 4 largely corresponds to the charge pump circuit already described in detail, which is shown in FIG. 3. In order to avoid repetitions, only the differences are dealt with in the following. The discharge transistor N_DISCH located in the source branch of the charge pump is with its drain connection on the current path switching node B between the two PMOS output transistors MP1 and MP2 of the source branch and with its source connection on the current path circuit node A between the two NMOS - Arranged from output transistors MN1 and MN2 of the sink branch.

The discharge transistor located in the sink branch of the charge pump P_DISCH is with its drain connection on the current path scarf tion node A between the two output transistors MN1 and MN2 of the sink branch and with its source connection on Current path circuit node B between the two output trains sistors MP1 and MP2 of the source branch arranged. The bulk of the NMOS discharge transistor N_DISCH is at the drain connection this transistor and the bulk of the PMOS discharge transistor P_DISCH connected to the source of this transistor sen.

The bulk of the discharge transistors N_DISCH and P_DISCH can as a variant also on the potential VSS (N_DISCH) and VDD (P_DISCH) are connected, which however results in a somewhat reduced effectiveness of the charge pump circuit results. The two discharge transistors N_DISCH and P_DISCH act as a transfer gate in this circuit and discharge the two circuit nodes A and B no longer against the pots tial VSS or VDD of the supply voltage, but against each other at the. To control the two discharge transistors N_DISCH and P_DISCH are for driving their gate electrodes Control lines to externally controllable gate connections N_DISCH_EN and P_DISCH_EN provided.  

The control of the discharge transistors N_DISCH and P_DISCH can be done in two different ways.

In the first variant, the externally accessible gate Connection P_DISCH_EN with the input DOWN for the second Im pulse sequence and the externally accessible gate connection Verify N_DISCH_EN with input UPN for the first pulse train bound. The discharge transistors N_DISCH and P_DISCH become in this variant, therefore, complementary (because of each Combination of NMOS and PMOS) to the sink or source two switched on.

In the second variant, the discharge transistors N_DISCH and P_DISCH switched on together as soon as both the sink and source branches of the charge pump are inactive become. A combinatorial logic circuit can be used for this insert from the state at the inputs DOWN and UPN for the pulse sequences coming from the phase detector the inacti recognizes the state of the charge pump and then the discharge transistors by appropriate control of the outside accessible gate connections N_DISCH_EN and P_DISCH_EN switches on at the same time.

An exemplary embodiment of such a combinatorial logic circuit is shown in detail in FIG. 5. This combinatorial logic circuit has a NAND gate 1 , to which the first pulse sequence from the input UPN is fed at its one input and the second pulse sequence from the input DOWN via an inverter 2 and at its output the gate connection N_DISCH_EN for the Discharge transistor N_DISCH are connected via an inverter 3 and at the same time the gate connection P_DISCH_EN for the discharge transistor P_DISCH is connected via two inverters 4 and 5 located in series.

The nodes A and B are during the active charge pumping time, for example during the anti-backlash pulse, practically at the potential VSS or VDD, so that for the first time after switching off the charge pump parts (first variant) or the whole Charge pump (second variant) almost the same conditions as in the charge pump circuit shown in FIG. 3. This means that the output transistors MP1 and MN1 are switched off very quickly by pulling away their respective source potentials very quickly.

3 occurs at the edge regions of the control voltage V_tune, as in the case of the charge pump circuit according to FIG. 3, ie the source branch of the charge pump draws charge from the loop filter LF or the sink branch pumps charge into the loop filter LF. In contrast to the charge pump circuit according to FIG. 3, no continuous current advantageously flows into the loop filter LF when the charge pump is inactive, even in the edge regions of the control voltage V_tune, but rather only the amount of charge which, according to the active state of the charge pump or the pump parts, flows into the parasitic capacitances of the circuit nodes A and B is stored.

The charge pump balances this finite total fault charge by distorting the anti-backlash pulse so that the phase locked loop always remains in the lock state. Thus, with the arrangement indicated by the invention of the discharge transistors N_DISCH and P_DISCH in one Phase locked loop provided charge pump circuit that Problem of slow shutdown and unacceptable Reduction of the tuning range of the voltage controlled Oscillators equally eliminated.  

Reference list

A circuit node
B circuit node
CP Charge Pump
CP _out

Charge pump output
C_SINK NMOS transistor, effective as boost capacity
C_SOURCE PMOS transistor, effective as boost capacity
DOWN Second pulse train, control input
F frequency in the spectrum
F _Q

Quartz stabilized frequency
F _ref

Reference frequency
F _VCO

VCO output frequency
F _VCO

/ N Frequency F _VCO divided by N

I _refSINK

Sink reference current
I _refSOURCE

Source reference current
LF low-pass loop filter
MN1. . . MN4 NMOS transistors
MP1. . . MP4 PMOS transistors
N frequency divider
N_DISCH NMOS discharge transistor
N_DISCH_EN gate connection of the NMOS discharge transistor
Q Quartz stabilized oscillator
P [dBm] absolute level in dBm
PD phase (frequency) detector
P_DISCH PMOS transistor
P_DISCH_EN Gate connection of the PMOS discharge transistor
R reference divider
UP First pulse train
UPN control input for inverted pulse sequence UP
VSS voltage potential (ground)
VCO voltage controlled oscillator (VCO)
VDD supply voltage
V_tune control voltage

1

NAND gate

2nd

b to

5

Inverter

Claims (9)

1. Charge pump circuit (Charge Pump), which is connected in a elec tric phase locked loop (PLL) a two alternating currents with respect to their mutual phase position comparing phase detector, the two pulse width modulated at two outputs, with respect to their pulse widths in a fixed relationship to the phase difference of the two alternating currents to be compared generated and with the same phase position of the two alternating currents to be compared turns on both outputs for a short time to generate an anti-backlash pulse, and the low-pass loop filter acting as an integrator is connected upstream, the output voltage of which Control voltage for setting the frequency of a subsequent voltage-controlled oscillator (VCO; Voltage Controlled Oscillator) is used, with two switchable, CMOS-technology current sources, of which the first (source) depending on the first pulse train (UPN) d the second (sink) in dependence on the second pulse sequence (DOWN) delivers a current of defined strength to the low-pass loop filter or carries it away, the source branch having four PMOS transistors that have a switchable, a source reference current represent a current mirror multiplying current mirror, and contains at its gate on the part of the first pulse train (UPN) driven NMOS discharge transistor and the sink branch with four NMOS transistors, which multiply a switchable, sink reference current by a current mirror factor represent decorative current mirror, and is provided with a PMOS discharge transistor driven at its gate by the second pulse train (DOWN), characterized in that the discharge transistor lying in the source branch of the charge pump (N_DISCH) has its drain connection on the current path -Circuit node (B) between the two output transistors (MP1, MP2) from the source branch and with its Sourc e-connection is arranged on the current path switching node (A) between the two output transistors (MN1, MN2) of the sink branch and that the discharge transistor (P_DISCH) located in the sink branch of the charge pump with its drain connection on the current path switching node ( A) is arranged between the two output transistors (MN1, MN2) of the sink branch and with its source connection at the current path switching node (B) between the two output transistors (MP1, MP2) of the source branch, so that the two discharge transistors are operated as a transfer gate and the two circuit nodes (A, B) are not discharged against the potentials (VSS, VDD) of the supply voltage, but against one another. 2. Charge pump circuit according to claim 1, characterized ge indicates that the gate connection (N_DISCH_EN) of the im Source branch of the charge pump lying discharge transistor (N_DISCH) immediately from the inverted first pulse train (UPN) of the phase detector (PD) and the gate connection (P_DISCH_EN) of the lying in the sink branch of the charge pump Discharge transistor (P_DISCH) immediately from the second Pulse train (DOWN) of the phase detector (PD) is activated. 3. Charge pump circuit according to claim 1, characterized in that the gate connection (N_DISCH_EN) of the discharge transistor located in the source branch of the charge pump (N_DISCH) and the gate connection (P_DISCH_EN) of the discharge transistor located in the sink branch of the charge pump (P_DISCH ) can be controlled by both the first inverted pulse train (UPN) and the second pulse train (DOWN) of the phase detector (PD) via a common combinatorial logic circuit ( Fig. 5), which from the state of the two pulse trains (UPN, DOWN) recognizes the inactive state of the charge pump and, upon detection of this state, switches on the discharge transistors (N_DISCH, P_DISCH) by correspondingly controlling the gate connections (N_DISCH_EN, P_DISCH_EN) of the two discharge transistors simultaneously. 4. Charge pump circuit according to claim 3, characterized in that the combinatorial logic circuit ( Fig. 5) has a NAND gate ( 1 ), which has the first pulse train (UPN) at its one input and at its second input via an inverter ( 2nd ) the second pulse sequence (DOWN) is fed and at its output the gate connection (N_DISCH_EN) of the discharge transistor (N_DISCH) located in the source branch via an inverter ( 3 ) and at the same time the gate connection (P_DISCH_EN) of the sink Branch discharge transistors (P_DISCH) are connected via two inverters ( 4 , 5 ) or connected directly. 5. Charge pump circuit according to one of the preceding An sayings, characterized in that the bulk of the NMOS discharge transistor (N_DISCH) to the drain terminal ses transistor and the bulk of the PMOS discharge transistor (P_DISCH) to the source of this transistor is closed. 6. Charge pump circuit according to one of claims 1 to 4, characterized in that the bulk of the NMOS Ent charging transistor (N_DISCH) to ground potential (VSS) and the Bulk of the PMOS discharge transistor (P_DISCH) to the utility voltage potential (VDD) is connected. 7. Charge pump circuit according to one of the preceding An sayings, characterized in that in the source Branch of the charge pump one through one at drain and source interconnected PMOS transistor (C_SOURCE) realized Boost capacity and one in the source branch of the charge pump by an NMOS- connected at drain and source Transistor (C_SINK) realized boost capacity for acceleration Inclination of the switch-on operations are provided that the Boost capacitance in the PMOS transistor forming the source branch (C_SOURCE) with its gate connection at the gate connection of the PMOS output transistor (MP1) of the charge pump (CP) is and its interconnected drain and source on conclude from the source branch of the phase detector (PD) supplied inverted pulse train (UPN) is driven,  that the NMOS train forming the boost capacity in the sink branch sistor (C_SINK) with its gate connection at the gate connection of the NMOS output transistor (MN1) of the charge pump is on and on its interconnected drain and source connections from the pulse train supplied to the sink branch by the phase detector (DOWN) is controlled and that the length and width of the Boost capacitance in the PMOS transistor forming the source branch (C_SOURCE) and the length and width of the boost capacity in the Sink branch forming NMOS transistor (C_SINK) each the same length and half width of the corresponding PMOS or NMOS output transistor (MP1 or MN1) of the charge pump is set. 8. Charge pump circuit according to claim 7, characterized ge indicates that the width of the boost capacity in the Source branch forming PMOS transistor (C_SOURCE) and / or the width of the one that forms the boost capacity in the sink branch NMOS transistor (C_SINK) to achieve an optimal sym metry of the parasitic effect of the corresponding output transistor (MP1 or MN1) of the charge pump (CP) adapted become. 9. Charge pump circuit according to one of the preceding An sayings, characterized by an implementation in an integrated CMOS device.