DE19882975T1 - Zugreifen auf eine Nachrichtenaustauscheinheit von einem sekundären Bus aus - Google Patents

Zugreifen auf eine Nachrichtenaustauscheinheit von einem sekundären Bus aus

Info

Publication number
DE19882975T1
DE19882975T1 DE19882975T DE19882975T DE19882975T1 DE 19882975 T1 DE19882975 T1 DE 19882975T1 DE 19882975 T DE19882975 T DE 19882975T DE 19882975 T DE19882975 T DE 19882975T DE 19882975 T1 DE19882975 T1 DE 19882975T1
Authority
DE
Germany
Prior art keywords
access
messaging device
secondary bus
bus
messaging
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19882975T
Other languages
English (en)
Other versions
DE19882975B4 (de
Inventor
Byron R Gillespie
Barry R Davis
William T Futral
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19882975T1 publication Critical patent/DE19882975T1/de
Application granted granted Critical
Publication of DE19882975B4 publication Critical patent/DE19882975B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/404—Coupling between buses using bus bridges with address mapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
DE19882975T 1998-02-13 1998-12-30 Zugreifen auf eine Nachrichtenaustauscheinheit von einem sekundären Bus aus Expired - Fee Related DE19882975B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/023,494 1998-02-13
US09/023,494 US7007126B2 (en) 1998-02-13 1998-02-13 Accessing a primary bus messaging unit from a secondary bus through a PCI bridge
PCT/US1998/027832 WO1999041671A1 (en) 1998-02-13 1998-12-30 Accessing a messaging unit from a secondary bus

Publications (2)

Publication Number Publication Date
DE19882975T1 true DE19882975T1 (de) 2001-09-27
DE19882975B4 DE19882975B4 (de) 2005-08-18

Family

ID=21815423

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19882975T Expired - Fee Related DE19882975B4 (de) 1998-02-13 1998-12-30 Zugreifen auf eine Nachrichtenaustauscheinheit von einem sekundären Bus aus

Country Status (6)

Country Link
US (1) US7007126B2 (de)
JP (1) JP2002503847A (de)
KR (1) KR100347076B1 (de)
AU (1) AU1949799A (de)
DE (1) DE19882975B4 (de)
WO (1) WO1999041671A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6457068B1 (en) * 1999-08-30 2002-09-24 Intel Corporation Graphics address relocation table (GART) stored entirely in a local memory of an expansion bridge for address translation
DE10119472A1 (de) * 2001-04-20 2002-10-31 Harman Becker Automotive Sys Schnittstelle für die Datenübertragung zwischen zwei Bussystemen und Betriebsverfahren dafür
US6976115B2 (en) * 2002-03-28 2005-12-13 Intel Corporation Peer-to-peer bus segment bridging
US7003615B2 (en) * 2002-04-22 2006-02-21 Broadcom Corporation Tracking a non-posted writes in a system using a storage location to store a write response indicator when the non-posted write has reached a target device
US20030212735A1 (en) * 2002-05-13 2003-11-13 Nvidia Corporation Method and apparatus for providing an integrated network of processors
TWI261120B (en) * 2002-07-18 2006-09-01 Konica Corp Image pickup lens, image pickup unit and portable terminal
US6928476B2 (en) * 2002-08-23 2005-08-09 Mirra, Inc. Peer to peer remote data storage and collaboration
US7397797B2 (en) * 2002-12-13 2008-07-08 Nvidia Corporation Method and apparatus for performing network processing functions
US7913294B1 (en) 2003-06-24 2011-03-22 Nvidia Corporation Network protocol processing for filtering packets
US20060026171A1 (en) * 2004-07-30 2006-02-02 Mirra, Inc. Content distribution and synchronization
US7260663B2 (en) * 2005-04-07 2007-08-21 International Business Machines Corporation System and method for presenting interrupts
US8719547B2 (en) * 2009-09-18 2014-05-06 Intel Corporation Providing hardware support for shared virtual memory between local and remote physical memory
US8549202B2 (en) 2010-08-04 2013-10-01 International Business Machines Corporation Interrupt source controller with scalable state structures
US20120036302A1 (en) 2010-08-04 2012-02-09 International Business Machines Corporation Determination of one or more partitionable endpoints affected by an i/o message
US8495271B2 (en) * 2010-08-04 2013-07-23 International Business Machines Corporation Injection of I/O messages
US9336029B2 (en) 2010-08-04 2016-05-10 International Business Machines Corporation Determination via an indexed structure of one or more partitionable endpoints affected by an I/O message
US10671460B2 (en) * 2018-02-05 2020-06-02 Micron Technology, Inc. Memory access communications through message passing interface implemented in memory systems

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5619728A (en) 1994-10-20 1997-04-08 Dell Usa, L.P. Decoupled DMA transfer list storage technique for a peripheral resource controller
US5555383A (en) 1994-11-07 1996-09-10 International Business Machines Corporation Peripheral component interconnect bus system having latency and shadow timers
JPH11513150A (ja) * 1995-06-15 1999-11-09 インテル・コーポレーション Ｐｃｉ間ブリッジを統合する入出力プロセッサ用アーキテクチャ
US5925099A (en) * 1995-06-15 1999-07-20 Intel Corporation Method and apparatus for transporting messages between processors in a multiple processor system
US5848249A (en) * 1995-06-15 1998-12-08 Intel Corporation Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices
US5838935A (en) * 1995-06-15 1998-11-17 Intel Corporation Method and apparatus providing programmable decode modes for secondary PCI bus interfaces
US5734847A (en) * 1995-06-15 1998-03-31 Intel Corporation Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices
US5734850A (en) 1995-07-05 1998-03-31 National Semiconductor Corporation Transparent bridge between of a computer system and a method of interfacing the buses to operate as a single logical bus
US5857080A (en) * 1996-09-10 1999-01-05 Lsi Logic Corporation Apparatus and method for address translation in bus bridge devices
US5774683A (en) * 1996-10-21 1998-06-30 Advanced Micro Devices, Inc. Interconnect bus configured to implement multiple transfer protocols
US5832245A (en) * 1996-10-21 1998-11-03 Advanced Micro Devices, Inc. Method for isochronous flow control across an inter-chip bus
US6047349A (en) * 1997-06-11 2000-04-04 Micron Electronics, Inc. System for communicating through a computer system bus bridge
EP0887738B1 (de) * 1997-06-27 2008-08-13 Bull S.A. Busschnittstellebrücke zwischen einem Systembus und Lokalbussen mit Lokaladressenübersetzung für mittels Adressenraum programmierbaren Systemraumzugriff
JP3264319B2 (ja) * 1997-06-30 2002-03-11 日本電気株式会社 バスブリッジ
US6275888B1 (en) * 1997-11-19 2001-08-14 Micron Technology, Inc. Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers
US6374321B2 (en) * 1997-12-23 2002-04-16 Intel Corporation Mechanisms for converting address and data signals to interrupt message signals
US6745369B1 (en) * 2000-06-12 2004-06-01 Altera Corporation Bus architecture for system on a chip
US6735659B1 (en) * 2000-12-21 2004-05-11 Intel Corporation Method and apparatus for serial communication with a co-processor

Also Published As

Publication number Publication date
US7007126B2 (en) 2006-02-28
DE19882975B4 (de) 2005-08-18
KR100347076B1 (ko) 2002-08-03
US20040139267A1 (en) 2004-07-15
KR20010040936A (ko) 2001-05-15
AU1949799A (en) 1999-08-30
JP2002503847A (ja) 2002-02-05
WO1999041671A1 (en) 1999-08-19

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: G06F 13/40

8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee