DE19858650A1 - Equipment for reducing the energy consumption of a self-clocking asynchronous system - Google Patents

Abstract

The asynchronous system has several functional units (100,102) coupled together to perform at least one required task and an energy control circuit coupled to a selected one of the functional units to define a first and/or a second operating speed for the selected functional unit. Less energy is consumed by the selected functional unit operating at one speed than at the other. An Independent claim is also included for a data processor and a method of reducing the energy consumption of a self-clocking system.

Description

This invention is based on an energy control device and ins special to a self-timed energy control unit that reduces energy consumption.

A processor, such as. B. a microprocessor, a micro controller or a digital signal processor (DSP) several functional units, each with a special one Task done with a set of binary coded instructions are coupled, the operations on the functional units define within the processor architecture. The binary co dated instructions can then be combined to form one To form a program that has a certain predetermined task executes. Such programs can be found on the processor architecture executed or in memory for later use leadership can be saved.

To run a given program, the radio tional units within the processor architecture syn chronized to ensure correct execution of instructions solutions (e.g. time, order, etc.). "Syn Chrone "systems attach to the functional units first time step signal (i.e. a clock signal) to a ensure synchronized execution. In sync Related systems therefore need everyone functional units a clock signal. For a given However, statement types do not have to be all functional On units in operation. Since the functional units acti can be fourth, even if they are used to perform a given instruction are unnecessary, synchronous systems be inefficient.

The use of a fixed timing signal (i.e. one Clock cycle) in synchronous systems also limits the Ent litter of functional units. Every functional unit must be designed to operate within the clock cycle  ration in the worst possible circumstances, if even surgery under the worst circumstances can be rare like. A worst case surgery design ver degrades the performance of synchronous systems, especially if the operation of a typical case is much faster than which expires the worst case criteria. The accordingly, synchronous systems try the clock cycle reduce to minimize the performance drawbacks that by criteria for surgery under worst case be effected. Reducing the clock cycle below Worst case criteria increasingly required complicated control systems or increasingly complicated radio national units. These more complex synchronous systems reduce the efficiency in terms of area and Energy consumption to meet given performance criteria, such as B. reduced clock cycles.

Self-clocked systems of related technology, also be Knows as asynchronous systems, eliminate many problems that are connected to the clock signal of synchronous systems. In Accordingly, asynchronous systems follow performance share only in one operation of a real (rare) worst case. Accordingly, asynchronous systems can for the performance of a typical case be cut, resulting in reduced complexity for Processor designs that can meet the performance requirements achievements. Since asynchronous systems are functional units Activate only if they are for the given instruction type the efficiency is also increased. Asynchronous systems can therefore be integrated and increased energy efficiency remote.

Asynchronous systems of the related art use functional units with an asynchronous interface protocol to forward data and control information. By coupling such asynchronous functional units together to form larger blocks, increasingly complex functions can be realized. Fig. 1 shows two such functional units, which are coupled via data lines and control lines. A first functional unit 100 is a transmitter that transmits data. The second functional unit 102 is a receiver that receives the data.

Communication between the functional units 100 , 102 is achieved by bundling data wires 104 with control wires. A request control wire REQ is controlled and activated by the transmitter 100 when the transmitter 100 has placed all valid data on the data wires 104 . By the receiver 102, an acknowledgment ACK control wire is controlled and activated when the receiver 102 has the data consumed, the WUR placed on the data wires 104 to. This asynchronous interface protocol is known as a "handshake" because transmitter 100 and receiver 102 both communicate with each other to forward the bundled data.

The asynchronous interface protocol shown in FIG. 1 can use various time control protocols for data transmission. A protocol of the related art is based on a control communication scheme with four phases. Fig. 2 shows a timing diagram for the four-phase control communication scheme.

As shown in Figure 2, transmitter 100 indicates that the data on data wires 104 is valid by generating an active request control wire REQ high. Receiver 102 can now use the data as needed. When the receiver 102 no longer needs the data, it signals an active confirmation control wire ACK high back to the transmitter 100 . The transmitter 100 can now receive the data from the communication bus, e.g. B. Data wires 104 , remove and prepare for the next transmission.

In the four-phase protocol, the control lines must be returned to the initial state. Accordingly, the transmitter 100 deactivates the issue request by returning the request control wire REQ to low. Upon deactivation of the request control wire REQ, the receiver 102 can deactivate the confirmation control wire ACK to low to indicate to the transmitter 100 that the receiver 102 is ready for further data. Transmitter 100 and receiver 102 must follow this strict order of events to communicate in the four-phase control communication scheme. However, there is advantageously no upper limit for the delays between successive events.

A first first-in-first-out (FIFO) register or a FIFO pipeline provides an example of self-clocked systems that couple several functional units with one another. Fig. 3 shows such a self-timed FIFO structure. The functional units can be registers 300 a - 300 c with both an input interface protocol and an output interface protocol. When empty, can each of the registers 300 a- 300 c via an input interface 302 put data received for storage. Once the data has been saved in the register, the input interface cannot accept any further data. In this state, the input of register 300 a has "locked". The register 300 a blocked remains until the Regi-edge 300 a is empty again. However, if the register 300 a contains data once, the register 300 a can forward the data via an output interface 304 to the next stage (ie the register) of the self-timed FIFO structure. The register 300 a generates an output request when the valid from data to be played. Once the data has been used up and is no longer required, the 300 a register is then empty. Accordingly, register 300a can again receive data using the input interface protocol.

Mutual concatenation of the registers 300 a - 300 c by coupling the output interface 304 with the input interface 302 forms the multi-stage FIFO or the pipeline. Consequently, request and confirmation signals, Rout and Aout, the output interfaces are coupled with the request and confirmation signals, Rin and Ain, the input interfaces of the following register 300 a - 300 c (level). As shown in Fig. 3, in a FIFO input 306 forwarded data from register 300 a to register 300 c to finally emerge at the FIFO output 308 . The data order is thus preserved while the data is sequentially forwarded along the FIFO. The FIFO structure shown in FIG. 3 can use the four-phase control communication scheme shown in FIG. 2 as the input and output interface protocol.

The FIFO register of Fig. 3 may include logic processing. In this case, data passes through processing logic between stages of the FIFO register. As shown in Fig. 4, data access by a process ing logic 402 a-402 b between registers 300 a-300 c. Since processing logic 402 a- 402 b takes time to determine an output value, control signals (e.g., the request signal Rout of an output interface) are delayed to match the logic delay. The coordinated control signal and processing logic delay ensures that the four-phase communication protocol is met. In other words, the data arrives and the Rout request signals its validity.

As shown in Fig. 4, the delay in the request path extends the time taken to complete the handshake, allowing data processing in the processing logic to be completed. The control signal delay can be any value that is appropriate to match the logic data delay. The delay 404 a- 404 b can also be implemented differently. For example, a simple matched path, a variable delay or function of EXISTING which uses data than the delay 404 a- 404 b who the. However, an increase in the delay reduces the throughput and the performance of the self-timed system because a delay in the request / confirmation loop of the receipt exchange reduces the data transmission rate.

An object of the present invention is the problems and disadvantages of the prior art described above Essentially eliminate technology.

Another object of the present invention is that To reduce energy consumption of a semiconductor device.

Another object of the present invention is in the energy consumption of an asynchronous system Determine an operating speed based on Reduce load requirements.  

To at least complete the above tasks in whole or in part To fulfill this is an asynchronous system according to the present Invention provided that a variety of functional Units that are coupled to each other by at least one Execute task, and ent an energy control circuit keeps that functional with a selected one of the multitude Units is coupled to a first and / or a second Operating speed of the selected functional on to determine.

To further complete the above tasks in whole or in part to meet, is a data processing device according to the before lying invention provided the multiple functional one an asynchronous control unit that has a current instruction decoded to a corresponding instruction task using a group of the multiple functional ones units to perform an energy determination device, wor into the data processing device at one of several energy providers giepegeln works by the energy determination device device was selected, and a communication device contains the functional units that determine energy mungseinrichtung and the control unit couples.

To continue the above tasks in whole or in part Meeting this is a method of operating an asyn chronic system with several, coupled radio tionese units according to the present invention hen that is determining operational criteria of the asynchro system and determining one of several energy ver levels based on the surgical criteria of the asynchronous system.

Additional advantages, tasks and features of the Erfin are explained in part in the following description and partially apparent to one skilled in testing the following Lich or can from the practical implementation of the Invention to be learned. The tasks and advantages of the Er can find, as in particular in the appended claims Chen is executed, realized and achieved.

An embodiment of an asynchronous system and A method to operate this is as follows described with reference to schematic drawings. Show it:  

Fig. 1 is a block diagram showing a self-timed data interface;

Fig. 2 is a diagram showing signal waveforms of a four-phase communication protocol represents;

Figure 3 is a block diagram showing a self-timed first-in-first-out (FIFO) data interface;

Fig. 4 is a block diagram showing a FIFO interface that includes processing and control logic;

Fig. 5 is a block diagram illustrating a digital processor;

Fig. 6 shows an operation of an instruction pipeline is alternate diagram;

Fig. 7 is a a self-timed processor represent the block diagram; and

Fig. 8 is a block diagram of a preferred form of execution of a processor interface with a control logic.

The system performance (e.g. throughput) of a self-timed system can be controlled by the speed of critical elements. A critical element performs a task that must be completed before the self-timed system continues processing. In a digita len processor, a critical element such. B. an instruction call. An exemplary architecture of a digital processor 500 is shown in FIG. 5. The architecture of processor 500 includes functional units that can be used in a microprocessor, microcontroller, and DSP implementation or the like. To run a program on a processor architecture, such as. For example, to implement processor 500 , a set of instructions and corresponding instruction tasks must be defined. During the operations, each instruction is decoded to activate the functional units required to execute the corresponding instruction task. Each of the functional units is coupled by a common resource data bus 516 .

A functional unit program counter PC 502 generates an instruction program address. The PC 502 may include an address stack for holding addresses of subroutine or interrupt calls. An instruction decoder 504 functional unit controls instruction fetch and decoding. The functional unit instruction decoder 504 includes an instruction decoder for generating control information for the functional units and a status register for maintaining a current process status. A functional arithmetic and logic unit ALU 506 performs data and arithmetic operations using integer arithmetic ALU. The ALU 506 also includes a data accumulator for storing a result of a particular data or arithmetic operation.

The processor 500 may further include a functional unit multiplier MULT 508 , which performs data multiplication, and a functional unit indirect address register ADDR 510 . The ADDR 510 contains indirect data addresses in an address register field. A functional random access memory RAN 514 is used to store data values. The functional unit data RAM controller RAMC 512 controls memory access to a data memory in the RAN 514 .

In the processor 500 , the functional blocks work simultaneously. However, processor 500 must ensure correct management of the data bus 516 of a shared operation by controlling data and sequence requests when data transfers occur between functional units. Processor 500 preferably uses a three-stage instruction pipeline consisting of an instruction fetch, instruction decode, and instruction execution cycle. A pipelined architecture improves performance requirements by allowing more efficient (e.g., simultaneous) use of the functional units of processor 500 . As shown in Fig. 6, the three-stage instruction pipeline allows each pipeline stage to overlap, which increases concurrency and processor performance.

Figure 7 shows the example of an instruction fetch that is the critical element in an asynchronous system. As illustrated, FIG. 7 is similar to FIG. 4, but the register, logic, and matched delay are grouped together as a single pipeline stage. In self-timed systems, system speed can be reduced by changing the performance (cycle time) of a critical functional unit because the receipt exchange in each functional unit must complete before the next element can be accepted. The system performance of the processor 500 can e.g. B. similarly reduced by increasing the delay of an instruction fetch by decoder 504 (ie, the processor can only process instructions as quickly as they are issued). As a result, a dedicated timer can be used to control throughput of a circuit, subsystem, or system by changing the operating speed of a functional unit.

In contrast, the system performance becomes synchronous Sy steme controlled by the clock. In a synchronous system consequently the speed of the system cannot be under Use the speed of a functional unit be controlled because the clock speed the system certainly. To slow down the synchronous system, the correspondingly every functional unit in the synchronous system to be slowed down.

In a semiconductor device and in particular in a technology with an integrated CMOS circuit, the energy consumption is proportional to the operating frequency. In other words, the higher the operating frequency for a given circuit, the higher the energy consumption. Energy consumption can be done by the following equation:

E = 1/2 CV ² × frequency (1)

be determined. In the equation above, E is the energy C the capacity, V the voltage and frequency 1 / cycle time.

In self-clocked systems, when the cycle time is increased, the frequency and energy consumption decrease device. According to the preferred embodiments of the present the invention can therefore the energy consumption of yourself clocked system by setting a cycle time of one critical functional unit or an element of the sy can be controlled.

Using the example described above one The processor does a priority job on instruction fetches at a first or full speed. If the  However, the processor is idle (e.g. waiting) is working then the processor at a second or reduced Ge dizziness. Accordingly, the system performance the second speed is reduced by the cycle time the instruction fetch level is increased. Hence the Ener Energy consumption of the self-timed system in the second Speed reduced.

Fig. 8 shows an arrangement for setting the energy consumption for a self-timed processor according to a first preferred embodiment of the present inven tion. As shown in Fig. 8, a variable cycle time used to control energy consumption is based on an instruction queue length. An energy control device 802 dynamically adjusts the system performance (e.g. cycle time) and the energy consumption depending on workload requirements. In the first preferred embodiment, the setting of the system performance is achieved by changing a variable delay in a processing stage (e.g. instruction fetch).

As shown in Figure 8, an instruction queue length is used to indicate processor workload requirements. A counter is used to count the number of items (e.g. instructions) waiting in a queue to be processed. The variable cycle time is then controlled by the energy control device 802 as a function of the queue length. As the "queue length" becomes longer and there is more work to be done, the delay (e.g. cycle time) is reduced. Accordingly, the system's energy consumption and system performance are increased. As the "queue length" of a job becomes smaller, the cycle time is increased to reduce energy consumption and system performance. The energy consumption thus corresponds to the amount of work to be carried out (e.g. execution instructions of the processor).

Thus, in a self-timed system, the operating speed can be controlled by controlling part of the system. In Fig. 7, the cycle time of a sub-block or sub-system can be increased by increasing the delay in the handshake loop. The first preferred embodiment thus monitors an instruction queue length to reduce the energy consumption of the self-timed system. The control structure can also be easily implemented.

Alternative preferred embodiments use ver Different devices and processes to meet the work requirements of the Systems to monitor to reduce energy consumption ren. A second preferred embodiment according to the before lying invention uses an explicit requirement reduce energy consumption. The requirement can un ter use z. B. an instruction executed in the system or a specific value at an external input, such as B. an external pin for the system leads. The external connector pin can be used for the user be accessible.

A third preferred embodiment according to the present The present invention uses the activation of certain radio tional units to control energy consumption. To the For example, a processor can be based on a particular one functional unit can be accelerated or slowed down (For example, a functional unit can be multiplier need a faster operation).

As described above, the preferred controls control management forms of the present control system of energy consumption using a variable delay in a functional unit, to cycle time with an ir linked to a measure of a system load. The present However, the present invention is not intended to be based on this embodiment be limited. Various alternative ads from Workload requirements such as B. application specific Load indicators can be used to measure the cycle time to control.

In addition to controlling the entire system performance er a fourth preferred embodiment of the present Invention also the energy consumption of one or more individual subcircuits or subsystems of an asynchronous Systems. In the fourth preferred embodiment, one is Variable delay unit required per subsystem Lich. The fourth preferred embodiment specifically allows len parts of the system, with respect to other parts of the sy  stems to reduce energy consumption. In this way can be a first functional unit of several functi onal units in the system use Ab work at a lower priority than the rest selectively reduce functional units.

As described above, the preferred identifiers different advantages. The preferred Embodiments reduce energy consumption asynchro systems. For example, a portable device where the energy consumption (e.g. battery life) directly with the potential useful life, while rela tiv longer periods can be used. The energy ver Consumption levels can also be based on a priority of Selective workload requirements of the system or the like tiv be set. In addition, different parts of the system systems operated at different energy consumption levels turn.

The previous embodiments are only examples liable and should not be considered as the present invention be viewed restrictively. The present teaching can oh ne more to be applied to other types of devices. The Be description of the present invention is intended to be illustrative be and not limit the scope of the claims. Lots Alternatives, modifications and modifications are the subject man visible.

Claims (28)

1. Asynchronous system with:
a plurality of functional units which are coupled to one another in order to carry out at least one task; and
an energy control circuit coupled to a selected one of a plurality of functional units to determine a first and / or a second operating speed of the selected functional unit. 2. Asynchronous system according to claim 1, wherein the asyn chrone system when the selected functional unit at the second operating speed works, less ener gie consumed as if the selected functional unit works at the first operating speed. 3. An asynchronous system according to claim 1, wherein the loading drive speed of the selected functional unit an operating speed of the asynchronous system be Right. 4. An asynchronous system according to claim 1, wherein the first and second operating speeds based on one Statement queue length, one statement, one external signals and / or application-specific criteria be true. 5. Asynchronous system according to claim 1, wherein the Ener casting control circuit for a variable operating speed selects the selected functional unit. 6. Asynchronous system according to claim 5, wherein the Ener pour control circuit on the variable operating speed the basis of an instruction queue length, an instruction solution, an external signal and / or application-specific Selects criteria. 7. An asynchronous system according to claim 1, wherein the loading drive speed an operation cycle time of a radio tional unit, in which the cycle time is the inverse of a Operating frequency.   8. An asynchronous system according to claim 7, wherein the cycle time on an input protocol delay and / or Output protocol delay based. 9. An asynchronous system according to claim 1, wherein the lot number of functional units in several functional groups Units is divided and in which the energy control circuit has several energy control units, each one correspond to the groups of functional units, and wherein each of the energy control units has a variable operating ge speed for the corresponding of the functional groups Units using a designated functional Unit in each of the groups of functional units poses. 10. An asynchronous system according to claim 1, wherein the loading drive speed of the selected functional unit the energy consumption of a subsystem of the asynchronous Sy stems determined. 11. Data processing device with:
several functional units;
an asynchronous control unit that decodes a current instruction to execute a corresponding instruction task using a group of the plurality of functional units;
an energy determination device, wherein the data processing device operates at one of a plurality of energy levels selected by the energy determination device; and
a communication device that couples the functional units, the energy determination device and the control unit. 12. The data processing apparatus according to claim 11, wherein the Energy determination device modified a cycle time. 13. The data processing apparatus according to claim 12, wherein the Cycle time a cycle time of a selected functional Unit and / or a cycle time of the data processing unit is guesswork. 14. The data processing apparatus according to claim 11, wherein a selected energy level on an instruction queue length, an instruction, an external signal and / or application-specific criteria.   15. The data processing apparatus according to claim 11, wherein the Energy determination device with a selected one of the Variety of functional units is coupled to a first and / or second operating speed of the selected one functional unit. 16. The data processing apparatus according to claim 15, wherein the Data processing device when the selected functional Unit operates at the second operating speed, in less energy in relation to the first operating speed consumed. 17. The data processing apparatus according to claim 11, wherein the selected energy level an operating speed of the Data processing device determined. 18. The data processing apparatus according to claim 11, wherein the Energy determination device the energy consumption for one Controls part of the data processing device. 19. The data processing device according to claim 11, further comprising several energy determination facilities. 20. The data processing apparatus according to claim 11, wherein the Control unit and a three-stage instruction pipeline Four-phase communication protocol used and what the Communication device is a data bus. 21. A method for operating an asynchronous system with a plurality of functional units coupled to one another, the method comprising:
determining operational criteria of the asynchronous system; and
determining one of several energy consumption levels based on the operational criteria of the asynchronous system. 22. The method of claim 21, wherein an execution speed of the asynchronous system on the energy ver consumption level based. 23. The method of claim 21, wherein the step Be agreeing operational criteria determining work has load requirements of the asynchronous system. 24. The method of claim 21, wherein the step Be agree one of several energy consumption levels agree an operating speed for a selected one  the functional units and / or the asynchronous system having. 25. The method of claim 24, wherein the Betriebsge speed of the selected functional unit drive speed of the asynchronous system determined. 26. The method of claim 25, wherein the selected one functional unit is an instruction decoder. 27. The method of claim 24, wherein the operating area speed of the selected functional unit Energy consumption level of a subsystem of the asynchronous sy stems determined. 28. The method of claim 21, wherein operational criteria en on determining an instruction queue length, an instruction type, an external signal type and / or an egg based on a functional unit type.