DE19843433A1 - Semiconductor chip and semiconductor component with such a semiconductor chip - Google Patents

Semiconductor chip and semiconductor component with such a semiconductor chip

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Publication number
DE19843433A1
DE19843433A1 DE19843433A DE19843433A DE19843433A1 DE 19843433 A1 DE19843433 A1 DE 19843433A1 DE 19843433 A DE19843433 A DE 19843433A DE 19843433 A DE19843433 A DE 19843433A DE 19843433 A1 DE19843433 A1 DE 19843433A1
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Germany
Prior art keywords
semiconductor chip
semiconductor
passivation layer
chip
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19843433A
Other languages
German (de)
Inventor
Alexandra Atzesdorfer
Achim Neu
Thies Janczek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19843433A priority Critical patent/DE19843433A1/en
Priority to PCT/DE1999/003006 priority patent/WO2000017926A1/en
Publication of DE19843433A1 publication Critical patent/DE19843433A1/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The invention relates to a semiconductor chip (1) or to a semiconductor component (1) comprising such a semiconductor chip, whereby a ceramic polymer is used for passivating (5) the semiconductor chip (1).

Description

Die Erfindung bezieht sich auf einen Halbleiterchip bzw. auf ein Halbleiterbauelement mit einem solchen Halbleiterchip ge­ mäß dem Oberbegriff der Patentansprüche 1 bzw. 2.The invention relates to a semiconductor chip or to a semiconductor device with such a semiconductor chip according to the preamble of claims 1 and 2.

Üblicherweise werden heutzutage einzelne Schaltungselemente, wie beispielsweise Transistoren oder Dioden oder gesamte Schaltungen auf einem Halbleiterchip ausgebildet. Bei der späteren Verwendung wurden diese Halbleiterchips bisher mit einem Gehäuse versehen, das üblicherweise aus einer Spritz­ gußmasse besteht, wobei Kontakte für elektrische Anschlüsse vorgesehen sind, die an den vom Gehäuse umgebenden Halblei­ terchip elektrisch anschließbar sind. Zunehmend kommt es je­ doch auch vor, daß die zuvor genannten Halbleiterchips im Rahmen einer größeren Gesamtschaltung direkt ohne Gehäuse auf einer sogenannten Leiterplatte ohne das zuvor beschriebene Gehäuse angeordnet werden.Nowadays, individual circuit elements, such as transistors or diodes or all Circuits formed on a semiconductor chip. In the These semiconductor chips have been used later provided with a housing, usually from a spray Casting compound consists of contacts for electrical connections are provided on the half lead surrounded by the housing terchip are electrically connectable. It is ever increasing but also before that the aforementioned semiconductor chips in Frame of a larger overall circuit directly without housing a so-called circuit board without the previously described Housing are arranged.

In beiden Fällen ist es jedoch notwendig, daß die aktiven Strukturen des Halbleiterchips, die ein oder mehrere Schal­ tungselemente aufweisen, vor mechanischen Beschädigungen, wie beispielsweise Kratzer oder chemischen Einflüssen, wie bei­ spielsweise Korrosion, geschützt werden. Hierzu wird üblicherweise der Halbleiterchip zumindest oberhalb der aktiven Strukturen mit einer sogenannten Passivierungsschicht versehen, wobei diese Passivierungsschicht auch aus mehreren Einzelschichten bestehen kann. In der US 5,287,003, ist ein Halbleiterchip mit einer derartigen Passivierungsschicht bzw. ein Halbleiterbauelement mit einem derartigen Halbleiterchip beschrieben. Dabei ist dieser Druckschrift zu entnehmen, daß als Passivierungsschicht Siliziumnitrid oder auch Polyimid als Passivierungsschicht verwendbar ist. In both cases, however, it is necessary that the active Structures of the semiconductor chip, the one or more scarf tion elements, from mechanical damage, such as for example scratches or chemical influences, such as for example, corrosion. To do this usually the semiconductor chip at least above the active structures with a so-called passivation layer provided, this passivation layer also from several Individual layers can exist. In US 5,287,003, is a Semiconductor chip with such a passivation layer or a semiconductor device with such a semiconductor chip described. It can be seen from this document that as a passivation layer silicon nitride or polyimide can be used as a passivation layer.  

Siliziumnitrid weist jedoch eine sehr große Härte auf und ist zudem sehr spröde, was leicht zur Rißbildung führen kann. Eine solche auch Hartpassivierung genannte Schicht, wird zu­ nehmend seltener benutzt, da sie insbesondere bei kleiner werdenden Chipstrukturen, die eine zunehmende Empfindlichkeit gegen Außeneinflüsse aufweisen, verstärkt zu Ausfällen füh­ ren. Dieses sogenannte Hartpassivierungsverfahren ist zudem mit einem hohen technischen Aufwand verbunden, da es in einem sogenannten Plasmanitrierverfahren unter Vakuum zu erzeugen ist.However, silicon nitride is very hard also very brittle, which can easily lead to cracking. Such a layer, also called hard passivation, becomes used less often because they are especially small Expectant chip structures that have increasing sensitivity against external influences, increasingly lead to failures ren. This so-called hard passivation process is also associated with a high technical effort, since it is in one to produce so-called plasma nitriding processes under vacuum is.

Polyimid ist eine sogenannte Softpassivierung und hat gegen­ über der zuvor beschriebenen Hartpassivierung den Vorteil, daß es im einfach handhabbaren sogenannten "Spin-off-Ver­ fahren" aufgetragen werden kann. Dabei ist keine Vakuumat­ mosphäre, sondern eine normale Atmosphäre ausreichend. Polyimid weist weiterhin die Vorteile auf, daß es mit Photoätztechnik anschließend weiterverarbeitbar ist. Der große Nachteil von Polyimid liegt jedoch darin, daß es sehr teuer ist, was insbesondere bei den unter zunehmenden Kostendruck stehenden Massenprodukten der Halbleitertechnik von Nachteil ist.Polyimide is a so-called soft passivation and has against the advantage over the hard passivation described above, that it is in the so-called "spin-off ver." driving "can be applied. There is no vacuum atmosphere, but a normal atmosphere is sufficient. Polyimide also has the advantages of having Photoetching technology can then be further processed. The major disadvantage of polyimide, however, is that it is very is expensive, which is increasing especially among those under Mass products of semiconductor technology facing cost pressure is a disadvantage.

Der Erfindung liegt somit die Aufgabe zugrunde einen Halblei­ terchip bzw. ein Halbleiterbauelement mit einem solchen Halb­ leiterchip vorzusehen, der zuverlässig arbeitet und möglichst einfach und kostengünstig herstellbar ist.The invention is therefore based on the object of a half lead terchip or a semiconductor device with such a half to provide a conductor chip that works reliably and if possible is easy and inexpensive to manufacture.

Diese Aufgabe wird erfindungsgemäß mit den im Patentanspruch 1 bzw. 2 angegebenen Maßnahmen gelöst.This object is achieved with the in claim 1 or 2 specified measures solved.

Durch die Verwendung von keramischen Polymeren als Passivie­ rung werden die Vorteile von Hart- bzw. Softpassivierung mit­ einander verknüpft, d. h. keramische Polymere weisen eine ge­ genüber Polyimid gesteigerte Härte auf, sind jedoch einfach auftragbar. Zusätzlich lassen sich die Eigenschaften kerami­ scher Polymere durch Variation der Reaktivmonomere bzw. des Verbindungselementes (Se, Al, Te) verändern.Through the use of ceramic polymers as a passive The benefits of hard and soft passivation are shared linked together, d. H. Ceramic polymers have a ge hardness compared to polyimide, but are simple applyable. In addition, the properties of kerami  shear polymers by varying the reactive monomers or Change the connecting element (Se, Al, Te).

Nachfolgend wird die Erfindung unter Bezugnahme auf die Zeichnung im einzelenen erläutert.The invention is described below with reference to FIG Drawing explained in detail.

Es zeigen:Show it:

Fig. 1 einen erfindungsgemäßen Halbleiterchip und Fig. 1 shows a semiconductor chip according to the invention and

Fig. 2 ein erfindungsgemäßes Halbleiterbauelement. Fig. 2 shows an inventive semiconductor component.

In Fig. 1 ist ein Halbleiterchip dargestellt, der ein Halb­ leitersubstrat 1 aufweist. Auf diesem Halbleitersubstrat sind nicht dargestellte aktive Strukturen ausgebildet, die ein einzelnes Schaltungselement, wie beispielsweise einen Transi­ stor oder eine Diode, oder auch komplexe Schaltungen umfaßt. Abgedeckt ist das Halbleitersubstrat 1 von einer Silizi­ umoxidschicht 2, in der wiederum nicht dargestellte Kontakt­ löcher für die Kontaktierung der aktiven Strukturen vorgese­ hen sind. Oberhalb dieser Kontaktlöcher sind Kontaktflächen bzw. Kontakt-Pads 3 ausgebildet, die aus Aluminium bzw. einer Aluminiumlegierung bestehen. Üblicherweise ist eine zweite Siliziumoxidschicht 4 vorgesehen, die mittels eines CVD-Pro­ zesses (chemical vapor deposition) aufgetragen ist. Als gemäß Fig. 1 vorgesehene oberste Schicht ist eine Passivierungsschicht 5 aus einem keramischen Polymer vorgesehen. Diese Passivierungsschicht 5 weist eine Dicke in der Größenordnung 2-6 µm auf. Die Eigenschaften des elastischen Polymers sind dabei einstellbar. Dabei steuert das Mischungsverhältnis die Lastigkeit der Eigenschaften des keramischen Polymers, wie beispielsweise die Härte, Tem­ peraturbeständigkeit und optische Eigenschaften. Die Ketten­ länge und der Vernetzungsgrad der Polymerverbindung steuert weiterhin das elastische Verhalten dieser Verbindung.In Fig. 1, a semiconductor chip is shown, which has a semiconductor substrate 1 . Active structures, not shown, are formed on this semiconductor substrate and comprise a single circuit element, such as a transistor or a diode, or else complex circuits. The semiconductor substrate 1 is covered by a silicon oxide layer 2 , in which, in turn, contact holes (not shown) are provided for contacting the active structures. Above these contact holes, contact surfaces or contact pads 3 are formed, which consist of aluminum or an aluminum alloy. A second silicon oxide layer 4 is usually provided, which is applied by means of a CVD process (chemical vapor deposition). A passivation layer 5 made of a ceramic polymer is provided as the top layer provided according to FIG. 1. This passivation layer 5 has a thickness of the order of 2-6 μm. The properties of the elastic polymer are adjustable. The mixing ratio controls the load of the properties of the ceramic polymer, such as hardness, temperature resistance and optical properties. The chain length and the degree of crosslinking of the polymer compound further controls the elastic behavior of this compound.

Ein solcher Polymer kann photochemisch und thermisch aushär­ ten und läßt sich photolithographisch strukturieren. Das thermische Aushärten findet bei Temperaturen unterhalb 170°C satt.Such a polymer can cure photochemically and thermally and can be structured photolithographically. The  thermal curing takes place at temperatures below 170 ° C Fed up.

In Fig. 2 ist ein erfindungsgemäßes Halbleiterbauelement mit einem zuvor beschriebenen Halbleiterchip dargestellt. Dabei ist der Halbleiterchip auf einem Trageelement 7 angeordnet, und über eine sogenannte Draht-Bond-Verbindung 8 mit Kontakt­ elementen 9 elektrisch verbunden. Das Trageelment 7 und die Kontaktelemente 9 sind üblicherweise Teil eines sogenannten Leadframes. Durch das Einstellen der Elastizität des kera­ mischen Polymers, aus dem die Passivierungsschicht 5 herge­ stellt ist, lassen sich insbesondere die benötigten Eigen­ schaften zwischen dem Halbleiterchip, die bedeutend durch die Eigenschaften der Passivierungsschicht 5 gekennzeichnet sind und den Eigenschaften des aus Preßmasse bestehenden Gehäuses 6 an den Grenzflächen optimieren. Die weiteren Elemente, die mit gleichem Bezugszeichen versehen sind, entsprechen denen in Fig. 1 und werden nachfolgend nicht nochmals erläutert.In FIG. 2, an inventive semiconductor device is shown with a previously described semiconductor chip. The semiconductor chip is arranged on a support element 7 , and electrically connected to contact elements 9 via a so-called wire-bond connection 8 . The support element 7 and the contact elements 9 are usually part of a so-called lead frame. By adjusting the elasticity of the ceramic polymer from which the passivation layer 5 is produced, in particular the properties required between the semiconductor chip, which are significantly characterized by the properties of the passivation layer 5 and the properties of the housing 6 made of molding compound optimize the interfaces. The other elements, which are provided with the same reference numerals, correspond to those in FIG. 1 and are not explained again below.

Abschließend ist noch darauf hingewiesen, daß die Erfindung nicht auf die in Fig. 2 dargestellte Gehäusebauform einge­ schränkt ist, sondern diese nur beispielhaft erläuternd beschrieben ist. Die Erfindung ist auf eine Vielzahl von unterschiedlichen Gehäusebauformen auch ohne die Verwendung eines Leadframes übertragbar.Finally, it should also be noted that the invention is not limited to the housing design shown in FIG. 2, but that this is only described by way of example. The invention can also be applied to a large number of different housing designs without the use of a lead frame.

Claims (2)

1. Halbleiterchip bestehend aus einem Halbleitersubstrat (1), auf dem eine aus zumindest einem elektrischen Schaltungselement bestehende integrierte Schaltung ausgebildet ist, und einer Passivierungsschicht (5), die auf zumindest einer Seite des Halbleitersubstrates ausgebildet ist, dadurch gekennzeichnet, daß die Passivierungsschicht (5) aus einem keramischen Poly­ mer besteht.1. A semiconductor chip comprising a semiconductor substrate ( 1 ) on which an integrated circuit consisting of at least one electrical circuit element is formed, and a passivation layer ( 5 ) which is formed on at least one side of the semiconductor substrate, characterized in that the passivation layer ( 5 ) consists of a ceramic poly mer. 2. Halbleiterbauelement mit einem Halbleiterchip, bestehend aus einem Halbleitersubstrat (1) und zumindest einem Kontakt (3), der für eine aus zumindest einem Schaltungselement be­ stehenden integrierten Schaltung, die in dem Halbleiterchip ausgebildet ist, eine Anschlußfläche bildet, die mit An­ schlußelementen (8, 9) elektrisch verbunden ist, und einem Halbleitergehäuse (6), das den Halbleiterchip und die An­ schlußelemente soweit umgibt, daß die Anschlußelemente (9) nur teilweise aus dem Gehäuse (6) herausragen, wobei der Halbleiterchip zumindest auf der Seite, auf der sich zumin­ dest ein Kontakt (3) befindet, eine Passivierungsschicht (5) aufweist, dadurch gekennzeichnet, daß die Passivierungsschicht (5) aus einem keramischen Polymer besteht.2. Semiconductor component with a semiconductor chip, consisting of a semiconductor substrate ( 1 ) and at least one contact ( 3 ), which forms a connection surface for an integrated circuit consisting of at least one circuit element, which is formed in the semiconductor chip, which with connection elements ( 8, 9) is electrically connected, and a semiconductor package (6), which locking elements the semiconductor chip and to the extent that surrounds the connecting elements (9) only partially project out of the housing (6), wherein the semiconductor chip at least on the side on which is at least one contact ( 3 ), has a passivation layer ( 5 ), characterized in that the passivation layer ( 5 ) consists of a ceramic polymer.
DE19843433A 1998-09-22 1998-09-22 Semiconductor chip and semiconductor component with such a semiconductor chip Ceased DE19843433A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE19843433A DE19843433A1 (en) 1998-09-22 1998-09-22 Semiconductor chip and semiconductor component with such a semiconductor chip
PCT/DE1999/003006 WO2000017926A1 (en) 1998-09-22 1999-09-20 Semiconductor chip and a semiconductor component comprising such a semiconductor chip

Applications Claiming Priority (1)

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DE19843433A DE19843433A1 (en) 1998-09-22 1998-09-22 Semiconductor chip and semiconductor component with such a semiconductor chip

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DE19843433A1 true DE19843433A1 (en) 2000-03-30

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0274274A2 (en) * 1987-01-02 1988-07-13 Dow Corning Corporation Multilayer ceramic coatings from silicate esters and metal oxides
US5287003A (en) * 1991-02-26 1994-02-15 U.S. Philips Corporation Resin-encapsulated semiconductor device having a passivation reinforcement hard polyimide film

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3616378A1 (en) * 1986-05-15 1987-11-19 Innotec Ges Fuer Spitzentechno Process for producing ceramic polymeric materials and accordingly produced material
US4997482A (en) * 1987-01-02 1991-03-05 Dow Corning Corporation Coating composition containing hydrolyzed silicate esters and other metal oxide precursors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0274274A2 (en) * 1987-01-02 1988-07-13 Dow Corning Corporation Multilayer ceramic coatings from silicate esters and metal oxides
US5287003A (en) * 1991-02-26 1994-02-15 U.S. Philips Corporation Resin-encapsulated semiconductor device having a passivation reinforcement hard polyimide film

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