DE19841470A1 - Error testing method of RAM especially for mobile radio equipment - Google Patents

Abstract

The method involves sequential and periodic reading of data words from the memory, followed by processing and re-writing into the memory. The data words are provided with parity bits for error/fault tests. A data word (D) is read from an address (3) during a clock-cycle (T) and a parity bit (P) is added to the word. The new data word (D4) is written in to the next higher address in the subsequent clock-cycle (T5), after reading a data word (D5) from the next higher address. After N clock-cycles, the data word is re-read and has a parity bit added to it. The parity bit is compared with the preceding parity bit of the data word (D4) and a new parity pit (P4N) is added to the new data word (D4N) and then stored. The new, processed data word (D4N) is then written into the next higher address (5), after being read out from the address.

Description

The invention relates to a method for error checking a read-write memory with N addresses, in which Data words of width M are stored, the data words sequentially and periodically in processing steps read from memory, then edited and then be written back into memory, and the data word parity bits for error checking.

To follow errors within a read-write memory Finding the RAM for short is used in some applications an ongoing memory test. Here a redundancy bit is created for each individual RAM word, i. H. on Parity bit provided and saved. Returns the Parity check after reading a different value than before saving, it may indicate an error in the storage space getting closed.

Especially in applications with regard to power consumption and construction volume are critical, e.g. B. in the mobile communications area the known method disadvantageous because of additional memory space is needed, which is the chip area of the RAM on the one hand and the power dissipation of the RAM on the other hand increases.

An application from which the invention originated are digital filters, here FIR filters, for echo cancellation in cellular and satellite radios or similar systems men. There are, for example, N PCM channels, and for M channel coefficients are required for each channel Sense of an adaptive filter according to the actual existing echo conditions are constantly recalculated and must be saved again. For parity check accordingly, all memory locations require M * N parity bits Lich, in practical applications such. B. 508 x 32 = 16 256  Parity bits. The scanning steps are, for example se 125 µs.

An object of the invention is an ongoing over Checking all storage spaces when reducing the for To allow parity bits to have the required storage space.

The task is based on a process of type mentioned, achieved according to the invention in that one data word from one address within one cycle and a parity bit is formed for this data word, the data word is edited to the edited new one Data word a parity bit is formed and stored, and the new data word in the next cycle after reading out the data word from the next higher address into these addresses it is written, N bars on it within one bar the data word is read in turn for this data word Parity bit is formed, the parity bit with the previous parity bit of this data word is compared, the Data word is edited to the edited, new data word a parity bit is again formed and stored, and the new, edited data word after reading out the data words from the next higher address to this address is written.

The inventive method causes the data words in which RAM is no longer assigned a fixed address, but "walking in a circle" in time with the processing steps. However, this means that a certain data word within a period N.N. "visited" all N addresses. This is it is possible to parity only one of the N data words to monitor, and yet all addresses peri odically checking for errors without it being necessary with each processing step at each address parity bit.  

The method according to the invention shows particular advantages, if the data words filter coefficients of a digital Filters for N channels or the digital filter are adap tives FIR filter. Namely, these use cases are at least in mobile devices very energy and space-critical table.

The invention together with further advantages is explained in more detail below using an exemplary embodiment with reference to the drawing. In the drawing, FIGS. 1a and 1b schematically show the sequence of the method according to the invention with the formation of a parity bit in the fourth working step or cycle.

In the drawing, a read-write memory RAM is shown schematically, in which data words D _i are written cyclically and linearly. In the present application example, the data words are filter coefficients of an adaptive FIR filter for N PCM channels in a mobile radio or satellite radio terminal, the filter being used for echo cancellation. It is designed as a transversal filter and contains a runtime chain with z. B. 508 gears, so that a receive path signal with a z. B. each delayed 125 µs delay at each output. Each of these signals is multiplied by its own coefficient - corresponding to a data word D _i - and summed up in an accumulator. Each end echo path can be compensated for by a suitable choice of the coefficients, provided that the running time in the present case is less than 508,125 µs = 63.5 ms.

The coefficients = data words are used during each clock read from RAM, updated and recalculated and then written back to memory.

In the upper half of the drawing, namely in FIG. 1a, the process of reading, calculating and rewriting for three bars T ₃ , T ₄ , T ₅ of N bars of a period is shown, in the right half of the drawing, namely in FIG . 1b, three clocks for the following period, that is, for the clock pulses T _{N + 3, N} T _{+ 4,} T _{n + 5.}

A check is made to check the RAM for errors used with parity bits, with the special feature of the method according to the invention is that only provide a single one of the N data words with a parity bit and yet a check of the RAM at all Liche addresses is possible, which is described below.

The clock T ₄ is now considered, in which a data word D4 _{old is} read from the address 3 and an updated, recalculated data word is written to the address 3. A parity bit P4 _{old is} formed for the data word D4 _{old in} order to be compared with a parity bit from the previous cycle, which will be explained later.

The read data word D4 is _old now processed, ie updated and recalculated - if necessary - and then is _re-formed a parity bit P4 to the new, processed data word D4 _new and stored. In the subsequent cycle T ₅ , the new data word D4 is written _new to this address after reading out the data word D5 _old from the next higher address 4. This is followed by the reading, calculation and writing processes for the further clocks T ₆ , T ₇ , etc., but without parity bit formation, which is only carried out in the clock T ₄ .

N clocks later, ie after exactly one period, this period, ie within the clock T _{n + 4} , the data word D4 _{N, old} is read again within the fourth clock, and a parity bit P4 _N becomes _old for this data word D4 _{N , old} educated. The parity bit P4 ses _{N, old} will now be compared with the _new one period previously formed parity bit P4 (Fig. 1a). If the compared parity bits are not the same, an error in the RAM can be concluded.

Now the data word D4 _{N, old is} processed, and then a new parity bit P4 _{N is newly} formed and stored for the new, processed data word D4 _N. The new, processed data word D4 _{N, new} is written into this address after reading out the data word D5 _{N, old} from the next higher address 5 .

The stored parity bit P4 _{N, new} is subsequently compared with the _old cycle (not shown here) with an analog parity bit P42 _N ( FIG. 1b).

It can be seen that in the described process all Move data words one address in each cycle, thus also the data word D4 on which the parity operation is made. The RAM is checked for errors therefore not in every cycle (period) N for all memories places together, but only in each cycle (period) for a storage space, but this way too all memory locations regularly every N.N cycles for errors checked.

The method according to the invention is based on the example of an adap tive FIR filter, but it is clear that this method is used for every random access memory can be in which data words sequentially and peri be written or read oddly.

Claims (3)

1. Method for checking the error of a read-write memory with N addresses, in which data words of width M are stored, the data words being read from the memory sequentially and periodically in processing steps, then processed and then rewritten into the memory, and the data words are provided with parity bits for error checking, characterized in that
that a data word (D4 _old ) is read from an address (3) within a cycle (T4) and a parity bit (P4 _old ) is formed for this data word, the data word is processed,
a parity bit (P4 _new ) is formed and stored for the processed new data word (D4 _new ), and
the new data word (D4 _new ) is written to this address in the subsequent cycle (T5) after reading out the data word (D5 _old ) from the next higher address (4),
N cycles thereafter the data word (D4 _{N, old} ) is read again within one cycle (T _{N + 4} ) _, a parity bit (P4 _{N, old} ) is formed for this data word (D4 _{N, old} ),
the parity bit (P4 _{N, old} ) is compared with the previous parity bit (P4 _new ) of this data word (D4), the data word (D4 _{N, old} ) is processed,
a parity bit (P4 _{N, new} ) is formed and stored again for the processed, new data word (D4 _{N, new} ), and the new, processed data word (D4 _{N, new} ) is read out after reading out the data word (D5 _{N, old} ) the next higher address (5) is written in this address. 2. The method according to claim. 1, characterized in that the data words filter coefficients of a digital filter for N channels. 3. The method according to claim 2, characterized in that the digital filter adapted FIR filter.