DE19816153A1 - Bus interconnect system for graphic processing system - has individual buses coupling graphics processing elements in ring, with signal lines for transferring command signals between elements - Google Patents

Abstract

The system includes a bus structure, coupling a number of graphics processing elements (202,222,242) in a ring. The bus structure comprises a number of individual buses (250,252,254), with each bus connecting a pair of graphics processing elements. Each individual bus comprises a number of signal lines (250A-250F) for transferring graphics command signals and information signals between graphics processing elements in the ring.

Description

This invention relates generally to the field of computer systems and in particular on interfaces circuits for digital pipeline data transmission.

Computer graphics systems are generally used for display graphic representations of objects on a two-dimensional sional display screen used. Current computers graphic systems can provide highly detailed representations and are used in a variety of applications.

In typical computer graphics systems, an object that to be displayed on a display screen, in a Plurality of graphics primitives divided up. Basic elements are basic components of a Gra phikbildes, such as. B. Points, lines, vectors and polygons (e.g. triangles). Typically a hardware / software schema implemented to the graphics primitives that a Have view of one or more objects on one prepare two-dimensional display screen (or too to draw).

A host computer generally provides primitive data which are the basic elements of a three-dimensional object, the should be prepared. If the basic element for example, a triangle, the host computer can do that Triangle with respect to the x, y, z coordinates and the red, Green, blue color values (R, G, B color values) each vertex Define points. Processing hardware interpolates the primitive data to the display screen pixels form each primitive, and the R, G, B color values for to calculate each pixel.

The basic components of a typical computer graphics system  comprise a geometry accelerator, a rasterizer and a frame buffer. The system can also have another Hardware components such as B. texture mapping hardware (which will be described below). The geome drive accelerator receives a bit from the host computer tele coordinate and color data for the basic elements, the form an object. The geometry accelerator is typically with respect to the vertex coordinate data (i.e. with regard to the screen space coordinates) breaks down quadrilaterals into triangles and can have other functions, such as B. a brightness setting, a cut and performing level equation calculations for each Basic element, perform. The output signal from the geome drive accelerator, which is referred to as the preparation data signal the rasterizer (and optionally one Texture mapping hardware) used to final image screen space coordinates and RGB color values for each pixel form the basic elements to calculate. The end dates will be in the frame buffer for display on a display image screen saved. Some graphics systems have a pipe line structure on such that different operations (such as e.g. B. transformations, interpolations, etc.) simultaneously of different components with different ob basic elements are carried out.

Technically more sophisticated systems optionally offer a texture illustration, so that objects with an improved surface chendetail can be displayed. A texture map is a method that involves imaging a source image as Texture is referred to on a surface of a three-di dimensional object and then an image of the textu three-dimensional object on the two-dimensional len graphic display screen to achieve this to display the image. The texture mapping includes a ver turn one or more point elements (texels) of a tex structure for each point element (pixel) of the displayed Ab section of the object on which the texture is mapped. Texture mapping hardware subsystems typically include  a local memory that stores the texture data that assigned to the section of the object that is being processed are.

Graphics systems with pipeline structure, i. H. especially the those that provide data-intensive texture mapping len, usually have complex bus structures, on which to transfer data between the various components be averaged, often with regard to the system bandwidth a compromise is made. It is with these systems for example, it is common practice that data paths (buses) for certain data types and operations are reserved, where otherwise the paths remain unused. In the absence of such reserved paths, it may be necessary that a main preparation bus system with pipeline structure must to certain operations such. B. a download texture data from the host into a local texture map storage. The bus structure also includes which is common in systems that have multiple parallel-connected Chips have a separate bus for each of these Chips, which further reduces the system bandwidth.

The system bandwidth is directly related to the Sy stem behavior. Due to technical advances, Host processors are able to process the graphics processing chips the primitive data ready at increased speeds to deliver. To a bus structure to the improved technolo Aligning the host processors is a bus structure required that is able to handle data transfers to handle a wide range.

The object of the present invention is therefore to an improved bus structure and an improved data comm communication protocol for a computer graphics system with pipe create line structure, whereby the system bandwidth ma is maximized.

This object of the present invention is achieved by a bus  Connection system according to claim 1, by a method for Operating a graphics system according to claim 11 and by solved a graphics device according to claim 14.

According to one aspect of the invention, a bus connection comprises system for use in a graphics processing system stem containing a plurality of graphics processing elements has a bus structure that the graphics processing element elements in a ring. The bus structure includes one Plurality of individual buses, each of the individual Busse connects a pair of the graphics processing elements. Each of the individual buses includes an equal plurality of Signal lines for transmission of graphic command and In formation signals between the graphics processing elements in this ring.

According to another aspect of the invention, a gra phikvorrichtung a number of processing elements that are coupled via individual buses in a ring. Everyone who individual buses transmit an equal number of Signa len. Each of the processing elements includes a core process processing unit and an interface unit that Kop pelt are to command and information signals from one previous processing element in the ring on a of individual buses to receive and information on a second of the individual buses to a subsequent one Forward processing element in the ring.

According to a further aspect of the invention, a method provided for operating a graphics system in which the graphics system has a plurality of processing elements has, which are coupled in a ring. One of the processors Processing element is a host interface processing element ment that additionally with a host processor for receiving command and information signals for transmission is coupled to other processing elements in the ring. The method includes the steps of receiving at one of processing elements in the ring of graphics command  and information signals from a previous processing tion element in the ring and the forwarding of the receptions NEN graphic command and information signals to a next most processing element in the ring. In addition, the received graphic command and information signals to one Core processing unit of the processing element directs.

Preferred embodiments of the present invention are described below with reference to the accompanying Drawings explained in more detail. Show it:

Fig. 1-3 block diagrams of computer graphics systems with Pi peline structure using the bus architecture of the inven tion;

Fig. 4 is a block diagram illustrating a general embodiment of the bus architecture of the invention;

Fig. 5 is a timing diagram showing the operational phases of the system clock used in the invention;

Figure 6 is a more detailed block diagram of one of the interface circuits shown in Figure 4;

Fig. 7 is a timing diagram showing how address and data information can be clocked into various registers used in the interface circuit shown in Fig. 6;

Fig. 8 is a timing diagram rule the delay Zvi a time when an interface circuit whose buffered ready signal (Buffered_Ready signal) to an in-processing before directionally arranged processing element is disabled, and a time indicates when the arranged in the processing direction before proces beitungselement so stops sending data to the interface circuit;

Fig. 9 is a timing diagram illustrating the delay Zvi rule a time when an interface circuit whose Buffered_Ready signal to a previously arranged in the machine direction process ing element is again activated and a point in time indicates when the start in the machine direction in front of parent processing element so that, Gul to send data to the interface circuit;

Fig. 10 is a more detailed block diagram of the buffered and unbuffered write FIFOs shown in Fig. 6;

Fig. 11 is a timing diagram showing the relationship between various signals used to control the buffered and unbuffered write FIFOs shown in Fig. 10;

FIG. 12 is a more detailed block diagram of the buffered and unbuffered read FIFOs shown in FIG. 6, and FIG. 12 also shows how these FIFOs can operate when a processing element is configured in a redirection mode;

Figure 13 is a more detailed block diagram of the buffered and unbuffered read FIFOs shown in Figure 6, and Figure 13 shows how these FIFOs can operate when no processing element is configured in a redirection mode; and

To control Fig. 14 is a timing diagram illustrating the relationship between various signals that are used to the buffered and unbuffered Le se-FIFOs 12 and 13 in Fig..

1. System overview

FIGS. 1-3 are block diagrams showing men the different exemplary embodiments of Computergraphiksyste that use a bus architecture and a Datenübertra transmission protocol according to the present invention. Each system has a different number of components and consequently offers a different level of performance; two of the systems shown also offer an additional texture mapping feature. It should be apparent that the systems shown are exemplary and not limiting in any way, and that any data transmission system could use the bus architecture and data transmission protocol of the invention.

Fig. 1 shows the simplest of the three systems. As shown, the system includes a host computer 100 , an upstream subsystem 102, and a frame buffer subsystem 104 . The upstream subsystem 102 receives from host computer 100 via bus 101 the basic elements that are to be processed. The primitives are typically x, y, z coordinate data, RGB color data, and alpha blend data for each of the particular portions of the primitives, such as. B. specified for the triangle vertices.

Data representing the primitives in three dimensions, comprising from the upstream end subsystem 102 via a bus 122, the segments 122 A, 122 B and 122 C, supplied to the Rah menpufferteilsystem. The frame buffer subsystem 104 interpolates the rendering data received from the upstream subsystem 102 to calculate the pixels on the display screen that will represent each primitive and to determine the RGB color values of the resulting object for each pixel. RGB color control signals for each pixel are provided via RGB lines 123, respectively, to control the pixels of the display screen (not shown) to display a resultant image thereon.

In the exemplary embodiment shown in FIG. 1, the upstream subsystem 102 comprises a host interface 106 and a three-dimensional geometry accelerator (3D geometry accelerator) 110 . As noted, the host interface 106 receives the x, y, z coordinates and color primitive data over the bus 101 from the host computer 100 . The se data is supplied from the host interface 106 via a bus 108 to the geometry accelerator 110th The geometry accelerator 110 performs conventional geometry acceleration functions, which results in the preparation of the data for a display. These functions can include three-dimensional transformation, brightness adjustment, clipping, and perspective division operations, as well as plane equation generation that is performed in a floating point format. The conditioning data is provided from a geometry accelerator 110 via a bus 112 to the host interface 106 , which reformats the conditioning data, performs floating point to fixed point conversion and provides this data to the frame buffer subsystem 104 via the bus system 122 .

In this exemplary embodiment, the frame buffer subsystem 104 comprises two frame buffer controllers 114 A and 114 B, each of which has a synchronous graphics memory with random access (SGRAM; SGRAM = SGRAM = Synchronous Graphics Random Access Memory) 116 A and 116 B, as well as a digital-analogue Have converters for a random access memory (RAMDAC; RAMDAC = Random Access Memory Digital-to-Analog Converter) 120 . Both the frame buffer controllers 114 A and 114 B and the host interface 106 are connected to the bus system 122 . In this embodiment, the bus 122 comprises three buses 122 A, 122 B and 122 C, which are identical to each other. The bus architecture 122 and the associated data transmission protocol, which are discussed in more detail below, offer an improved bandwidth compared to architectures and protocols known in the art.

In the embodiment of FIG. 1, each frame buffer controller 114 A and 114 B receives conditioning data from the host interface 106 . Each frame buffer controller can control different, non-overlapping segments of the display screen. The frame buffer controls can interpolate the primitive data to calculate the screen pixel coordinates that represent the primitive and the corresponding object RGB color values for each pixel coordinate.

The resulting image video data, the control of the frame buffer 114 A and 114 B are generated which include the RGB values for each pixel, 116 A and 116 B may be stored in the corresponding SGRAMs. The video data can be read from the SGRAM chips into the frame buffer controllers, reformatted so that they can be handled by the RAMDAC 120 , and supplied to the RAMDAC. The RAMDAC 120 can in turn convert the digital color data to analog RGB color control signals for each pixel, which are provided via RGB lines 123 to control a screen display (not shown).

The host interface 106 can also communicate directly with the RAMDAC 120 via the video bus 124 . The system is preferably a system with a pipeline structure, such that the frame buffer subsystem 104 can process a first basic element, while the upstream subsystem 102 processes a (basic) subsequent basic element.

The bus system of the present invention can also be used in the graphics system shown in FIG. 2. The system shown in FIG. 2 corresponds to the system shown in FIG. 1, with the exception that: (1.) two 3D geo gear accelerators 110 A and 110 B are included in the upstream subsystem 102 , (2.) a texture mapping subsystem 130 is used, and (3.) the capacity of each SGRAM memory 116 A and 116 B has been increased. With the two geometry accelerators 110 A and 110 B, the basic element data are assigned to the geometry accelerators according to the data transmission protocol of the invention, which is described in more detail below.

A texture mapping subsystem 130 may be any subsystem that performs texture mapping operations and, in this exemplary embodiment, includes a texture mapping circuit 132 and an associated local cache 134 that stores a limited amount of texture data.

In this embodiment, bus 122 includes sections 122 A- 122 D. Texture mapping circuit 132 is connected to bus 122 between host interface 106 and frame buffer controller 114 A. During operation emp captures the texture mapping circuit 132, as both of the frame buffer control circuits 114 A and 114 B, basic element data on the bus 122 A. The data can x-, y-, z-Objektpixelkoordi naten, object-RGB color values and S, T -Texture map coordinates for at least one vertex, and include the plane equation of the base element (ie the triangle). The texture mapping circuit 132 may interpolate the x, y pixel coordinates and the S, T texture coordinates to calculate the resulting texture data for each pixel. The texture data for each pixel can be stored in cache 134 at any time. If this is done, the texture data is read from cache 134 . If the required texture data is not present in the cache 134 at this time, the required texture data is downloaded from the host computer in an efficient manner in accordance with the present invention, as will be described in more detail below, without this Clear the data preparation pipeline or a reserved texture data path is required.

The texture data for each pixel can be a texel bus 136 to each frame buffer controller 114 A and 114 B are supplied, in which the same from each frame buffer control on a pixel-by-pixel basis with the object R, G Farbwer th are combined.

It should be obvious that the upstream subsystem 102 , the frame buffer subsystem 104, and the texture mapping subsystem 130 may be any currently known subsystem or subsystems that were developed later. In addition, each of these subsystems preferably has a pipeline structure and processes several basic elements at the same time. For example, while the Tex turabbildungsteilsystem 130 and the frame buffer subsystem process 104 primitives previously provided by the vorgela siege subsystem 102 which is running ahead mounted subsystem 102 thus continues to process new primitives until the pipelines in these in processing thereafter arranged subsystems towards full will.

The bus architecture of the present invention is configured such that different types of graphics processing chips can be interchangeably arranged in the architecture. That is, each chip connected to bus 120 could have any graphics function, such as. B. perform a texture mapping, a frame buffer control or other of these functions.

Fig. 3 is a block diagram illustrating another execution shows a graphics system which uses the bus architecture of the present invention. In the system of FIG. 3, an upstream subsystem 102 comprises three 3D geo-accelerators 110 A, 110 B and 110 C; a frame buffer subsystem 104 comprises four frame buffer controllers 114 A- 114 D, each having an associated SGRAM memory 116 A- 116 D; and a texture mapping subsystem 130 includes two texture mapping circuits 132 and 133 , each having an associated cache 134 and 135 .

A host interface 106 , each of the texture mapping circuits 132 and 133 and each of the frame buffer controllers 114 A- 114 D are connected via bus segments 122 A-G of the bus architecture 122 of the present invention. A texel bus 137 connects the texture mapping circuit 133 to the frame buffer controllers 114 C and 114 D. The operation is the same as that described with reference to FIG. 2.

2. The bus connection system

Referring now to FIG. 4, a block diagram of a bus connection system 200 in accordance with the present invention is shown. The bus connection system that can be used to connect multiple graphics chips (e.g., frame buffer controllers) includes multiple processing elements 202 , 222, and 242 . The processing element 202 is via a PCI bus 201 (PCI = Peripheral Component Interconnect = Peripheriekompo nentenverbindung) interface with an external host device (not shown), for. B. connected to a PC. Each of the processing elements 202 , 222 and 242 preferably comprises an ASIC chip (ASIC = Application Specific Integrated Circuit = application-specific integrated circuit), the core of the same as any graphics processing device, such as. A frame buffer controller, a texture mapping device, etc., can be configured.

Examples of systems that could use bus interconnection network 200 are shown in FIGS. 1-3. In Fig. 1, a host interface, for example, 106 is connected via bus 101 to the host computer 100, the host interface 106 in a ring with the frame buffer controllers 114 A and 114 B is connected. Thus, in this example, processing element 202 ( FIG. 4) could correspond to host interface 106 ( FIG. 1), PCI bus 201 ( FIG. 4) could correspond to bus 101 ( FIG. 1), and processing elements 222 and 242 ( FIG. 4) could correspond to frame buffer controllers 114 A and 114 B ( FIG. 1), respectively.

As shown in FIG. 4, each of the processing elements 202 , 222 and 242 includes a core processor 204 , 224 and 244 , and an interface circuit 206 , 226 and 246 , respectively. The core processors of each processing element may match or differ, while interface circuits 206 , 226 and 246 are (preferably) identical. Between the core processors 204 , 224 and 244 and their associated interfaces 206 , 226 and 246 are several asynchronous FIFO buffers (FIFOs; FIFO = FIFO = first-in-first-out) 208 , 210 , 212 , 214 , 228 , 230 , 232 , 234 , 248 , 250 , 252 and 254 coupled. These asynchronous FIFOs provide buffered (ie non-priority) information paths and unbuffered (ie priority) information paths both from the interface circuits 206 , 226 and 246 to the core processors 204 , 224 and 244 as well as from the core processors 204 , 224 and 244 to the interface circuits 206 , 226 and 246 , respectively.

The difference between buffered (i.e. non-priori information) and unbuffered (i.e. priority) Information and the processing of each type of information between buffered (i.e. non-priority) and unpuffed fert (i.e. priority) information paths will follow each explained in more detail. At this point it should however, it should be obvious that two different In formation types using a shared Busses are transferred between the processing elements can. Each information package is (determined by setting ter bits in type field data that coincide with the same transferred) either as buffered (i.e. non- Priority) or unbuffered (i.e., priority) information  tion identified. After the information from one Interface circuit have been received, the Information identified as buffered information were adorned to a storage element that only puffed information (i.e. to a non-priority activity information storage element), wherein Informa ions that were identified as unbuffered to one Storage element that only contains unbuffered information (i.e. to a priority information storage element ment).

By controlling the interface circuits in the ring, so that unbuffered (i.e., priority) information always Take precedence over buffered (i.e. non-priority) In formations, but so that non-priority informat ons in an information path that is different from the unbuffered (i.e. Priority) information path is kept separate, who until the unbuffered (i.e., priority) information processed, there are clear advantages over Syste men provided where a pipeline route "cleared" must be done before priority information is given by the same can be forwarded.

It should be obvious that, although priority information mations are identified herein as "unbuffered" which the same nonetheless processed by information storage elements be, and the same as such actually in all mean meaning of the word "buffered". Nevertheless priority information is described here as unbuffered draws, since the same in terms of non-priority in formations are to a certain extent unbuffered.

In the following, reference is further made to FIG. 4. Using, for example, processing element 222 , a buffered write (FIFO) FIFO 228 (ie, a non-priority interface output memory element) is coupled between an interface circuit 226 and a core processor 224 to provide a buffered (ie, not -Priority-) provide information path from the interface circuit to the core processor. Accordingly is an unbuffered write FIFO (UW FIFO; UW = unbuffered write) 230 (ie, a priority interfaces output storage element) between the interface circuit 226 and coupled to the core processor 224 to a ungepuf ferten (ie, priority) information from the To provide interface circuitry to the core processor. In addition, a buffered read FIFO (BR-FIFO) 232 (ie, a non-priority interface input storage element) is coupled between the core processor 224 and the interface circuit 226 to provide a buffered (ie, non-priority) Provide information path between the core processor and the interface circuit. Finally, an unbuffered read (FIFO) 234 (ie, a priority interface input storage element) is coupled between the core processor 224 and the interface circuit 226 to provide unbuffered (ie, priority) information between them To provide core processor and the interface circuit. The arrangement and operation of the exemplary read and write FIFOs 228 , 230 , 232 and 234 are illustrated and described in more detail below.

The processing elements 202 , 222 and 242 are connected to one another by means of a unidirectional bus, which comprises the bus segments 250 , 252 and 254 . The bus segments 250 , 252 and 254 of the connection network 200 have an identical structure and an identical width. As illustrated, bus segments 250 , 252, and 254 connect processing elements 202 , 222, and 242 in a ring format, with bus segment 250 connecting processing elements 202 and 222 , bus segment 252 connecting processing elements 222 and 242 , and bus segment 254 the processing elements 242 and 202 connects. In this manner, information is passed from processing element 202 to processing element 222 , information from processing element 222 to processing element 242 , and information is returned from processing element 242 to processing element 202 .

Using the arrangement shown in FIG. 4, information can be exchanged between the external host device and the processing element 202 (via the PCI bus 201 ), with information being unidirectional from each of the processing elements 202 , 222 and 242 to the processing element that is the same in the ring follows, are passed on all around. This circumferential (circular) arrangement provides simple point-to-point connections between each adjacent pair of processing elements, such that it is only required that the output of each interface drive the input of the interface that follows it in the ring. Since each processing element only drives one load, signal integrity problems are minimized, as a result of which a high bus bandwidth can be obtained.

In addition, the Infor mations that transfer from one element to another are transmitted together with a clock signal. The need as such, system-wide clock synchronization ready is eliminated, adding additional Chen processing elements is achieved by only a new processing element is inserted into the ring. That means this transmission of the clock signal with the information mations allows the number of elements included in the bus is picked up, is actually unlimited, though the integrity of the clock signal naturally deteriorates tert when the number of processing elements in the ring is increased.

Consequently, the ring connection system according to the Er finding an increase in communication bandwidth with one Bus that has a reduced width. A high through sentence is achieved by providing information about the cut make the ring be forwarded quickly while it is  enables the core processors of each element Be missing asynchronously from the information transfer rate work. The signal routing and signal integrity problems are reduced because the bus width is reduced and only there is one load per bus. You can also use the clock signal with the information in the ring arrangement transfer is carried out without additional processing tion elements added to the ring network or from the same can be deleted without negative effects for the synchronization of the system occur. Due to the ge time that each processing element takes changes to extract information from the bus, this results Add additional processing elements in the Ring only added one additional clock cycle per tem processing element, creating a minimal additional Delay is caused.

3. The bus connection

Still referring to FIG. 4 is a function of the bus segments 250, 252 and 254 therein, information packets Zvi rule the processing elements 202, 222 and 242 carry over. According to one embodiment of the invention, a complete information package comprises two different sections, each section having 32 information bits. When the two sections of each information packet are transmitted, they are time-multiplexed, so that for each complete packet that is transmitted, 64 bits of information are actually transmitted between the processing elements. For example, a first section of an information packet could have a 32-bit address and a second section of the packet (which immediately follows the first section) could have a 32-bit data word. Furthermore, according to this exemplary embodiment, each section of each complete information packet has a 9-bit type data field which is assigned to it, this 9-bit type field being transmitted simultaneously with the information packet to which it is assigned.

Each of the bus segments 250 , 252 and 254 has 41 bus lines which are reserved for the transmission of information and type data. Using bus segment 250 , for example, bus line 250 F, which comprises 32 different bus lines, is reserved for the unidirectional transmission of 32 information bits between interface circuit 206 and interface circuit 226 , bus line 250 E, which comprises 9 different bus lines, for one unidirectional transmission of 9 type data bits between the interface circuit 206 and the interface circuit 226 is reserved. Consequently, during a single clock cycle, the bus lines 250 E and 250 F together are able to transfer 9 data type bits and 32 information bits between the processing elements 202 and 222 . Half packets of information and data types (ie 32 information bits and 9 data type bits) are preferably transmitted at a rate of at least 200 MHz.

As shown in FIG. 4, each of the bus segments 250 , 252 and 254 provides common signals between the processing elements that connect them. Again using the bus segment 250 , these signals include, for example, a clock signal (CLK; CLK = clock), which is transmitted via the bus line 250 A, a buffered information ready signal (B_Rdy; B_Rdy = buffered ready), which are transmitted via the bus line 250 B. is, and an unbuffered ready signal (U_Rdy; U_Rdy = un buffered ready), which is transmitted via the bus line 250 C, and a busy signal (busy = busy or busy), which is transmitted via the bus line 250 D, type field signals (Type [8: 0]), which will be transmitted via the bus lines 250 E, and information field signals (Info [31: 0]), which will be transmitted via the bus lines 250 F. The clock signals (CLK), type field signals (type [8: 0]) and information field signals (info [31: 0]) are transferred in a first downstream direction from one processing element (such as processing element 202 ) to the next Processing element (such as processing element 222 ) passed in the ring. The buffered information ready signals (B_Rdy) and the unbuffered information ready signals (U_Rdy) as well as the busy signals (Busy) are in a reverse direction (upward direction) from a second processing element (such as processing element 222 ) to a first processing element (such as e.g. processing element 202 ) is supplied in the ring. Two of these "reverse direction" signals, ie the B_Rdy and U_Rdy signals, are used to control the flow of information between the processing elements, as described in more detail below.

The busy signal is used to indicate whether any The chips on the bus are busy or not. A Register in the main processing element (Master Processing Element) that can be read by the host device, ver follows whether the chips are busy or not. To this Way, the host device can determine when it is in is able to perform certain operations that the processing relate to elements.

A significant advantage of the bus connection system 200 is its flexibility. That is, the bus connection system 200 can connect any number of processing elements without significant degradation in signal integrity or bandwidth since the clock signal, as noted above, is transmitted with the data and only one load is coupled to each source. Thus, the bus architecture of the invention allows optional processing elements to be added to perform functions such as. B. a texture mapping, image processing, a volume preparation, perform, or that standard processing elements such. As rasterizers or frame buffer control devices, for increased performance or functionality.

Another advantage provided by the bus structure is that by (time) multiple xen of two different 32-bit information words the number of pins required to get the se information between the processing elements swap half the number that is required would be if the information packets were not so multiplexed would. The speed of the bus, i. H. 200 MHz large enough that the multiplexing of the 32 address bits and 30th Data bits in the manner described above can be performed while it is still possible that the Gra phic device meets the performance requirements. Since the Pin reduction in general is a major factor is an ASIC design, provides the capability of the bus structure ture, the performance requirements with half the size number of pins that are used for an information transfer reserved to meet, a clear advantage versus systems that have a larger number of connection Use pens to transfer the same amount of information gene.

However, as the ASIC technology improves and the number of available pins increases, or if technological advances dictate the need for a faster data transfer rate, the 41-bit information path can easily be expanded in such a way that more pins for one Information transmission can be reserved, the bandwidth of the system can be increased accordingly. Furthermore, improvements in PC board technology and I / O pad designs will no doubt allow bus architecture 200 to run at higher frequencies.

As noted above, bus segments 250 , 252 and 254 are also unidirectional. Unidirectional buses generally provide a faster data transfer rate than bidirectional buses because there is no delay period associated with reversing the direction of the bus. Furthermore, since there is no need to provide and control both a send and a receive path, unidirectional bus structures are typically easier to manage and require simpler hardware.

4. The processing elements

As mentioned above, each of the processing elements of FIG. 4 includes a core processor (e.g., core processor 224 ), a series of write and read FIFOs (e.g. FIFOs 228 , 230 , 232 and 234 ) and an interface circuit ( for example, the interface circuit 226 ), wherein the core processors of the processing elements do not have to be identical, as was also mentioned above. For example, in the embodiment of FIG. 4, the core processor 204 of the processing element 202 includes a logic circuit for an interface connection to the host PCI bus, which does not have to be included in the other core processors. In the example of FIG. 4, processing element 202 is the main processing element in ring network 200 , and consequently, as previously mentioned, it could correspond to host interface 106 in FIGS . 1-3. As will be described in more detail below, the processing element 202 thus processes the input signal packets in a slightly different way than the other processing elements coupled in the ring.

The general functioning of each of the processing elements 202 , 222 and 242 is as follows with regard to the bus connection network 200. A primary clock signal is divided into two phases, ie a phase 1 (P1) and a phase 2 (P2). As mentioned above, the packets transmitted over the information lines (e.g. bus lines 250 F) may e.g. B. Multiplexed addresses / data information, each packet (in an exemplary embodiment) having 32 address information bits and 32 data information bits (for a total of 64 information bits per packet). Consequently, an address section of a packet can be transmitted via the information lines (for example the lines 250 F) during phase 1 (P1), and the associated data section of the packet can be transmitted via the information lines during phase 2 (P2).

At this point, however, it should be noted that a Information package is not necessarily an address package on which a data packet follows, must have, but any Combination of address and data information include can. For example, as in the following in Table II shows, an information packet can have a data packet sen, which is followed by another data packet if an Opera tion, such as B. a block transfer is performed. It should also be noted that an information package not multiplexed into two or more separate sections must be used, but alternatively as a single multi-bit package can be transferred without the intended Deviate scope of the invention.

Each information packet is received via a set of information lines (e.g., bus lines 250 F) from an interface circuit (e.g., interface circuit 226 ). All packets received by a processing element are forwarded to the core processor of that processing element (for example, the core processor 224 of the processing element 222 ) for processing. Each processing element has a unique base address associated with it, so that during a read operation, for example, five bits of an incoming address can be compared to the base address of the processing element to see if the packet is for that processing element.

Preferably, all identical processing element types will share or use a common base address. If a particular package does not affect a processing element, the core processor will simply drop the package. Otherwise the core processor will perform the function prescribed by the packet. For example, if the packet is a read packet, the core processor (e.g., core processor 224 ) the information read from its memory (after a slight delay) to the interface circuitry associated with it (e.g., interface circuitry 226) ), so that the interface circuit can forward the information to the downstream processing elements (for example to the processing element 242 ).

One reason that bus connection system 200 is capable of operating at a high frequency is that each interface circuit for each processing element (not main processing element 202 ) holds information for only a minimal amount of time before it goes to the next Processing element in the ring be forwarded. That is, as information is transferred to each of processing elements 222 and 242 , each of interface circuits 226 and 246, respectively, retrieves the information in an input register (not shown) during a first clock cycle and passes it to an output register (not shown) during a second clock cycle following the first clock cycle, the second clock cycle may be the next subsequent clock cycle, but need not be. Thus, in one embodiment, there is only one clock cycle latency caused by each of processing elements 226 and 246 . Consequently, all packets received by a processing element (not the main processing element 202 ) are forwarded through its interface circuit to the next processing element in the ring.

In contrast, the main processing element is configured to operate in a "rerouting mode" since it is the beginning and end of the ring connection. During the redirection mode, the interface circuit 206 operates as two different halves. An input half (including write FIFOs 208 and 210 ) receives all of the address / data information from the ring and redirects the information through core processor 204 , with an output half (including read FIFOs 212 and 214 ) of new address / data information from receives the core processor 204 and forwards this information to the next processing element in the ring. Thus, in the example shown in FIG. 4, all information received from interface circuit 206 (in main processing element 202 ) is entered into core element 204 , the information never directly from the input of interface 206 to the output thereof be forwarded, as is also the case with the interface circuits 226 and 246 . The output half is capable of receiving commands from the host processor (via the PCI bus), relaying or modifying those commands (or generating additional commands in response to them), and relaying these commands to the ring.

Although the redirection mode was previously described as if it were only for the main processing tion element is used, it is conceivable that diesel be for other processing elements in the ring as well Providing increased functionality can be. For example, the redirection mode used in further processing elements to allow these elements to perform functions such as Legs Image processing, perform. During an image processing device is generally data in a core processor leads, manipulates and leads out of the core processor. As a result, the data received by a core processor  will be caught (if the same goes through image processing leads), typically stored and processed in this way, that the latency time between the input and the output of the Data can be very long. In addition, the amount of data which is entered into the kernel is different from the amount of data distinguish that leaves it. Hence, by placing one or more of the processing elements image processing in the ring in the redirection mode processing by means of these processing elements without deterioration tion of the overall behavior of the ring.

The redirection mode can also be used, for example det to enable a processing element a digital video data stream to a video data processor transmission element that transmits in the processing direction the transmitting processing element is arranged. The or the processing elements that make up the digital videoda should always be in the direction of processing arranged in front of the video data processing element or elements be receiving the digital video data stream. To one to perform such function, the host device places the digital video data processing element in a diversion mode by using a redirection state hardware register (not shown) in the interface of the digital video over work element is described. On the connection should no further operations be performed after the video processing element in the redirection area drive mode was placed. After the video processing element was placed in the redirection mode, it can same writes to a memory or in overlay buffer, in image buffers or texture cache arrays in any of the downstream processing elements in generate the ring bus.

The redirection mode is enabled by setting a redirection state hardware flag on each interface circuit that is "to be redirected". Thus, in the example shown in FIG. 4, the redirection status hardware flag of interface circuit 206 is permanently set, while the redirection status hardware flags of interface circuits 226 and 246 may optionally be set.

Furthermore, since the main processing element 202 (in FIG. 4) initiates information packet communication in the ring network, it also provides the main clock signal which is passed on with the information. That is, in addition to configuring the main processing element 202 to operate in a redirection mode, it is also configured to operate in a "master mode". Regardless of whether the processing elements are configured or not to operate in a main mode, all processing elements receive an incoming clock signal (In_CLK) from an upstream processing element together with information from this processing element. This incoming clock signal In_CLK is used to clock the input circuitry of the interface circuits (described below). The processing elements, ie without the processing element 202 , which are not configured to operate in a main mode, also use the incoming clock signal In_CLK to clock the output circuitry of the interface circuit (which will be described below).

Since the interface circuit 206 is configured to operate in a main mode, it is controlled such that its output circuitry is utilizing a source clock signal (Src_CLK; Src_CLK) generated by the core processor 204 and not using the incoming clock signal (In_CLK) is clocked. The source clock signal Src_CLK from the core of a "main" processing element is thus forwarded together with the information from the core of this processing element to the next processing element in the ring. The manner in which either the source clock signal or the incoming clock signal is selected to provide timing for the output circuitry of an interface circuit (depending on whether it is configured to operate in a main mode or not), as well the generation of suitable timing signals therefrom is described in more detail below.

As mentioned above, the processing elements coupled to the main processing element generally do not operate in the redirection mode. Thus, for all non-main processing elements (e.g., processing elements 222 and 242 ), the routing of information from one processing element to another in the ring is largely controlled by the processing element's interface circuitry (e.g., interface circuits 226 and 246 ). For example, using non-main processing element 222 , core processor 224 receives, for example, information about asynchronous buffered write and unbuffered write FIFOs (BW, UW) 228 and 230 and routes information read from core processor 224 via asynchronous buffered Read and unbuffered read FIFOs (BR, UR) 232 and 234 continue to the output of interface circuit 226 . FIFOs 228 , 230 , 232, and 234 are referred to as "asynchronous" because buffered write and unbuffered write FIFOs (BW, UW) 228 and 230 receive information from interface circuit 226 , and buffered read and unbuffered read information (is the circuit from the interface 226 provided) -FIFOs (BR, UR) 232 and 234 under USAGE dung a first clock signal transmitted to the interface circuit 226, while the gepuf ferten write and unbuffered write FIFOs (BW, UW) 228 and 230 transmit information to the core processor 224 , and the buffered read and unbuffered read FIFOs (BR, UR) 232 and 234 using a second clock signal (provided by the core processor 224 ) that has a different frequency than that may have the first clock signal, receive information from the core processor 224 . Consequently, since the interface circuit 226 and the core processor 224 can operate at different frequencies, the use of asynchronous FIFOs 228 , 230 , 232 and 234 facilitates the transfer of information between the two devices.

For example, still using processing element 222 , in one embodiment, each of FIFOs 228 , 230 , 232, and 234 is capable of storing 82 bits (in parallel) per FIFO input. The reason for using both buffered FIFOs (ie, non-priority interface memory circuits) and unbuffered FIFOs (ie, priority interface memory circuits) in each of the write and read paths is described in more detail below. At this point, however, it should be noted that two different information paths, ie, a buffered (ie, a non-priority) information path and an unbuffered (ie, a priority) information path are provided in and out of the core processor 224 . In one embodiment, 41 of the 82 parallel bits that are stored each time buffered write and unbuffered write FIFOs (BW, UW) 228 and 230 are entered correspond to the 32 information bits and 9 type bits used during phase 1 (P1) of packet transmission, the other 41 bits corresponding to the 32 information bits and the 9 type bits received during phase 2 (P2) of the packet transmission. If a function, e.g. For example, if a write function requiring an address and data is performed, each buffer entry will include a 32-bit address, a 9-bit type field associated with the address, 32 data bits, and a 9-bit type field associated with the data (which is generally a duplicate of the type field associated with the address). In one embodiment of the invention, each of the buffered write and unbuffered write FIFOs (BW, UW) 228 and 230 should be at least five entries deep, with each of the read FIFOs being at least one entry deep. However, it should be apparent that the number of entries in each FIFO can be set as required by the core.

In one embodiment, the clock signal that is passed between each processing element is a 200 MHz clock signal. Each interface circuit (for example, the interface circuit 226 ) uses a two-phase clock system, each phase operating at half an external clock frequency, ie each phase operating at 100 MHz in this exemplary embodiment. In the following, reference is briefly made to FIG. 5. A timing diagram is shown which represents the relationship between the incoming system clock signal In_CLK (In_CLK = incoming clock) (from an upstream processing element) and the two clock phases Phase 1 (P1) and Phase 2 (P2), which are internal to each of the interface circuits be generated. It is noted that the operating phase (ie P1 or P2) changes for each falling edge of the incoming system clock signal In_CLK. For timing reasons, it may be desirable to use a complementary system clock signal and not the single phase clock signal shown in FIG. 5. For reasons of simplification, however, only a single-phase clock signal is described below.

As mentioned above, if it is not configured to operate in a main mode, a processing element transmits the incoming clock signal In_CLK as an outgoing clock signal (Out_CLK; Out_CLK = out going clock) which is transmitted with the outgoing information. Consequently, the internally generated phases P1 and P2 for the outgoing clock signal Out_CLK, if they are not configured in a main operating mode, will be identical to the internally generated phases P1 and P2 for the incoming clock signal In_CLK. However, if a processing element is configured to operate in a main mode, it will use a source clock signal Src_CLK from its core and not the incoming clock signal In_CLK to transfer data. Thus, when an interface circuit is in a main mode, it will transmit a source clock signal as its output clock Out_CLK, and to control the flow of outgoing information, it will create a two-phase clocking system (which also includes phases P1 and P2 ), which is similar to that shown in Fig. 5 (but is not identical).

Referring now to FIG. 6, a detailed block diagram of an interface circuit 226 is shown. In one embodiment, since the interface circuits of all processing elements in the ring are identical, it should be obvious that the following description of the interface circuit 226 applies to both the interface circuit 206 and 246. However, as noted above, the interface circuit 206 can generally only operate in a "rerouting mode" and a "main mode", which will make their operation a little different from that of the interface circuits 226 and 246 .

As shown in Fig. 6, data type and gemulti plexte Informatonspakete are simultaneously supplied to the input of the interface circuit 226 and gister in a Eingangsre 260 (ie, an input storage element) latched. The input register 260 can be included in the input pads of the interface circuit 226 or alternatively can be arranged externally on the interface circuit. As noted in the foregoing, the logic in the interface circuit 226 is clocked using a two-phase clock system. The incoming clock signal In_CLK is supplied to the input of a divide-by-two circuit 295 , the output signals, ie a write clock signal (Wr_CLK; Wr_CLK = write clock) and a phase 2 clock signal (P2_CLK), which is the inverse signal of the Wr_CLK signal and consequently has a high state during phase P2. The Wr_CLK and P2_CLK signals are used to control various registers in the interface logic as described below.

The incoming clock signal In_CLK is also supplied to an input of a multiplexer 299 . The multiplexer 299 also receives a source clock signal Src_CLK from the core processor 224 as a second input signal. When the interface circuit 224 is configured to operate in a main mode, the multiplexer 299 will select the source clock signal Src_CLK as its output signal and will provide the source clock signal Src_CLK as the output clock signal Out_CLK to the output of the interface circuit 226 . Conversely, if the interface circuit is not configured to operate in the main mode, the multiplexer 299 will select the input clock signal In_CLK as its output signal and provide the input clock signal In_CLK as the output clock signal Out_CLK.

The output of multiplexer 299 is also provided to the input of a divide-by-two circuit 297 which includes a read clock signal RD_CLK (RD_CLK) as well as a signal (not shown) which is the inverse of the RD_CLK signal and is used for an output control, at whose output provides. Accordingly, if the interface circuit 226 is not configured in the main mode, the write clock signal Wr_CLK and the read clock signal RD_CLK should be synchronous, both of which should be the inverse of P2_CLK. Conversely, when the interface circuit 226 is configured in the main mode, the read clock signal RD_CLK should only be driven by the source clock signal Src_CLK.

In one embodiment, the clock signals generated by the parts-by-two circuits 295 and 297 can be system-wide by switching the state of a single information bit on one of the information bus lines, e.g. B. Bit [31] of the bus lines 250 F (shown in Fig. 4), and by synchronizing the output signals of the parts-by-two circuits 295 and 297 with them.

By using a through path 261 , which is arranged (via multiplexers 270 and 282 ) between the input register 260 and an output register 300 (ie an output storage element), the interface circuit 226 is able to insert information packets (and type data) via their circuit arrangement into the Quickly forward output register 300 for transfer to the next processing element. Pass-through path 261 is used when backup path 290 (described below) is empty and downstream processing element (not shown) provides signal to interface circuit 226 indicating that it is currently in is able to receive information. However, if the downstream processing element indicates that it is unable to receive information, the information that would have been forwarded to the downstream element (if it was willing to receive the information) will be stored in information storage elements (e.g. Register) is stored in the backup information path 290 (described below). This saved information must be stored in the information storage elements of the backup information path 290 at least until the interface circuit 226 then stops receiving information from an upstream processing element (for example the processing element 202 in FIG. 4). The upstream processing element will cease to transmit this information by responding to the interface circuit 226 which provides a signal to the upstream processing element to instruct the processing element to stop transmitting information.

5. Communication protocol

In the embodiment described herein, as in  previously presented, the information pa kete transferred between the processing elements be two sections on. For example, the first Section have address information, the second Section data assigned to this address can. In addition, each of these two sections is one Information package assigned a type field. When executing Example, the type field comprises 9 bits and, as described in Table I is shown to be encoded as follows:

Table I

The type field is used to provide an instruction to each of the To provide processing elements regarding what to deal with the information that is concurrent with the same are received. Two type fields that ver are the register read and register write types fields. A register write is done in two steps ten carried out. First the address will be shown during the  Phase 1 (P1) sent over the bus, secondly during phase 2 (P2) data is sent. For register read forward the address is sent during phase 1 (P1), being the data field sent during phase 2 (P2) is unknown. After a short delay the data read from the core processor in the previously unknown data slot of the same register le se package and added to the next processing element forwarded in the ring.

Two other commonly used type fields are BIN read and BIN write instructions for reading and writing BIN type data (i.e. read and write information in spec fish buffers, e.g. B. overlay buffer, image buffer or texture cache arrangements) are provided. As another Type field option can use block transfer instructions to move large blocks of data between a source and a Transfer destination. For example, a big da tenblock from a host computer (via main processing tion element) to a downstream processing element using direct memory access techniques (DMA techniques; DMA = Direct memory access). In addition, you can Level equation statements included in the type field to provide level equation data to the registers for a 3D rendering. Eventually other type Use instructions (Misc; Misc = miscellaneous = other) det to implement special functions on the bus. For example, the Misc type statement could be used the one reading path before performing another ope to clear ration type.

As is evident from Table I, use a instructions together bits with common meanings. For example, bit <8 <of the type field is a "valid" bit, which is used to validate each of the Ab display sections of an information package. If the gül bit is a "0", the bits <7: 0 <of the type fields ignored. In addition, bit <3 <of the type field  typically used to identify whether a ge buffered (i.e. a non-priority) information path or an unbuffered (i.e., a priority) information path should be used to: (1.) information from the Transfer interface circuit to the core processor, (2.) Information from the core processor to the interface transmission, or (3.) information in the Backup information path (described above was) to keep. More details regarding buffered and unbuffered information channels are provided below poses.

As mentioned earlier, information is transmitted in multiplexed packets on the bus, one Half of every information packet during each phase of the Clock signal is transmitted. The following Table II summarizes the information gathered during phase 1 and 2 (P1 and P2) for the types of operations described above described and listed in Table I, transferred will:

Table II

Referring to FIGS . 4 and 6 (and again using, for example, processing element 222 ), as shown in Table II, the first portion of each packet of information from interface circuit 226 during phase P1 (on information lines 250 F ) received, with the second portion of each packet being received by interface circuit 226 during phase P2 (also on information lines 250 F). As shown in FIG. 6, the interface circuit 226 includes an input register 260 , a P1 register 262 , a P1WD register 264 and a P2WD register 266 . The input register 260 receives the incoming information packets (and their associated type data), the P1 register 262 receiving its input signal from the output of the input register 260 . In addition, the P1WD register 264 receives its input signal from the output of the P1 register 262 , the P2WD register receiving its input signal from the output of the input register 260 .

Reference is now made briefly to FIG. 7 below. A timing diagram is shown illustrating the receipt of various complete packets of information by interface circuit 226 . In particular, this timing diagram shows: (1.) the state of the arrival of the clock signal (In_CLK) that is received on the bus line 250 A, (2.) the information (Info [31: 0)) that is on the bus lines 250 F (3.) the write clock signal (Wr_CLK), which is output from the divide-by-two circuit 295 , and (4.) the content of the input register 260 (IN_Reg; IN_Reg = input register), the P1 Register 262 (P1_Reg) and the P1WD and P2WD registers 264 and 266 (P1- / P2WD). The states of the previous signals are shown over a series of transmission cycles T0-T3, where for each of the transmission cycles T0-T3 comprises a first phase P1 and a second phase P2. These signals are shown on the same time scale (horizontal axis) for comparison. Placing one signal over another does not indicate that one signal has a greater amplitude than the other signals.

Because one embodiment of the invention described herein is implemented using ASIC circuits as the processing elements, control of the "next state" content of each of the individual information storage elements shown in FIG. 6 (ie, like the content of the information storage elements during the next clocked state), as well as the control of the information flow via the various multiplexers using a software simulation language, such as, for. B. Verilog, are implemented, and then by means of a synthesis tool such. B. Synopsys ™, which works on a general-purpose processor, can be converted into a logic gate circuit. The logical functions can alternatively be written in a software program and carried out by a processor.

As shown in FIG. 7, an output register of an upstream processing element, for example, forwards an address ADR1 (ie an address section of a first information packet) via the bus lines 250 F during the phase P1 of the transmission cycle T1. During phase P2 of the transmission cycle T1, the falling edge of the incoming clock signal In_CLK latches the ADR1 (address 1) into the input register 260 of the interface circuit 226 . During phase P1 at time T2, the falling edge of the incoming clock signal In_CLK latches the data section DATA1 of the first information packet into the input register 260 . This leaves input register 260 and interface circuit 226 free to receive ADR2 from an upstream processing element during the next falling edge of the incoming clock signal In_CLK (ie during phase 2 (P2) at time T2). The type data is received by the interface circuit 226 (from the bus lines 250 E) in an identical manner. As a result, information and type data are received by the interface circuit 226 at the frequency of the incoming clock signal In_CLK, ie at approximately 200 MHz.

In order to demultiplex the two sections of each information packet into a parallel 82-bit word (to be forwarded to core processor 224 ), phase P1 register 262 is provided. When the information (and associated type fields) is received by the interface circuit 226 , as previously described, the P1 register 262 is controlled by a half-frequency clock signal Wr_CLK to latch only the first portion of each information packet. Further, the P1 / P2WD registers / control 264 266 (for forwarding information to the core processor 224) from the clock signal (which is the inverse signal of the clock signal at half the frequency WR_CLK) half Fre quency P2_CLK to simultaneously both sections of each Latche information packs.

In particular, during the rising edge of the half frequency clock signal Wr_CLK, the content of input register 260 is latched into P1 register 262 , while during the rising edge of the half frequency clock signal P2_CLK (which is the falling edge of Wr_CLK) the content of P1 register 262 is latched into P1WD register 264 and the content of input register 260 is latched into P2WD register 266 . Thus, the P1 / P2WD registers 264 and 266 store the first and second portions of an information packet after the rising edge of a P2_CLK signal, respectively. During any point in time before the next rising edge of the P2_CLK signal (e.g., during the rising edge of the next Wr_CLK signal), the information in the P1 / P2WD registers is either buffered in the asynchronous (i.e. non- Priority) write FIFO (BW) 228 or the asynchronous unbuffered (ie the priority) write FIFO (UW) 230 loaded, ie depending on the values of certain bits in the type fields assigned to the packet, as described in the following will be explained in more detail. There is no filtering of the address / data and type information provided by the interface. Thus, each packet of information received at the interface is forwarded to the core processor 224 , which determines whether that packet is of interest or not.

In the following, reference is again made to FIG. 6. All incoming multiplexed information packets are received by the input register 260 during each falling edge of the incoming clock signal In_CLK (as noted above), with the information either from: (1.) the input register 260 (via pass 261 ), (2. ) the fuse information path 290 or (3.) the buffered read or unbuffered read FIFOs (BR, UR) 232 or 234 into the output register 300 (via one or more of the multiplexers 270 , 282 and 280 ) during the falling edges of the output clock signal Out_CLK (which corresponds to the input clock signal In_CLK when the processing element is not in the main configuration) are clocked. Thus, input register 260 and output register 300 , if not configured in the main mode, receive and transmit information during each falling edge of the input clock signal In_CLK, that is, during both the P1 and P2 transfer cycles. Since the information packets are multiplexed into two sections (e.g. an address section and a data section), the input register 260 actually receives the first section of each information packet, e.g. the address information, during the falling edge of the input clock signal In_CLK during the P2 operating phase, and that second portion of the information packet, for example the data information, during the falling edge of the input clock signal In_CLK during a P1 operating phase (which immediately follows the P2 phase, during which the address was clocked into the register 260 ). Accordingly, the first portion of each information packet, which is transmitted by the interface circuit 226 , is switched on by means of a falling edge of the output clock signal Out_CLK (which corresponds to the input clock signal In_CLK when the processing element is not in the main configuration) during a P1 operating phase the output register 300 is clocked, the second portion of each transmitted information packet being dropped by a falling edge of the output clock signal Out_CLK during a P2 phase of operation (which immediately follows the P1 phase, during which the first portion of the packet was clocked into the register 300 ) the output register 300 is clocked.

If the processing element that is downstream from the processing element 222 (e.g., management, the Verarbeitungsele 242), indicating that it is able to receive information from the processing element 222, and the Ver processing element 222 itself is not delayed (Example instance, when the same waiting for read information from its core processor), the output register 300 information is received directly from the input register 260 (through passageway 261 ) so that a portion of an information packet (and its associated type data) during each falling edge of the input clock signal In_CLK is shifted via the interface circuit 226 , the latency of only a single clock cycle being caused as a result of the presence of the interface circuit.

6. Security information channels

If the processing element that is downstream from the processing element 222 (e.g., the Verarbeitungsele element 242) indicates that the same current is not able to catch information from the processing element 222 to emp, or if the processing element 222 is itself hesitates ver (for example, if it is waiting for read information from its core), the information storage elements in the backup information path 290 (described below) are used to store information that has been saved in the interface circuit 226 while the processing element (e.g. processing element 202 ) that is downstream from the processing element 222 still sends data, ie, until the vorgela crop processing element 202 to an indication from the Ver processing element 222 responds that the same is not currently able to accept information. That is, this securing function is carried out at least until the interface circuit 226 is able to signal the upstream processing element (for example the processing element 202 ) in order to stop sending information.

As shown in FIG. 6, backup information path 290 includes a buffered (ie, non-priority) information backup path 292 and an unbuffered (ie, priority) information backup path 294 . The buffered information backup path 292 in turn comprises buffered (ie non-priority) backup path storage elements B0, B1, B2, B3, B4 and B5, the unbuffered information backup path 294 unbuffered (ie priority) backup storage elements U0, U1, U2, U3, U4 and U5 includes. Furthermore, the backup information path 290 includes multiplexers 292 A and 292 B, which in one embodiment are arranged to transfer the content of only one (or none) of the buffered backup path storage elements B4 and B5 and the unbuffered backup path storage elements U4 and U5 to one of the inputs of the multiplexer 270 to deliver, to which the outputs of the multiplexers 292 A and 292 B are connected.

Further, in Fig. 6 is a B_Rdy register (B_Rdy = buffered ready) 322, a U_Rdy register (U_Rdy = unbuffered ready) 324, a B_Rdy logic circuit 326 and a logic circuit shown U_Rdy 328th The B_Rdy register 322 receives an incoming buffered ready signal (B_Rdy_In) from a downstream processing element (via the B_Rdy logic circuit 326 ), and supplies an outgoing buffered ready signal (B_Rdy_Out) to an upstream processing element. Accordingly, the U_Rdy register 324 receives an incoming unbuffered ready signal (U_Rdy_In) from a downstream processing element (via the U_Rdy logic circuit 328 ), and delivers an outgoing unbuffered ready signal (U_Rdy_Out) to an upstream processing element. The B_Rdy and U_Rdy logic circuits 326 and 328 receive, in addition to the incoming B_Rdy_In and U_Rdy_In signals, a number of other input signals, any of which may indicate that the processing element 222 is currently unable to receive information from one Processing element upstream 45518 00070 552 001000280000000200012000285914540700040 0002019816153 00004 45399gen. Each of the B_Rdy and U_Rdy registers 322 and 324 is clocked during the rising edge of the Wr_CLK signal.

The downstream processing elements signal the upstream processing elements to stop the transmission of information by simply their outgoing buffered ready signals (B_Rdy_Out) (for example on bus line 250 B) or their outgoing unbuffered ready signals (U_Rdy_Out) (for example on bus line 250 C) upstream element can be deactivated. The B_Rdy_Out and U_Rdy_Out signals indicate the respective ability of the processing element 222 to receive buffered (ie non-priority) information and unbuffered (ie priority) information. Further explanations regarding the use and control of buffered and unbuffered information are presented in detail below.

The backup information path 290 in FIG. 6 includes three buffering levels in each of its buffered and unbuffered information paths 292 and 294 to accommodate the maximum amount of information that could be saved, for example, between the time the interface circuit 226 first received an incoming deactivated B_Rdy_In signal receives from the downstream interface circuit 246, and to receive the time at which the interface circuit 226 actually ceases so that information from one of the storage-th interface circuit 206 (after the interface circuit 226 whose outgoing buffered be readiness signal B_Rdy_Out circuit to the upstream section has disabled 206).

The receipt of either the incoming B_Rdy_In or U_Rdy_In signal by the interface circuit 226 (from a downstream processing element) will cause the interface circuit 226 to transmit information of the identified type (ie, either buffered or unbuffered information) to the downstream processing element stops and stores any pending information as well as any information in reserved (given) buffers included in the backup information path 290 , which during the period between when the interface circuit 226 received its outgoing B_Rdy_Out or U_Rdy_Out signal ( to an upstream processing element), and the time when the upstream processing element actually stops sending information of the identified type. Consequently, the receipt of a deactivated incoming B_Rdy_In or U_Rdy_In signal is an indication that the processing element receiving the signal should stop (as soon as possible) from sending information and type data on its bus lines for outgoing information and type data .

Once the interface circuit 226, a disabled B_Rdy_In- or U_Rdy_In signal receiving processing element of a downstream Ver, the same their information transmission only stop after it thus is fer kind, any complete package of information to be transmitted, the transmission had already begun when the same received the signal. Thus, for example, if interface circuit 226 receives a disabled B_Rdy_In signal from interface circuit 246 just after an address (associated with a non-priority operation) has been clocked into output register 300 , interface circuit 226 will continue to process the data portion of the information packet (which is associated with the previously sent address) to be clocked before the information transfer to the downstream processing element 246 is stopped.

It is noted that the information transferred to backup path 290 is also latched into P1WD register 264 and P2WD register 266 and sent to either buffered write FIFO (BW) 221 or unbuffered write FIFO ( UW) 230 (depending on whether the information is buffered or unbuffered) are transmitted so that even the "saved" information will reach the core 224 (in the event that the information relates to the core).

For simplicity, the description below will only refer to the use and effects of the B_Rdy_In and B_Rdy_Out signals and the use of the buffered backup information pathway 292 , although it should be obvious that the methods used for temporary storage of saved information be used for both buffered and unbuffered information are identical.

When information (and type data) is transferred into the buffered backup path 292 , it is first written into the registers B4 and B5. As soon as registers B4 and B5 are full, incoming information (and type data) is then written into registers B2 and B3. When registers B2 and B3 are full, the incoming information (and type data) is finally written to registers B0 and B1. When the information (and type data) is transferred into the buffered backup path 292 , the information (and type data) from the P1 register 262 is additionally always written into one of the registers B0, B2 or B4, the information from the on Gang register 260 are always written in one of the registers B1, B3 or B5. Although the information transmitting paths from the P1 register 262 cherelementen to the buffered Sicherungsspei B2 and B4, and from, the input register 260 to the buffered backup storage elements B3 and B5 are not explicitly shown in FIG. 6 are shown, it should be open view Lich be that this information transmission paths present nonetheless and that the inputs to the buffered backup path 292 are intended to represent inputs to each pair of buffered backup memory elements (ie, B0 and B1, B2 and B3, and B4 and B5) in the buffered backup path 292 .

The information (and type data) is always read out of registers B4 and B5 in reverse of how the buffered save path 292 is filled when the buffered save path 292 is emptied. If registers B4 and B5 are empty, the contents of registers B2 and B3 (if available) are also moved to registers B4 and B5, where the contents of registers B0 and B1 (if available) are moved to registers B2 and B5. B3 is postponed.

As noted above, software designed / hardware implemented logic can be used to control the content of the next stage of each of the registers used in the invention. In one embodiment, instead of checking the content of each of the individual registers in the backup information path 290 that contains type data, as well as the individual type data register in the P2 register 262 , to determine what information is at which position during the next clock cycle who should be transferred in the circuit using a series of separate single-bit registers (ie, content-identifying memory elements), for example registers 302 , 304 , 306 , 308 , 310 , 312 and 314 , which are included in control register block 320 to track what type of information exists in which positions in the backup information path 290 , as well as to track what type of information exists in the P1 register 262 . For example: (1.) the single register 302 can be used to indicate whether the buffered save registers B4 and B5 are full, (2.) the single register 304 can be used to indicate whether the buffered save registers B2 and B3 are full , (3.) the single register 306 can be used to indicate whether the buffered save registers B0 and B1 are full, (4.) the single register 308 can be used to indicate whether the buffered save register B0 information of another type stored in the same, (5.) the single register 310 can be used to indicate whether the buffered save register B2 has information of any other type stored therein, (6.) the single register 312 may be used to indicate whether the buffered save register B4 has any other type of information stored therein, and (7.) the single register 314 may use to indicate whether the P1 register 262 has any other type of buffered information stored therein. The use of a single bit register simplifies the control of the circuit and enables the circuit to operate at a higher speed that would otherwise not be possible for operation.

Corresponding registers (not shown) may also be provided in the control register block 320 to indicate whether each of the save registers B0, B2 and B4, like the P1 register 262, has other specific types of information stored therein, such as e.g. B. an address that matches the base address of the core of this processing element, an address of a BIN read packet or a block transfer packet (BltOb) as defined in Table I above. Corresponding information is also stored in the additional single bit registers (not shown) in the control register block 320 (ie in content-identifying memory elements) to store the contents of the unbuffered (ie priority) save memory elements, e.g. the registers, in the unbuffered save path 294 are included. In addition, the "type-identifying" single bit registers (not shown) in the control register block 320 are used to identify whether the P1 register 262 contains certain types of buffered information, e.g., buffered BltOb information, and then uses the same. to identify whether it contains certain types of unbuffered information, such as unbuffered BltOb information.

The B_Rdy_Out signal has two states; d. H. one activated state, which indicates that the processing element ment that transmits the B_Rdy_Out signal is available to Record information and a non-activated To stood, which indicates that the processing element is not ver is available to include information. When executing Example, the activated state corresponds to a logi "1", the deactivated state of a logical Corresponds to "0".

In addition to having a processing element disable its B_Rdy_Out signal to an upstream processing element in response to receiving a deactivated incoming B_Rdy_In signal from a downstream processing element, a processing element may not be able to do so for a variety of other reasons. To record information. For example, if the buffered write FIFO (BW) 228 (ie, a non-priority information storage element) fills up within a certain number of entries (as explained in more detail below), the B_Rdy logic circuit 326 will cause that outgoing B_Rdy_Out signal (during the next Wr_CLK clock) is deactivated in order to prevent the upstream processing element from transmitting information, thereby ensuring that no information entered is lost since the interface circuit 226 can not receive any further information . Furthermore, during a core read operation, if no readings already exist (for example, due to a prefetch operation = pre-fetch operation), the B_Rdy logic circuit 326 will cause the outgoing B_Rdy_Out signal (during the next Wr_CLK clock) is deactivated when an incoming information packet is encoded to perform a read operation from the core 224 . This read operation may include reading one or more core registers or reading a memory element (such as a frame buffer) coupled to the core.

When a read packet (e.g., a register read packet) is received when there is no prefetched data, processing element 222 receives an indication that it should stop (as soon as possible) information and send type data to the downstream processing element. That is, a read packet received by processing element 222 provides an indication that processing element 222 (in addition to signaling to upstream processing element to stop sending information) is presently (as soon as possible) with it should stop sending information and type data to the downstream processing element insofar as the processing element 222 has to wait for information to be read from its kernel before this information (which is multiplexed with the previously received address) is stored on the downstream one Processing element can be transferred.

As mentioned above, when a readout of core data is requested, a small delay period occurs and core processor 224 is accessed before the read data is sent back. The data is read from the core via either the buffered read FIFO (BR) 232 (ie, via a non-priority interface input memory element) or the unbuffered read FIFO (UR) 234 (ie, via a priority interface input memory element), whereby this depends on whether the data is buffered or unbuffered, as explained below. The data from these FIFOs are then read into one of four information holding registers, ie into the information holding registers P1_OUT, P2_OUT, U_P1_OUT and U_P2_OUT ( 272 , 274 , 276 and 278 ). For the sake of simplicity, only the reading of buffered data is described again below, although it should be obvious that the reading of unbuffered data is carried out in the same way (although different registers are used).

During the delay period, when the core processor 224 is accessed, the address of the read is stored in an information storage element within the backup information path 290 , with the processing element 224 deactivating its outgoing B_Rdy_Out signal on the bus line 250 B to the upstream processing element to signal to stop sending information. When the data is sent back from the core processor 224 , it propagates through the buffered read FIFO (BR) 232 and is stored in the P2_OUT register 274 . Once the retrieved data is stored in the P2_OUT register 274 , the B_Rdy_Out signal is reactivated (indicating that the upstream processing element is allowed to send information again), with the address corresponding to the read being through the multiplexers 292 A, 270 and 282 are forwarded and output during the rising edge of the next P2_CLK signal. The recovered data is then output (after passing multiplexers 280 and 282 ) during the rising edge of the next RD_CLK signal. Thus, when a core read is performed, the B_Rdy_Out signal can be used to temporarily stop the upstream processing elements until the read data is available. Thus, after the core read is performed, the address and data retrieved from that address can be transferred synchronously with a delay period determined (essentially) only by the delay associated with the core read operation.

Referring now to FIG. 8, a timing diagram is presented that illustrates the latency that occurs between the time when the outgoing B_Rdy_Out signal is deactivated by processing element 222 after it has received a core read packet, for example, and the time when the processing element 222 actually stops receiving information from an upstream processing element (e.g., processing element 202 ). These signals are shown for comparison on the same time scale (horizontal axis). The arrangement of one signal over another does not indicate that one signal has a greater amplitude than the other signals.

As shown, address and data information is received on bus lines 250 F during phase 1 (P1) and phase 2 (P2) of each transmission cycle. If the type information assigned to an address sent during the phase P1 of the transmission cycle T1 indicates that a core reading operation is to be carried out, the B_Rdy_Out signal is then deactivated during the phase P2 of the transmission cycle ses T1. As it is indicated by the high state of the bit <8 <of the type field (ie the validity signal), valid address and data information is continuously received on the bus lines 250 F until the end of the transmission cycle T2. The time delay between the time when the B_Rdy_Out signal is deactivated during the transfer cycle T1 and the time when the transmission of information on the bus stops during the transfer cycle T2 results in a backup of the information on the processing element 222 .

Referring now to FIG. 9 is a corresponding tarry tion between the time when the B_Rdy_Out signal is again activated by the processing element 222, and if the processing element 222 receives return valid information from an upstream processing element (for example, the processing element 202) the time , represents. These signals are shown for comparison in the same time scale (horizontal axis). The arrangement of a signal over another signal does not indicate that one signal has a higher amplitude than the other signals. This time delay enables information in the backup information path 290 to be forwarded from the output register 300 before new information is received by the input register 260 of the interface circuit 226 .

In the following, reference is again made to FIG. 6. The operation of interface circuit 226 after it has received an incoming B_Rdy_In signal (from a downstream processing element) that has been deactivated will now be described. A first section of an incoming information packet (e.g., address and address type information) is received at the input of input register 260 during phase P1 of a transmission cycle. During phase P2 of the same transmission cycle, the first section of the information packet is entered into the input register 260 latched. During phase P1 of the next transmission cycle, the information stored in input register 260 is loaded into P1 register 262 , while a second portion of the information packet (e.g., data and data type information) is loaded into input register 260 . Both sections of information are then forwarded to the first stage of the buffered backup path 292 (ie to the registers B4 and B5) during the subsequent P2 clock phase. The information continues to be transferred from P1 register 262 and input register 260 into subsequent registers (ie, buffered backup memory elements) in buffered backup path 292 (during the subsequent P2 clock phases) until the upstream processor in response to interface circuit 226 which it deactivated from outgoing B_Rdy_Out signal, stops transmission.

When interface circuit 226 is again ready to receive and / or send information, its outgoing B_Rdy_Out signal is activated, and the process of flushing the registers in buffered save path 292 begins. During phase 1 (P1) of the first transmission cycle, after the outgoing B_Rdy_Out signal has been activated again, the information from register B4 is passed on via multiplexers 292 A, 270 and 282 and latched into output register 300 . During phase 2 (P2) of the same transmission cycle, information from register B5 is forwarded via multiplexers 292 A, 270 and 282 and latched into output register 300 .

During phase 1 (P1) and phase 2 (P2) of the second transmission cycle, the information from registers B4 and B5, which (if present) has been shifted from registers B2 and B3, are forwarded to output register 300 . Next, during phase 1 (P1) of the third transfer cycle, the information from register B4, which (if any) during the first transfer cycle from register B0 into register B2 and during the second transfer cycle from register B2 into register B4 have been forwarded via the multiplexer to the output register 300 . Furthermore, during phase 1 (P1) of the third transmission cycle, an upstream processing element (for example processing element 202 ) supplies a first section of an information packet to bus 250 . Thus, during phase 2 (P2) of the third transfer cycle, the first portion of the information packet from the upstream processing element is latched into register 260 , while the information from register B5, which (if any) during the first transfer cycle from register B1 into register B3 and during the second transfer cycle from register B3 to register B5 have been latched into output register 300 , thereby clearing buffered save path 292 .

Finally, during phase 1 (P1) of the fourth transfer cycle, the second section of the information packet can be latched from the upstream processing element into the input register 260 at the same time as the first section of the information packet (that previously latched into the input register 260 ) was) can be forwarded directly to the output register 300 via the through path 261 . Because the buffered backup path 292 is sized to accommodate the maximum amount of information that may be saved therein, no information is lost when a processing element stops operating while maintaining a very fast communication throughput.

7. The buffered and unbuffered information paths

Reference is further made to FIG. 6 below. As explained above, the first and second portions of each incoming information packet (as well as its associated type field) are latched into the P1 register 262 and the input register 260 (ie, an input storage element) before being put into the P2WD register, respectively 266 and the P1WD register 264 latched and forwarded to the core processor 224 of the processing element 222 who the. Both sections of each packet of information that are latched into P1WD and P2WD registers 264 and 266 are either written to buffered write FIFO (BW) 228 (ie, non-priority) depending on the content of the type field of the first section of the packet. Interface output storage element) or the unbuffered write FIFO (UW) 230 (ie the priority interface output storage element) is given. That is, the type field of the first section of the packet, that is, the section stored in P1 register 262 , is checked to determine whether the packet is identified as buffered or unbuffered according to the listings in Table I.

As shown in Table I, if the bit <7 <of this type field is a "1", the packet should always be transferred to the buffered write FIFO (BW) 228 , and if the bit <7 < is a "0", depending on the value of bit <3 <of the type field, whether the packet will be transferred to the buffered write FIFO (BW) 228 or the unbuffered write FIFO (UW) 230 . If the bit <3 <of the type field of the first section of a packet is a "1", the information is unbuffered in an exemplary embodiment, and vice versa, if the bit <3 <is a "0", the information is buffered .

In one embodiment, the content of the type field of P1 register 262 is not checked to determine whether it contains buffered or unbuffered information, but two separate single-bit registers (e.g., registers 316 and 318 in control register block 320 ) are used to track whether P1 register 262 currently contains buffered or unbuffered information. For example, register 316 can be used to indicate whether P1 register 262 currently contains buffered information, and register 318 can be used to indicate whether P1 register 262 currently contains unbuffered information. The next state content of each of registers 316 and 318 can be determined by checking the type field of information stored in input register 260 so that P1 register 262 receives input information, register 316 and 318 input signals are received that correspond to the type of information input signal to P1 register 262 during the same clock phase.

Buffered write FIFO (BW) 228 and unbuffered write FIFO (UW) 230 are shown in greater detail in FIG. 10. As shown, in one embodiment, each of the buffered write and unbuffered write FIFOs (BW, UW) 228 and 230 includes eight entries to store each of the two sections of an information packet. That is, each of the buffered write and unbuffered write FIFOs (BW, UW) 228 and 230 includes eight entries to store the following: (1.) Phase 1 information and type data (P1_WrInfo and P1_WrType) from the P1WD register 264 , and (2.) phase 2 information and type data (P2_WrInfo and P2_WrType) from the P1WD register 266 . The FIFO 228 further includes a charge control circuit 227 and a discharge control circuit 229 , and the unbuffered write FIFO (UW) 230 further includes a charge control circuit 231 and a discharge control circuit 233 .

In the following, reference is briefly made to FIG. 11. A timing diagram is shown showing the relationship between the incoming clock signal In_CLK, the write clock signal Wr_CLK from the divide-by-two circuit 295 (shown in FIG. 6) and the P1_WrInfo and P2_WrInfo signal (ie Information written to FIFO 228 or 230 from registers 264 and 266 ). These signals are shown for comparison in the same time scale (horizontal axis). The arrangement of a signal over another signal does not indicate that a signal has a higher amplitude than the other signals. As shown in Fig. 10, each of the charge control circuits 227 and 231 receives the Wr_CLK signal as a clock input signal. The load control circuit 227 also receives a buffered information load signal (B_WrInfoLd) that is a result of the type bit check explained above to identify whether the information is buffered or unbuffered. Load control circuit 227 provides a buffered full write signal (B_WrFull) which is activated when buffered write FIFO (BW) 228 is full to four or fewer entries and which is deactivated when buffered write FIFO (BW) 228 has five or more entries that can be filled. Accordingly, the load control circuit 231 receives an unbuffered information load signal (U_WrInfoLd), which is also a result of the type bit check explained above to identify whether the information is buffered or unbuffered. The charge control circuit 231 provides an unbuffered write full signal (U_WrFull) which is activated when the unbuffered write FIFO (UW) 230 is full to four or fewer entries and which is deactivated when the unbuffered write (UW ) FIFO 230 has five or more entries that can be filled.

Each of the discharge control circuits 229 and 233 also receives a respective core clock signal and a discharge signal from the core (which enables the core to discharge information from the FIFOs at the core clock rate when one of the discharge signals is activated) and provides a respective idle signal to the kernel (which indicates to the kernel that the FIFO currently has no information stored therein). Consequently, the core can access the P1 and P2 information and type data (P1_Info, P1_Type, P2_Info and P2_Type) from either the buffered write or the unbuffered write FIFO (BW, UW) 228 or 230 with one rate, which is asynchronous to the clock rate at which these FIFOs receive the information and type data from the interface circuit 226 .

In Figs. 12 and 13, the asynchronous buffered read and unbuffered read FIFOs (BR, UR) are shown detail profiled 232 and 234. FIG. 12 shows how buffered read and unbuffered read FIFOs (BR, UR) 232 and 234 could operate when processing element 222 is configured in a redirection mode, FIG. 13 showing how buffered read and unbuffered read FIFOs (BR, UR) 232 and 234 could operate if the processing element is not configured in the redirection mode (such as the configuration shown in FIG. 6). First, reference is made to FIG . When processing element 222 is configured in a redirection mode, one of the buffered read and unbuffered read FIFOs (BR, UR) 232 and 234 that is selected receives both sections of an information packet (ie, phase 1 information (P1_Info ) and type data (P1_Type) and phase 2 information (P2_Info) and type data (P2_Type)) from the core together with a core clock signal and a load signal, and delivers a "full" signal to the core around the core indicate when each of the FIFOs is full. In the example shown, both the buffered read and unbuffered read FIFO (BR, UR) 232 and 234 are eight entries deep, however, the necessary depth of the read FIFOs is determined by the operations performed by the core should.

As shown in Figure 12, the buffered read FIFO (BR) 232 provides both portions of a buffered information packet (ie, phase 1 output information (P1_OutInfo) and type data (P1_OutType) and phase 2 output information (P2_OutInfo) and Type data (P2_OutType)) to the interface circuit 226 . In particular, the phase 1 output information P1_OutInfo and type data P1_OutType are supplied to the P1_Out register 272 , the phase 2 output information P2_OutInfo and type data P2_OutType being supplied to the P2_Out register 274 . Accordingly, unbuffered read FIFO (UR) 234 provides both portions of an unbuffered information packet to interface circuit 226 . That is, the unbuffered phase 1 output information (P1_U_OutInfo) and type data (P1_U_OutType) are supplied from the unbuffered read FIFO (UR) 234 to the U_P1_Out register 276 , the unbuffered phase 2 output information (P2_U_OutInfo) and type data (P2_U_OutType) from unbuffered read FIFO (UR) 234 are provided to U_P2_Out register 278 .

In the following, reference 13 is now made to Fig.. If processing element 222 is not configured in a redirection mode, one of the buffered read and unbuffered read FIFOs (BR; UR) 232 and 234 selected from the core receives information along with mask data, which is explained below and are assigned to the information. If the redirection mode is not configured, the type data assigned to each section of an information package is irrelevant and is ignored. The buffered read FIFO (BR) 232 provides at its output either the two sections of a buffered information packet (ie either the buffered phase 1 output information (P1_OutInfo) or the buffered phase 2 output information (P2_OutInfo)) as well the mask data (OutMask) from the core to the interface circuit 226 . In particular, either the buffered phase 1 output information P1_OutInfo or the buffered phase 2 output information P2_OutInfo is supplied to the P1_Out register 272 or the P2_Out register 274 , the 32 bits of the buffered mask data (OutMask) being supplied to the mask register 284 will. Accordingly, the unbuffered read FIFO (UR) 234 provides each section of an unbuffered information packet as well as the unbuffered mask data (OutMask) from the core to the interface circuit 226 . In particular, either the unbuffered phase 1 output data (P1_U_OutInfo) or the unbuffered phase 2 output data (P2_U_OutInfo) are supplied to either the U_P1_Out register 276 or the U_P2_Out register 278 , with the unbuffered mask data (OutMask) the mask register 284 are provided. According to an exemplary embodiment, only a single bit of the unbuffered mask data is used.

The buffered mask data (OutMask) that is transferred to mask register 284 (when reading buffered information) is used to perform selective masking or "bit slicing" of the buffered information resulting from the Core spent to perform. In this way, the 32-bit mask selects buffered information on a bit-by-bit basis either from: (1.) the buffered information output from the core or (2.) either the buffered Information flowing through passageway 261 or the buffered information read from backup information path 290 . The only bit of unbuffered mask data (OutMask) that is transferred to mask register 284 (when reading unbuffered information) is used to select an entire 32-bit information word from one of the two sources just listed. It should be noted that, alternatively, 32 bits of the unbuffered mask data can be used to selectively "bit by bit" mask the unbuffered information from the core.

In the following, reference is briefly made to FIG. 14. A timing diagram is presented that illustrates the relationship between the outgoing clock signal Out_CLK, the read clock signal RD_CLK from the divide-by-two circuit 297 (shown in FIG. 6) and the buffered output information from one of the FIFOs 232 and 234 . The buffered output information, ie P1_OutInfo and P2_OutInfo, from the buffered read FIFO (BR) 232 are shown as an example and could also represent the unbuffered output information P1_U_OutInfo and P2_U_OutInfo. These signals are shown for comparison on the same time scale (horizontal axis). Placing one signal over another does not indicate that one signal has a greater amplitude than the other signals.

In Figs. 12 and 13 comprising the buffered read FIFO (BR) 232, the discharge control circuit 235 and the charging control TIC 237, wherein the unbuffered read FIFO (UR) 234 Ent charging control circuit 239 and the charging control circuit 234 to handled. The information and mask data are loaded into one of the FIFOs during a transition of the core clock signal when the load signal to one of the load control circuits 237 or 241 is activated, and are discharged from one of the FIFOs during a transition of the RD_CLK clock signal when either the buffered or unbuffered discharge signal (B_OutInfoUnld or U_OutInfoUnld) to one of the discharge control circuits 235 and 239 is activated. The signals B_OutDatVal and U_OutDatVal from the discharge control circuits 235 and 239 indicate that buffered or unbuffered information is ready to be clocked into a corresponding one of the read registers 272 , 274 , 276 and 278 .

As noted above, by controlling FIFOs 228 , 230 , 232 and 234 and backup information path 290 such that unbuffered (ie, priority) information always takes precedence over buffered (ie, non-priority) information , two different types of information are passed through a pipeline along a single bus without requiring any non-priority information present in the pipeline to be cleared or discarded before the priority information is sent can. That is, any non-priority information that is in the pipeline when a priority information packet enters the interface may be in one of the non-priority information storage elements in one of the non-priority information paths (ie, the buffered read FIFO (BR) 232 , the buffered write FIFO (BW) 228 or the buffered backup path 292 ) are held stationary until the priority information passes through the interface, whereupon the non-priority information can be retransmitted. By sharing both the incoming and outgoing buses of an interface circuit (e.g., interface circuit 226 ) for two unique and independent routes with a pipeline structure and not by providing reserved routes for either the priority or the non-priority information significant savings in terms of hardware and the ASIC pin count compared to systems known in the prior art, which only provide bus solutions with a pipeline structure that do not involve the common use of the resources.

Although it has been described herein that the invention is a bus used, which is able to a certain number of Transfer bits and that the invention special tax signals used to spread the information to control through the entire circuit is intended that a bus of any width and any Steueri gnalen, who perform corresponding functions in the Scope of the present invention falls. Although here in that the circuit elements during be coordinated edges of the clock signals could be clocked these elements additionally equivalent during the opposite set edges of the clock signals to be clocked without the Deviate scope of the invention.

Although specific types of In formation storage elements in the present invention any alternative can be used Types of information storage elements equivalent according to the intended scope of the invention can be used. Although the invention has been described in Ver Implementation of ASIC circuits can be implemented using diesel be further equivalent using a dedicated Hardware, a suitably programmed firmware or soft goods or any combination of the same be animal.

Although it has also been described that the bus system ver is used in various graphics processing devices to connect to a graphics processing system is Scope of the invention not on graphics processing limited applications, with the bus system equivalent ver any type of processing element can be used to connect. Although it has been described that the Interface circuits used to graphics processing  Processing devices interface with a bus connect, is the scope of the invention not only on the interface connection of Gra limited phic processing devices, the Interface circuitry can be used to equivalent Interface any type of device with a bus to connect moderately.

Claims (18)

1. A bus connection system for use in a graphics processing system having a plurality of graphics processing elements, the bus connection system having the following feature:
a bus structure coupling the plurality of graphics processing elements ( 202 , 222 , 242 ) in a ring, the bus structure comprising a plurality of individual buses ( 250 , 252 , 254 ), each of the individual buses ( 250 , 252 , 254 ) connects a pair of graphics processing elements ( 202 , 222 , 242 ), each of the individual buses ( 250 , 252 , 254 ) having an equal number of signal lines ( 250 A- 250 F) for transmitting graphics command signals and information signals between the graphics processing elements ( 202 , 222 , 242 ) in the ring. 2. Bus connection system according to claim 1, wherein the plurality of signal lines ( 250 A- 250 F) further comprises the following features:
a plurality of information signal lines ( 250 F) for transmitting the information signals; and
a clock signal line ( 250 A) for transmitting a clock signal associated with the information signals on the information signal lines to a next processing element in the ring. 3. A bus connection system according to claim 1, wherein the plurality of signal lines further comprises a standby signal line ( 250 B, 250 C) on which a ready signal from a first graphics processing element ( 226 ) to a previous graphics processing element ( 206 ) in the ring is transmitted, the ready signal indicating that the first graphics processing element ( 226 ) can receive information from the previous graphics processing element ( 206 ) in the ring. 4. A bus connection system according to claim 2, wherein the plurality of signal lines ( 250 A- 250 F) further comprises a signal for indicating a validity of information on the information signal lines ( 250 F). 5. The bus connection system according to claim 2, wherein the plurality of signal lines ( 250 A- 250 F) further comprises a plurality of type signal lines ( 250 E) for transmitting type signals indicating a type of operation associated with the information on the plurality of Information signal lines ( 250 F) to be performed. The bus connection system of claim 1, wherein one of the graphics processing elements in the ring is a host interface processing element ( 202 ), coupled to a host processor, for receiving commands and information signals from the host processor to the other graphics processing elements ( 222 , 242 ). to be forwarded in the ring. 7. The bus connection system of claim 6, wherein each of the graphics processing elements ( 222 ) further comprises:
a core processing unit ( 224 ); and
an interface unit ( 226 ), the interface unit having a passageway ( 261 ) to enable command and information signals to be transmitted directly via the interface unit to another graphics processing element in the ring, and a backup path ( 290 ) for temporary storage Chern the forwarded command and information signals. The bus connection system of claim 7, wherein the interface unit further includes a plurality of buffers ( 228 , 230 ) coupled to the passageway ( 261 ) for temporarily storing the command and information signals for transmission to the corresponding core processing unit ( 224 ). 9. Bus system according to, fehls- claim 7 in which all the loading and information signals, the interface processing element from the host (202) received who are transferred to be the core processing unit (204) of Hostver processing elements (202) before the same from the host interface processing element ( 202 ) to another graphics processing element in the ring. A bus connection system according to claim 7, wherein each of the processing elements ( 222 ) has a normal operating mode and a redirection operating mode, and in which during the normal operating mode command and information signals are forwarded via the through path ( 281 ) of the interface ( 226 ), and During the redirection mode of operation, command and information signals are forwarded via the core processing unit ( 224 ) before they are transmitted from the interface ( 226 ). 11. A method of operating a graphics system having a plurality of processing elements coupled in a ring, one of the processing elements being a host interface processing element additionally coupled to a host processor for receiving command and information signals from the host processor for transmission to other processing elements in the ring, the method comprising the steps of:
Receiving, at one of the processing elements in the ring, graphics command and information signals from a previous processing element in the ring;
Forwarding the received graphics command and information signals to a next processing element in the ring; and
Forwarding the received graphics command and information signals to a core processing unit of the processing element. 12. The method of claim 11, further comprising the steps of:
Receiving, at the host interface processing element, command and information signals from a previous processing element in the ring;
Forwarding the received graphics command and information signals to a core processing unit of the host processing element; and
Forwarding graphics command and information signals from the core processing unit to a next processing element in the ring. 13. The method of claim 11, further comprising the step of Forwarding a clock signal with the command and Information signals for a next processing has element in the ring, the clock signal and the information signals from a previous processing tion element can be received in the ring. 14. Graphics device with:
a plurality of processing elements ( 202 , 222 , 242 ) coupled in a ring via individual buses ( 250 , 252 , 254 ) for transmitting a corresponding plurality of signals, each of the plurality of processing elements ( 202 , 222 , 242 ) further has the following characteristics:
a core processing unit ( 204 , 224 , 244 ); and
an interface unit ( 206 , 226 , 246 ) coupled to receive information from a previous processing element in the ring on one of the individual buses and information to a subsequent processing element in the ring on a second of the individual Forward buses ( 250 , 252 , 254 ). 15. A graphics device according to claim 14, wherein each of the individual buses ( 250 , 252 , 254 ) comprises a standby signal line for transmitting a standby signal from a first processing element to a previous processing element in the ring, which indicates that the first processing element is not is able to receive data from the previous processing element. 16. The graphics device according to claim 15, wherein the individual buses ( 250 , 252 , 254 ) further have the following features:
a plurality of information signal lines ( 250 F) for transmitting a plurality of information signals for use in executing graphics commands by the graphics device; and
a clock signal line ( 250 A) for transmitting a clock signal which is received with the information signals at the associated processing element. 17. The graphics device of claim 16, wherein the clock signal and the information signals received at one of the processing elements ( 202 , 222 , 242 ) are forwarded together to a next processing element in the ring. The graphics device of claim 14, wherein one of the processing elements ( 202 , 222 , 242 ) in the ring is a host interface processing element ( 202 ) coupled to a host processor, and wherein the core processing unit ( 204 ) of the host interface processing element ( 202 ) processes all information received from the ring and from the coupled host processor before forwarding the information to a subsequent processing element ( 222 , 242 ) in the ring.