DE19782228C2 - N-bit adder with adder blocks - Google Patents

Abstract

The present invention provides a 64-bit adder that has four spatially pipelined 16-bit adder blocks (310). Each adder block contains 16-bit summing and leakage carry logic that is configured in parallel. The summing logic (320) of an adder block provides a 16-bit result (326) corresponding to the 16-bit operands (312) and an incoming carry signal (314) which are input to the adder block, at an associated block output. The logic (340) for the outgoing carry of an adder block determines an incoming transfer signal (319) for an adjacent adder block. The first adder block provides a 16-bit result at its associated block output at a rate determined by the delay of the 16-bit summing logic. The 16-bit results from the next three adder blocks are determined sequentially as soon as the incoming carry from the previous 16-bit block becomes available.

Description

The invention relates to an N-bit adder with k (N / k) bit adder blocks, with each (N / k) bit adder block ei ne summing logic for generating an (N / k) bit result and a carry logic to generate an expiring over has inert, and a method for adding two N-bit operands.

The arithmetic-logic unit (ALU) is a center le component of each processor. The ALU performs addition, Subtraction and logical operations through and is at any command used to calculate an address must become. Because of their central role and complex radio tion, the ALU is usually a critical path in the Determine the speed at which the processor can work. For example, the ALU self-determination determines path (ALU self-bypass path), how much time from the start an ALU operation is required until the result of the Operation for use in a subsequent calculation is available. Processor designers typically use the ALU self-bypass path to the cycle time target for the Processor.

A lot of effort is currently being made to optimize the design of 64-bit wires, as such adders are often the slowest components in a 64-bit ALU. The various optimization techniques can be understood by referring to the logical equations used to sum two single bit numbers (A and B):

SUM = A ⊕ B ⊕ C _in (I)

C _out = G1 + P1. C _in (II)

Here, G1 is a 1-bit generate signal that is generated by A. B is given, P1 is a 1-bit propagation signal given by (A + B) or (A ⊕ B), where "." represents the logical AND operation, "+" represents the logical OR operation, "⊕" represents the exclusive OR (XOR) operation, where C _out is the carry bit generated by summing A, B, and C _in , and C _in the carry bit generated by a bit of the adder. Since C _{in is} generated by a preceding bit sum, the direct application of (I) and (II) to an N-bit adder would require the bits to be summed in N sequential stages, with the C generated by one stage _out to the next bit pair. The resulting delay for N-bit adders quickly becomes intolerable as N (the adder width) increases.

Conventional adders use various techniques to avoid sequential summation of all bits. In particular, carry look-ahead and carry select techniques are often combined to implement a high degree of parallelism with N-bit wires. An example of a carry select adder is described by OJ Bedrij in "Carry Select Adder", IRE Transactions on Electronic Components, June 1962, pages 340-346. Carryforward lookup techniques divide the N-bit adders into blocks of L bits each. Forwarding, generating and expiring carry signals (PL, GL, CL) for the L-bit blocks are calculated in parallel. OJ Bedrij describes a 25-bit adder with 5 blocks, each 5 bits wide. Carry selection techniques compute speculative sums for each L-bit block for a C _in of 0 or 1. In any case, C _in for a block (j) is CL for the previous block (j-1). The correct L-bit sums and carryovers are selected when the L-bit results from the previous blocks become available.

It can be shown that under certain conditions an N-bit adder using these techniques has a delay in a chain of (2 + log _L [N]) gates. A first gate calculates P and G signals from the L-bit operands, the log _L [N] gates generate the forward and generate signals and the outgoing higher order carry and the remaining gate carries the final XOR through, e.g. B. Equation (I). For a 64-bit adder with L = 4, this leads to a 5-gate delay. While the logarithmic dependence indicates that larger L are desirable, the operation of a CMOS gate is significantly slowed down if it is driven by more than four inputs (fan-in <4). Thus, CMOS adders typically use gates that have peaks of 4 or less. In addition, the number of gates in the critical path of the adder provides only a rough estimate of the adder speed since the cycle time depends on the complexity of the gates used and the load on the gates.

Certain adder designs implement one Ling pseudo-carry, which is a modified generate Si signal (H) used in addition to the forwarding signal (P). The modified generate signal allows 4-bit H- and -P signals (H4, P4) directly from the operand bits below Use of a gate with a fan-in of 4 be be counted. This eliminates a gate from the adder, he but calls for the use of larger, slower gates Calculation of the forward and carry signals. One of these Technology using adder is in S. Naffziger, "A Sub- Nanosecond 0.5 mm 64b Adder Design ", Proceedings of the 1996 IEEE International Solid-State Circuits Conference ben.

Using optimized technologies and parallel Architectures can give this well known adder a 64 bit result nis with a delay of about 7 inverters with a Fanning out 4 (in a little less than a nanosecond with the 1996 CMOS technology). In in any case, the critical path is limited by the delays transfer chain. To the operating frequencies of Processors over this through simple process improvements supported frequency increases further increase an even faster adder architecture is required.  

This task is carried out by an N-bit adder with the Merk paint the claim 1 or a method with the features of claim 5 solved.

The present invention is an N-bit adder that does so arguably the delay in calculating the least weight bits of an operation as well as the cycle time of the ad at the expense of a longer delay for those at the highest most evaluated bits minimized. According to the present Er k (N / k) bit adder blocks, each one (N / k) bit summing logic and logic for the expiring Have carry, with each other in the manner of a pipeline coupled to form the N-bit adder. The summation logic of an adder block sets an (N / k) bit result at the output of the adder. The logic for the expiring Carry determines the outgoing carry signal for the Adderblock and couples it to the neighboring Adderblock. In an N-bit adder according to the present invention flows ate the data through the k adder blocks in the manner of a pipe line. The N / k least significant bits of the result are available with a delay caused by the (N / k) bit summing logic is determined while the bits are increasing order becomes available at subsequent intervals, the between the forwarding of the expiring carryover between the blocks.

Advantageous developments of the invention are in the Subclaims marked.

The present invention is best referenced on the following detailed description and accompanying understandable drawings.

Fig. 1 is a timing chart of a conventional N-bit adder that performs a two-stage calculation.

Fig. 2 is a timing diagram of a pipeline N-bit adder according to the present invention, which performs a two-stage calculation.

Fig. 3 is a block diagram of an exemplary embodiment of a game pipeline N-bit adder according to the present invention.

Fig. 4 is a block diagram of an exemplary embodiment of a game 64-bit pipelined adder according to the present invention.

Fig. 5A, according to a block diagram of an exemplary embodiment of a game 16-bit Adderblocks of the 64-bit adder Fig. 4.

FIG. 5B is a schematic illustration of an exemplary embodiment of a 4-bit adder sub-block of the 16-bit adder block according to FIG. 5A.

FIG. 5C is a schematic illustration of an embodiment of the outgoing carry logic for the 16-bit adder block of FIG. 5A.

Detailed description

Referring first to FIG. 1, a timing diagram 100 for a conventional N-bit adder including a self-bypass period 102 is shown. The timing diagram shows a two-step calculation, C = A + B ( 104 ) and E = C + D ( 106 ), separated by a self-bypass period 102 , in which the result C of the first addition back to the adder as Operand for the second addition is sent. The expression in brackets [N - 1: 0] indicates that the adder works on all N bits (N - 1 to 0) simultaneously. For purposes of this discussion, assume that the N-bit adder can be segmented into k (N / k) -bit blocks, such as a 64-bit adder that is segmented into four 16-bit blocks.

In addition, the times T1, T2 and T3 are shown in FIG. 1. T1 is the time required to generate the (N / k) least significant bits of the N-bit result. T2 is the self-bypass cycle time of the adder, that is, the time required before the adder can start the second addition 106 . T3 is the time required to generate the N-bit result. This is the time required before subsequent operations that require all N bits of the result can begin. Since a conventional adder generates all N bits at once, T1 is T3. That is, the N / k-bit result is only available when the full N-bit result has been calculated.

The determination of the expiring N-bit carry represents make a significant contribution to T1 and T3 as the over chain lies in the critical path of the adder. From the For this reason, the logic for the expiring carry is below Implemented using relatively large gates to control the Si signal transmission through the transmission chain accelerate which is in the critical path of T3. The Use of relatively large gates in the logic for the Auslau The carry forward increases the load on the summation logic path, which T1 specifies. However, since minimizing T3 the up is given to these veins, this increase of T1 is considered considered acceptable.

However, many applications of an adder do not require that all N bits are available before the next operation begins. For example, adders are used repeatedly for address calculations in which any subset of the N-bit result is used to initiate a memory read. Consider the case of a processor that has a 4 KB cache configured in the form of 128 cache lines of 32 bytes each. With this configuration, bits 5-11 of an address calculation can be used to start row decoding as soon as they are available. This is a critical step in cache reading, and anything that speeds up the availability of these low-order bits reduces the cache reading delay. In typical cache organizations, a subset of the 16 least significant bits is critical to quickly accessing cache data, and the speed at which this data is accessed greatly affects the effectiveness with which the processor operates . Hence, a reduction in T1, the latency for the N / k least significant bits, is important.

Other operations can also begin as soon as a subset of the full N-bit result is determined. For example, the second step of the two-step addition shown in FIG. 1 could begin as soon as a subset of the N-bit result from the first step is available, and left shifts are relatively common operations that can be started as soon as suitable dimensioned sub-blocks of data are ready. As noted above, the self-bypass cycle time (T2) that characterizes these operations is an important design parameter. Reducing T2 is required to increase the frequencies at which ALUs operate.

In summary, it can be said that T2 is ideal fall the cycle time of the microprocessor dictated and it out for this reason the main delay is that in one Minimize Adder. T1 affects cache access delay, and it is also important to minimize it ren. T3 specifies the delay only for those operations that require all N bits of the result (as with for example, shifts to the right). The minimization of T3 is therefore less important than minimizing either T1 or T2.

The present invention is an N-bit adder that consists of k (N / k) bit adder blocks is formed to take advantage the lesser delay to pull through the small one ren adder blocks is provided. In particular does each of the k (N / k) bit adder blocks have an (N / k) bit Summing and carry logic on, and the k adder blocks are connected in the manner of a pipeline. this will performed by a block corresponding to a block of bits Adderblock with one Adderblock for the next few most evaluated bits via the carry logic of the first adder block  is coupled and by this coupling at Adder blocks are repeated for subsequent blocks of higher value becomes. The summation logic, which is the (N / k) bit result of the Adderblocks is designed with an associated output for coupled the adder block. This allows self-bypass (self-bypass) as soon as an N / K bit result for the block is available instead of a delay until the entire N-bit adder ends. Since the outgoing carry every N / k- Bit block is no longer critical to the N / k bit result is can also be used to implement the logic dim down the gate used for the outgoing carry what the load on the critical N / k bit Summation path reduced. In addition, this topology reduces the length of the wires in the adder and thus the load on the critical path.

Referring now to FIG. 2, in a timing diagram 200 is shown that the spatially pipeline-ver nested architecture of an N-bit adder according to the reflected vorlie constricting invention. The timing diagram includes k timing diagrams 210 ( 1 ) -210 (k). Each diagram 210 ( 1 ) -210 (k) represents the processing by an adder block of an (N / k) bit block of the N bit operand to an (N / k) bit result and an expiring carry of the Generate N / k bit blocks (CN / k). As indicated by arrows 212 ( 1 ), CN / k of the adder block presented by diagram 210 ( 1 ) re is calculated in parallel with the (N / k) bit result and to the adder block which is through diagram 210 ( 2 ) is coupled in time for use in determining its (N / k) bit result. The architecture is repeated for the remaining blocks of the adder, as shown by timing diagrams 210 ( 3 ) -210 (k).

The times T1, T2 and T3 for a conventional adder are shown in FIG. 2 under the associated times T1 ', T2' and T3 'of the spatially pipeline-nested adder. The time to low order (N / k) bit result [N / k - 1: 0], T1 'is shorter than T1 for the conventional adder. This is because the generation of the carry-over into bits [N - 1: N / k] no longer strains the critical path to the (N / k) bit result. The bypass time T2 'for diagram 210 ( 1 ) of the adder architecture is shorter than the bypass time T2 for the conventional adder 110 because only the N / k least significant bits need to be known before bypassing. In particular, the gate that determines the N-bit result from the speculative (N / k) bit sums and the (N / K) bit carry signals is from the path to the (N / k) bit Result removed. This reduces the number of gates in the adder self-bypass path from 9 to 8, which allows the ALU to run about 12.5% faster.

The to generate the full N-bit result at Use of a spatially pipelined architect T3 'required time is greater than the corresponding Time (T3) for a conventional adder. This is based on the The fact that the pipeline interleaving the degree of Pa parallelism is reduced when the carryover is generated can be placed. In particular, the calculation of CN / k for a block cannot be completed until CN / k for the previous block has been determined. The additional Delay T3'-T3 increases with k because of the block carry must move through several blocks (ripple).

Referring now to FIG. 3, there is shown a block diagram of a spatially pipelined N-bit adder 300 in accordance with the present invention. The N-bit adder has k (N / k) bit adder blocks 310 ( 1 ) -310 (k). In the following discussion, references to multiple adder blocks 310 ( 1 ) -310 (k) and their components are not indexed as long as a particular adder block need not be distinguished. Where appropriate, a representative single adder block 310 is, for example, indexed as adder 310 (j). The same Indexierungsvereinba tion is used in all subsequent figures.

As shown in FIG. 3, each adder block 310 includes (N / k) bit summing logic 320 , (N / k) bit logic for the outgoing carry 340 , a first input 312 for receiving an (N / k) bit blocks of an N-bit operand, a second input 314 for receiving an incoming carry signal from a previous block, an output 316 for supplying an (N / k) bit result and an output 318 for Providing an outgoing (N / k) bit carry signal (CN / k) to an adjacent adder block 310 , ie the next higher rated block of bits. In this discussion, the term "summing logic" includes gates for calculating low order P and G signals that are used to determine an (N / k) bit result, e.g. B. (N / Lk) bit P and G signals on an (N / k) bit block. Outgoing carry logic 340 includes logic to generate CN / k from the precursor forward (P) and generator (G) signals. In conventional logarithmic wires, for example, the precursor P and G signals for the (N / k) bit logic 340 for the outgoing carry are the N / Lk bit P and G signals, where L is the number of inputs that drive the gate (fan-in). In particular with a 64-bit adder (N = 64), which is divided into k = 4 blocks with a simplification of L = 4, the precursor 4-bit generation and forwarding signals G4 or Be P4. The present invention is not limited to adders based on logarithmic architectures.

The (N / k) bit sum at output 316 (j) of summing logic 320 (j) does not depend on the CN / k carry out at output 318 (j). The outgoing carry (N / k) bit logic 340 (j) operates in parallel with the (starting at the point in summing logic 320 (j) where the precursor P and G signals are calculated) N / k) bit summing logic 320 (j). Except for loading summing logic 210 (j), the (N / k) bit logic 340 (j) for the outgoing carry is actually off the path to the (N / k) bit result provided by the summing logic 310 (j) is removed, and loading can be reduced by downsizing carry chain logic 340 (j) to speed up the path to the (N / k) bit result.

Referring now to FIG. 4, there is shown a block diagram of one embodiment of a 64-bit spatially nested adder 400 in accordance with the present invention. The adder 400 has four 16-bit adder blocks 410 ( 1 ) -410 ( 4 ). Each adder block 410 has a fast 16-bit carry select adder 420 and 16-bit logic 440 for the outgoing carry. In addition, blocks 470 , 412 for forwarding the data to the adder 420 and a block 430 for selecting a 16-bit result from the adder 420 or from other ALU function blocks (such as logic operations) are shown in the figure. Block 470 is an early bypass multiplexer (MUX) that selects non-critical results from the register file or writeback queue to generate source ALU data. Block 412 is a late bypass MUX that contains the ALU operand source from MUX 470 , a data cache read result, or an ALU result from the previous cycle from either its associated adder or one selects another adder in a superscalar execution unit. Block 430 is a late result MUX that selects the 16-bit result of the adder 420 or other ALU function block and returns it to the bypass MUX 412 . In addition, to provide a context, FIG. 4 shows the register file access path that starts with a decoded register ID. The register file access path includes a word line driver 450 and a register / read circuit 460 .

For purposes of illustration, only the gates in the critical path to the 16-bit result of adder block 410 and the gates in the critical path to the 64-bit result of adder 400 are shown in FIG. 4. The critical path to the 16-bit result of adder 420 includes gates 422 , 424 , 426 and 428 . Gate 422 computes 2-bit propagate and generate signals P2 and G2, gate 424 computes P4 and G4, gate 426 computes 4-bit carry (C4) and gate 428 (MUX 428 ) selects a 16-bit result according to the 16-bit carry entering the adder 420 and the 4-bit carry computed by the adder 420 . A speculative summation path (illustrated in more detail in FIG. 5) that is not in the critical path of adder 420 is configured in parallel with gates 422 , 424 and 426 to provide speculative sums to result MUX 428 .

The spill carry logic 440 includes a gate 442 for computing 16-bit generate and forward signals (P16, G16), an inverting buffer 444, and a gate 446 for determining a 16-bit spill carry signal (C16). Leak carry logic 440 determines C16 from P4 and G4 signals (precursor signals) generated by gate 424 in adder 420 and is discussed below in connection with FIG. 5C.

As shown in FIG. 4, a 16-bit result is available at the MUX 428 output. In the disclosed embodiment, the least significant 16-bit result is shown to drive the data cache to begin row decoding. The spatially pipeline-nested structure of the adder 400 allows the row decoding to begin as soon as the 16-bit result is available, e.g. B. Before 16-bit results have been generated from wires 420 ( 2 ) -420 ( 4 ). Thus the cache access delay (T1) of adder 410 is shorter than it would be if adder 400 first calculated all 64 bits of the result. By downsizing gates 442 , 444, and 446 of outgoing carry logic 440 , the load on adder 420 is reduced, which further increases the speed of the lowest order 16-bit result.

Also shown in FIG. 4 is a self-bypass path formed by late result MUX 430 and late bypass MUX 412 in conjunction with adder block 420 . Since the 16-bit result on MUX 428 ( 1 ) is available with the relatively small delay of 16-bit adder 420 ( 1 ), ie without resorting to any 16-bit carry determined by adder 400 , this can 16-bit late bypass result MUX 412 ( 1 ) returned faster. This allows a subsequent addition, subtraction, etc. to the low-order bits to start faster than would be possible if the complete 64-bit result had to be generated first. Thus, the self-bypass cycle time (T2) of the adder block 410 is reduced, and the operating frequency of the adder 400 may increase accordingly.

The adder 400 can be implemented in any of the available semiconductor technologies. A preferred embodiment of pipeline adder 400 is implemented in CMOS using opportunistic time-borrowing domino logic to eliminate latch delays from the critical path. Dual-rail domino techniques are used to implement non-monotonous functions. The opportunistic time-borrowing domino logic is discussed in greater detail, for example, in U.S. Patent No. 5,517,436, which is hereby incorporated by reference.

Referring still to FIG. 4, in which the Gat ter of the block 410 (4), the gates 414, 416, 422, 424, 426, 428, 432, 434, 442, 444 and 446 correspond with a D or an S are marked, followed by a number that indicates the gate structure in a domino implementation of the adder 400 . Here D denotes a domino gate, S denotes a static gate, and the number indicates the number of transistors in the pull-down / pull-up chain of the respective D / S gate. In the Domino embodiment, the early bypass MUX 470 is a Domino MUX 472 and a static inverter 474 . The word line driver 450 includes a domino inverter 452 and a static inverter 454 , and the bit line scan module 460 includes an SRAM cell 462 and a static inverter 464 . In addition, block 480 re-presents a stage network required to coordinate the clock signals among the domino gates of adder blocks 410 ( 1 ) -410 ( 4 ).

In the rest of the discussion, dual-rail dominoes Circuits used for illustration, one Po larity of each gate and signal is disclosed. The com complementary signals and the gates for generating this com complementary signals can easily be viewed from the clear embodiment using known Ver determine driving.

Referring now to FIG. 5A, a block diagram of one embodiment of a fast 16-bit adder 420 is shown. In this embodiment, the 16-bit adder 420 is divided into four 4-bit adders 510 ( 1 ) - 510 ( 4 ) and logic 520 for the outgoing carry. Each of the 4-bit adders 510 has inputs 512 for receiving 4-bit sub-blocks of the 64-bit operands, an input 514 for receiving an incoming 16-bit carry from the previous stage, and inputs 515 for receiving of incoming 4-bit transfers (C4 _in ). Inputs 515 of adder 510 ( 1 ), which handles the least significant four bits of the 16-bit block, are coupled to 0 and 1, while the C4 _in for adders 510 ( 2 ) -510 ( 4 ) can be determined from the 16-bit block 520 using the P4 and G4 signals calculated by the wires 510 ( 1 ) to 510 ( 3 ). The adders 510 are discussed in more detail below in connection with FIG. 5B.

Outgoing carry logic 520 includes lookout circuits for forwarding 4-bit transfers between 4-bit wires 510 for those cases where C4 _in to adder 510 ( 1 ) is 0 and 1. In particular, the 16-bit block 520 implements the logic equation (III):

C4 (j) _out = G4 (j) + P4 (j). C4 (j - 1) _in (III)

Here, the index j specifies one of the adders 510 ( 1 ) - 510 ( 4 ). For adder 510 ( 1 ), C4 (0) is _in 0 and 1, as discussed above. For example, C4 (1) _out = G4 (1), if C4 (0) is _in = 0 and C4 (1) _out = G4 (1) + p4 (1), if C4 (0) is _in =. 1 These functions are implemented by buffers 522 or OR gates 524 in 16-bit block 520 .

The calculation and the associated logic become more complex later in the transfer chain. For example, the incoming carry C4 ( 4 ) _in to the adder 510 ( 4 ) is given by the logical equation (IV):

C4 ( 3 ) _out = G4 ( 3 ) + P4 ( 3 ). G4 ( 2 ) + P4 ( 3 ). P4 ( 2 ). G4 ( 3 ). P4 ( 2 ). P4 ( 1 ). C4 (0) _in . (IV)

This is implemented by the complex gates 526 and 528 for cases in which C4 - _is equal to 0 or 1 (j 1). Here, "complex gates" refers to gates formed by combining component AND and OR gates, as can be done efficiently in CMOS logic. Complex gates are displayed by placing the component gates in contact with each other. In particular, complex gate 528, due to its size and complexity, is in the critical path to the 16-bit result of adder 420 and corresponds to gate 426 in FIG. 4. Gates 422 , 424, and 428 , which are complex gates that do critical path of the adder 420 are components of the adder 510 and are discussed in more detail below.

Referring now to FIG. 5B, a schematic representation of an embodiment of a 4-bit adder 510 is shown. In the disclosed embodiment, the adder 510 is divided into four sets of gates 552 , 554 , 556 , 558 that represent the separation of the gates 422 , 424 , 426 , 428 shown in FIG. 4. The dashed, vertical lines indicate the boundaries between the different gate sets 552 , 554 , 556 , 558 . In the do mino embodiment of the adder 510 , the dashed lines also represent the boundaries between domino and static gate sets, as shown in the figure.

Each of the gate sets 552 , 554 , 556 , 558 is also labeled according to the signal it generates. For example, complex gates 532 , 534 , 536 , 538 of set 552 generate signals G2 <0 <, P2 <0 <and G2 <1 <, P2 <1 <from the input bits a <3: 0 <and b <3: 0 <. The remaining gates of set 552 determine 1-bit generate and forward signals P1 <0 <-P1 <3 <and G1 <0 <and G1 <2 <. Where, as in this case, P1 <n <is defined as the XOR of the operands bits a <n <, b <n <, P1 <n <is also equal to the bit sum for C _{in <} n <= 0. Due to its relative Size and complexity is complex gate 532 in the critical path of adder 510 and corresponds to gate 422 in FIG. 4.

In gate set 554 , complex gate 542 and gate 544 determine the 4-bit generate and forward signals G4 and P4 from P2 <0 <, G2 <0 <, P2 <1 <, G2 <1 <. The lower gates of set 554 determine 1-bit outflow carry-outs from the 1-bit forward and generate signals P1 <0 <, P1 <1 <, P1 <2 <, P1 <3 <and G1 <0 < , G1 <2 <. Because of its relative size and complexity, complex gate 542 is in the critical path of adder 510 and corresponds to gate 424 in FIG. 4.

In gate set 556 , the lower gates determine speculative sum pairs s0 <0 </ s1 <0 <, s0 <1 </ s1 <1 <, s0 <2 </ s1 <2 <and s0 <3 </ s1 <3 <for bits 0-3, whereby carryovers of 0 and 1 are assumed. The upper gates of set 556 contained in 16-bit block 520 determine 4-bit speculative carry, ie, 4-bit carry for C16 _in = 0 and 1. As noted in connection with FIG. 5A, is gate 528 in the critical path of adder 510 and speaks to gate 426 in FIG. 4.

The gate set 558 comprises the MUXs 559 , which accordingly selects one of the speculative sums s0 / s1 in accordance with the outgoing 4-bit transfers of the adder 510 and the incoming 16-bit transfer to which the adder 510 is at the level indicated. Since it is the only gate present in gate set 558 , MUX 559 is in the critical path of adder 510 and corresponds to gate 428 in FIG. 4.

Referring now to FIG. 5C, block diagrams of the embodiments of gate sets 560 , 570 , 580 for determining C16 from P4 and G4 signals generated in wires 510 ( 1 ) - 510 ( 4 ) are shown. In particular, gate set 560 includes complex gate 562 , which determines G16 from the G4 and P4 signals calculated in 16-bit block 420 , and gate 564 , which determines P16 from the P4 signals. Due to its size and complexity, complex gate 562 is in the critical path and corresponds to gate 442 in FIG. 4. Gate set 570 receives buffer 572 , which corresponds to buffer 444 in FIG. 4, and gate set 480 contains this complex gate 482 for computing C16, which corresponds to gate 446 of FIG. 4. Those skilled in the art will recognize that there are alternative circuits for generating these signals that fall within the scope and spirit of the present invention.

An N-bit adder is thus made available which has a spatially pipeline-nested configuration instructs to be the time to score the lowest evaluated bits (T1) and the bypass cycle time (T2) to re reduce. This is done by segmenting the adder into k (N / k) bit adder blocks and by coupling the adder blocks in like a spatial pipeline. The invention enables self-bypassing after a short delay an (N / k) bit adder block. It also enables downsizing the carry logic to the Bela on the critical path to the (N / k) bit total reduce order.

The present invention has been accomplished in various ways Described embodiments that are only for the purpose serve as an illustration. Specialists become from this Description recognize that the invention is not based on the be described embodiments is limited, but with Modifications and changes that can be made  only by the spirit and scope of the pending claims be restricted.

Claims (8)

1. N-bit adder with k (N / k) bit adder blocks ( 310 ), each (N / k) bit adder block ( 310 ) having summation logic ( 320 ) for generating an (N / k) - Bit result and a carry logic ( 340 ) for generating an expiring carry (CN / k),
characterized by
that the second (310 ( 2 )) to k-th (310 (k)) (N / k) -bit adder block each only with the output ( 318 ) of the neighboring lower-rated ( N / k) bit adder blocks ( 310 ) are coupled,
that the first (N / k) bit adder block (310 ( 1 )) has the least weighted (N / k) bit result at an output of the N bit adder with a through the summing logic (320 ( 1 )) of the first (N / k) bit adder block (310 ( 1 )) provides a certain delay so that the result can be used for further operations, and
that the subsequent (N / k) -bit adder blocks (310 ( 2 ) ... 310 (k)) send their (N / k) -bit results to further outputs of the N-bit adder after receipt of the respective expiring super Provide carrier (CN / k) from the neighboring (N / k) bit adder block. 2. N-bit adder according to claim 1, characterized in that the outputs ( 316 ) providing the (N / k) bit results are coupled to a cache in such a way that the cache can begin to initiate row decoding as soon as the least significant (N / k) bit result is provided from the output of the first (N / k) bit adder block (310 ( 1 )). 3. N-bit adder according to claim 1 or 2, characterized in that the least significant (N / k) bit result providing output of the first (N / k) bit adder block (310 ( 1 ) ) is coupled to an input of the N-bit adder by a bypass line. 4. N-bit adder according to claim 3, characterized in that that an addition of the least valued (N / k) bit Er result and a new (N / k) bit segment is initiated, as soon as the result provided via the bypass line is available at the input of the N-bit adder. 5. A method of adding two N-bit operands using an N-bit adder with k (N / k) -bit adder blocks, wherein
k sets of (N / k) bits each of the two N-bit operands are made available to the k adder blocks,
processing the first, least significant set of (N / k) bits, producing a least significant (N / k) bit sum and a carry bit,
the carry bit is made available to the second adder block, and
the lowest-valued (N / k) bit sum is provided at a first output of the N-bit adder, while the second to k-th adder block still process the sets of (N / k) bits made available to them. 6. The method according to claim 5, characterized in that the second (N / k) bit sum to (k - 1) th (N / k) bit sum be at a second to (k - 1) th output of the N-bit adder be provided during the third to kth adder block the sentences of Process (N / k) bits. 7. The method according to claim 5 or 6, characterized records that the lowest valued (N / k) bit sum  in a bypass back to an input of the N-bit adder is directed. 8. The method according to claim 7, characterized in that that the addition of a third operand to the sum of the first and second operands are initiated as soon as the least significant (N / k) bit sum to an input of the N-bit adders has been returned.