DE19751439A1 - Programmable controller for connection of sensors and actuators - Google Patents

Abstract

The controller consists of a control unit, a processing unit, registers and memory. The controller comprises a bit-oriented controller and a byte-oriented controller. The bit-oriented controller is application-specifically hard-wired. The control unit in the byte-oriented controller may be application-specifically hard-wired. The bit-oriented controller and the control unit in the byte-oriented controller may be completely accommodated in a programmable logic device, such as a field-programmable gate array, complex programmable logic device, or EPROM. A method of controlling a programmable controller is also claimed.

Description

1 Introduction

Application-specific integrated circuits (Asics) change our technical environment, especially the two programmable subgroups CPLDs and FPGAs. You could earlier already implement parts of a controller with FPGAs (see patent EP 0 499 695 A2 and patent EP 0499695 A2 ≘ DE 42 05 524 A1) or control programs for binary signal processing in one Implement state machines in the interior of a CPLD (see patent DE 40 38 533 A1) to house the complete control in one FPGA today. The circuit is usually realized as a microprocessor or as an automat (Moore, Mealy or Metvedev) inside the FPGAs. In contrast, the present invention provides a programmable controller application-specific hard wiring available from a STEP5 program can be developed.

Compared to programmable logic controllers, application-specific hard-wired controllers have the following advantages:

• - parallel processing of logic possible,
• - Much shorter cycle times,
• - lower control costs,
• - reduced space requirement of the control,
• - modular construction possible,
• - simplified storage of system components,
• - increased system reliability as well
• - Reduction of system power loss.

So far, even for small controls where flexibility is required, Programmable logic controllers are used. Application-specific hard-wired Controls with FPGAs represent a smaller alternative that corresponds to the size of the system.

A problem, however, is the programming of the FPGAs, which until today have only been reserved for engineers remains. The procedure for converting a STEP5 program into a application-specific hard-wired control also puts practitioners with PLC knowledge in the Able to program FPGAs.  

The microprocessor is also used in control technology in many applications found, but can only be programmed by experts due to the complexity of the assembler code become. The difference between this controller and a microprocessor is that it is bit-oriented Operations are implemented one-to-one in hard-wired logic. Besides, there is none Program in a program memory, like a processor, but one application-specific hard-wired control unit.

Since FPGAs work internally in parallel, it is possible that several bit operations in only one System clock cycle and byte operations can be processed in a maximum of two system clock cycles can. This results in very short signal delay times and very fast ones Control response times.

On the surface, a direct implementation of the STEP5- Programs in the hardware description language VHDL (Very High Speed Integrated Circuit Hardware Description Language). The resulting control would be many times too complex to be implemented in an FPGA. Proved to be a far better process a structured implementation, which also contains fixed components. The Fixed components only occur in byte-oriented control.

An overview of the overall circuit is shown in the Appendix in Figure 1. The individual components of the control system are described below:

• - The application-specific hard-wired bit-oriented control,
• - The fixed components of the byte-oriented control and
• - The application-specific hard-wired control unit.

2 The application-specific hard-wired bit-oriented control

The logic operations in the bit-oriented controller are activated by the micro clocks (µTn) of the micro program counter (µPc), so that the corresponding logic operations are carried out in each system cycle. According to Figure 2, the logic circuits ( 1 ,..., 1 ') are connected to the state memory ( 3 ) via the multiplexer ( 2 ) controlled by the micro clock. The correct results of the logic circuits are stored in the correct state memories in each micro clock cycle. Flags (M), inputs (E), outputs (A), logic results (RLO), count results (Z) and timer results (T) are stored in the status memory. The current states can be further processed with the bus ( 5 ) in the logic circuits ( 1 ,..., 1 ') or sent to the outputs (A0,..., On). The inputs (E0,..., Em) are buffered in the status memory and the outputs (A0,..., On) in the output latch ( 4 ,..., 4 ') in order to keep their values constant during a program cycle . The reading of the inputs and the output image is carried out simultaneously in micro clock cycle zero, in which there is no logical linkage yet.

Bit operations

The bit-oriented control contains the bit operations as hard-wired logic. Each Operation is converted directly into combinatorial logic, making it very small Processing times result.

Table 1 shows an overview of the operations and the associated circuit implementation.

Table 1

This creates a combinatorial logic circuit with successive gates, which is later parallelized by minimizing by summarizing and the number of which is reduced.

Parentheses

When opening parentheses with O (or U (a second combinational logic circuit started when the bracket was closed with) added to the first combinatorial circuit becomes.

Additional clock cycles

The next step will be when to implement a STEP5 program combinatorial circuit is no longer sufficient and a micro clock must be waited for.

This is necessary after setting (S), resetting (R) or assigning (=) flags if the flags are used again. The flags could be used by And (U), Undnicht (UN), Oder (O) or Odernicht (ON). The same applies to entrances and exits. Figure 3 shows the different options.

You can keep the number of micro clocks low by trying so-called To bypass "scratch marks". Lubrication flags are flags that appear in the same program cycle different meanings can be used. You can always use new flags instead of them use.  

Likewise, one to two additional micro clocks are inserted after all byte operations, because at most one byte operation is possible in one micro clock cycle.

Especially after all timer operations SI, SE, SV, SA, SS and R and all counter operations S, R, ZV and ZR require two micro clock cycles. So you get on subsequent queries the correct timer or counter status.

Nevertheless, significantly fewer micro clocks are required in one program cycle than Cycles in a program cycle of a programmable logic controller. First, because of that application-specific hard-wired control requires only one micro clock per byte operation, and secondly, because several bit operations can be carried out in parallel in one micro-cycle.

3 The fixed components of the byte-oriented control

The thin components of the byte-oriented controller framed thinly in Figure 1 are required for all applications. With the exception of the data storage, their content is the same for all applications. The application-specific constants of the STEP5 program are stored in the data memory and there is space for data blocks. In contrast to the programmable logic controller, there is no program code that should be stored in the memory. The timers and counters are also the same for all applications, only their number depends on the applications. In order to keep the circuit as small as possible, you should use as few timers and counters as possible.

The entire circuit is clocked synchronously. To control the timers (T1, T2,..., Tn) the System clock with the frequency divider (T) divided into different frequencies. So will be several Enable lines are made with short pulses for the timers, and the different time bases realized that come from the STEP5 programming language.

Table 2 shows the different time bases and the associated frequencies on the enable lines.

Table 2

Frequencies of the enable lines for the timers

As mentioned in the previous section, both the timers (T1, T2, ..., Tn) and Counters (Z1, Z2, ..., Zm) in the byte-oriented controller are the same for all applications. To do this Different timer or counter attachments are required in the bit-oriented control. Through it the different STEP5 operations SI, SE, SV, SA, SS and R for the timers and S, R, ZV and ZR implemented in the meters. The essays are over with the timers or counters global buses connected, the front used all the necessary lines independently included (see Chapter 5 Timers and Counters).

The core of the byte-oriented control consists of an arithmetic-logic processing unit (ALU) and two series-connected accumulators (A1 and A2).

The rotating operations SLW and SRW are carried out directly in battery 1 , which is designed as a shift register. For the arithmetic operations + F, -F, D, I and KZW, the logical operations UW, OW, XOW and KEW and the comparison operations! = F, << F, <F, <= F, <F and <= F the ALU is used. The result of the arithmetic or logical operations is led from the ALU into the battery 1 . In the comparison operations, only the lines C (carry) and Z (zero) are important as a result of the ALU. Depending on the comparison operation, they are linked to one another and fed to the bit-oriented control as a RLO.

In the loading operations L DL, L DR and L DW, data is loaded directly from the data memory into the battery 1 . With the transfer operations T DL, T DR and T DW, however, the data from the battery 1 must be transferred to the data memory by the ALU. The timers and counters can be charged directly from battery 1 . With the loading operations L T1 and L Z1, the current timer or counter readings can be recharged into the battery 1 .

The control unit is one of the application-specific hard-wired components (see Chapter 4). It coordinates the process in the byte-oriented controller by switching connections, such as from the battery 1 through the ALU to the data memory. It also produces all control lines, meter readings for the micro program counter (µPc) and addresses for the data memory. It only has the micro program counter as input.

The micro program counter (µPc) with a downstream decoder (D) is increased by one for each cycle elevated. At the end of each cycle, the control unit loads it again with zero. At micro clock The states of all inputs are read in zero and the output image to the outputs switched through. The input image and the states of the outputs can be viewed during a Cycle remain constant. The other micro clocks activate the correct logic circuits of the bit-oriented control.

The decoder has the current status of the micro program counter as an input signal. At the exit he sets the corresponding micro clock line to high. There is only ever one micro clock line High.  

In order to be able to call subordinate program blocks and function blocks, a stack is created used, which saves the current status of the micro program counter with each block call and a continuation of the superordinate component when the subordinate component is terminated enables.

4 The application-specific hard-wired control unit

The application-specific hard-wired control unit is a purely combinatorial circuit. she has only one input: the micro program counter (µPc). Their outputs are accurate in Table 3 described. The number of outputs is variable since one for each timer and for each counter another readout signal is required (LT1,..., LTn, LZ1,..., Lzm).

Table 3

Control unit inputs and outputs

The switching network of the application-specific hard-wired control unit is shown on a scoreboard created from the STEP5 program. An example of this table of values is shown in Table 4.

Table 4

Control unit scoreboard

As can be seen in Table 4, an operation in the byte-oriented does not have to be carried out in every micro clock cycle Control. There are also operations in bit-oriented control executed.

5 timers and counters Timer attachments

Figure 4 in the appendix shows the timer attachments in the bit-oriented controller for the STEP5 operations SI, SE, SV, SA, SS and R.

To control a timer attachment, a logic result is generated in the bit-oriented control ( Fig. 2, 1). The rising edge (SI, SE, SV and SS) or the falling edge (SA) is evaluated by this within the timer attachment at the correct micro clock. The timer is reset (R) independently of the edge. At its output, the timer attachment indicates when the timer is in the soft state. The output is fed to the state memory ( 3 ) without further logic circuitry via the multiplexer ( 2 ) controlled by the micro clock.

timer

When the timer is loaded, the accumulator transfers 10 bits to the counter. Two more bits indicate which frequency the enable line of the timer should have. You will be loading the Buffered timers in D flip-flops and select the enableline via a multiplexer.

Loading the timer requires a micro clock; and to determine the status of the timer and buffer it in the status memory, another micro clock is required (see Chapter 2, Additional Clock Cycles). The current timer status can be loaded into battery 1 (L).

In the STEP5 programming language it is possible to use the same timer several times with different ones Call STEP5 operations. In such cases, the connections from the timer attachments linked to the timer with OR gates. In this way, the last one activated Timer attachment with setting or resetting the timer.

Counter tops

Figure 5 in the appendix shows the counter attachments in the bit-oriented controller for the STEP5 operations S, R, ZV and ZR. Here, too, a logic result is generated in the bit-oriented control ( 1 ) to control the counter top, and the rising edge of the VKE (ZV and ZR) is evaluated within the counter top with the correct micro clock. The counter is set (S) and reset (R) independently of the edge. At its output, the counter top indicates the soft state of the counter. The output is fed to the state memory ( 3 ) without further logic circuitry via the multiplexer ( 2 ) controlled by the micro clock.

counter

As with the timer, 10 bits are transferred from the accumulator to the counter when the counter is loaded. The meter loading requires a micro clock; and to determine the state of the counter and buffer it in the state memory, another micro clock is required (see Chapter 2, Additional Clock Cycles). The current meter reading can be loaded into battery 1 (L).

6 hierarchy levels

STEP5 programs are divided into several blocks for clear structuring. A STEP5 program contains the organization block OB1, which is called cyclically in which the program blocks PB1, PB2,. . . be called. Function blocks (FB) contain program parts that are often used. Figure 6 shows an example of a clearly structured STEP5 program. Two different ways of implementing a STEP5 program of this type are presented below.

"Flattening" of the hierarchy levels

With this procedure, the subordinate program and function blocks are completely in embedded in the higher-level building blocks. This is possible with STEP5 programs because within only the same number of blocks can be called in a program cycle (none Recursions possible). If a function block is called several times in the STEP5 program, then it is also implemented several times. This leads to a relatively extensive control.

Using a stack

When a subordinate program or function block is called, the current count of the microprogram counter (see Fig. 1, µPc) is written to the stack. Now the subordinate block is processed. The old count of the microprogram counter is then retrieved from the stack and the higher-level block is continued.

The stack is a storage area that is independent of the data storage and is directly accessible from a special one Stack pointer register can be addressed from. This makes stack accesses in just two micro-cycles possible.  

7 Example of the implementation of a STEP5 program in an application-specific hard-wired control

The state graph from Figure 7 is to be implemented.

The assignment list for the flags, inputs and outputs is shown in Table 5:

Table 5

Allocation list

The STEP5 program in Table 6 results.

Table 6

STEP5 program

The application-specific hard-wired control implemented according to the specified procedure looks as follows:

• - Application-specific hard-wired bit-oriented control see Figure 8,
• - For fixed components of the byte-oriented control, see Fig. 9 and
• - application-specific hard-wired control unit see table 7.

Table 7

Application-specific hard-wired control unit

Claims (21)

1. Programmable controller for connecting sensors such as. B. buttons, switches, temperature, pressure and inductive sensors and actuators such. B. motors, valves and signaling devices with a bit-oriented control and a byte-oriented control consisting of control unit, computing unit, registers and memory, characterized in that the bit-oriented control is hard-wired for specific applications. 2. Programmable controller for connecting sensors such as. B. buttons, switches, Temperature, pressure and inductive sensors and actuators such as B. engines, valves and Signaling devices with a bit-oriented control and a byte-oriented control consisting of control unit, computing unit, registers and memory, characterized, that the control unit contained in the byte-oriented controller is application-specific is hardwired. 3. Programmable controller for connecting sensors such as. B. buttons, switches, Temperature, pressure and inductive sensors and actuators such as B. engines, valves and Signaling devices with a bit-oriented control and a byte-oriented control consisting of control unit, computing unit, registers and memory, characterized, that both the bit-oriented control and that in the byte-oriented control included control unit completely housed in a programmable logic module are. 4. Control according to claim 1 and 2, characterized in that both the bit-oriented Control as well as the control unit contained in the byte-oriented control are hard-wired for specific users. 5. Control according to claim 1, characterized, that the bit-oriented control is housed in a programmable logic module. 6. Control according to claim 2, characterized, that the control unit contained in the byte-oriented controller in one programmable logic module is housed.   7. Control according to claim 1 and 2, characterized, that both the bit-oriented control and that in the byte-oriented control included control unit completely housed in a programmable logic module are. 8. Control according to claim 3, 4, 5 or 6, characterized, that the programmable logic module is an FPGA (field programmable gate field), CPLD (complex programmable logic device) or an EPROM (erasable Programmable read-only memory). 9. Control according to claim 1, characterized, that a counter with a decoder connected the selection line (micro clock line) active logic subcircuit of the bit-oriented controller. 10. Control according to claim 1, characterized, that parallel logic structures are present in the bit-oriented controller. 11. Control according to claim 2, characterized, that the timers contained in the byte-oriented controller have fixed components have the same configurations. 12. Control according to claim 2, characterized, that the counters contained in the byte-oriented controller have fixed components that have the same configurations. 13. Control according to claim 1, characterized in that the bit-oriented control both is structured in parallel as well as sequentially. 14. Method for operating a programmable controller according to one or more of the above claims, characterized, that the bit-oriented controller is hard-wired for specific applications.   15. A method of operating a programmable controller according to one or more of the above claims, characterized, that the control unit contained in the byte-oriented controller is application-specific is hardwired. 16. A method of operating a programmable controller according to one or more of the above claims, characterized, that both bit-oriented and those contained in the byte-oriented control Control unit are housed in a programmable logic module. 17. The method according to claim 12 to 14, characterized, that the overall functional behavior of the programmable controller in the program language for programmable logic controllers STEP5 is specified. 18. The method according to claim 15, characterized, that the overall functional behavior of the programmable controller in the hardware description language (VHDL) is implemented. 19. The method according to claim 16, characterized, that the overall functional behavior of the programmable controller in a network list is implemented. 20. The method according to claim 16, that a further logic subcircuit in the bit-oriented control is started and this when closing the bracket to the preceding logic subcircuit is added. 21. The method according to claim 17, characterized, that in the bit-oriented control the structure after set (S), reset (R) or Assign (=) is used again.